FR2572612A1 - Interface between video decoder and television receiver - Google Patents

Abstract

Interface device receiving video signals from a peripheral receiving coded television signals, characterised in that the signals are received on a synchronisation-video separator and on a line detector, the said separator being followed by a line-frequency oscillator and by a test card generator connected to the receiver to permit adjustment to the modulation thereof, the said line detector selecting the chrominance signals of one type and being followed by a circuit having half line frequency and reset, connected to the line frequency oscillator, as well as an oscillator operating at the limiting frequencies of deflection and which emits frame-identifying signals, the said synchronisation-video separator also being connected downstream, on the one hand to a monostable connected to the line detector and to the switching control for the frame-identifying signals, and on the other hand to a frame synchronising circuit associated with a counting circuit connected to the line frequency oscillator, actuating the control of the frame identification and emitting on the test lines.

Description

INTERFACE BETWEEN VIDEO DECODER AND
TELEVISION RECEIVER
The present invention relates to interface devices intended to ensure the connection between a peripheral receiver of coded television broadcasts and a television receiver not equipped with systems for adapting to the reception of such broadcasts, and in particular connection sockets. to such devices for receiving encoded television broadcasts.

 The present invention is particularly suitable for special-pay coded television systems as designed on the basis of the SECAM system. Furthermore, in the current state of things, even on receivers equipped with such sockets for television peripherals, we come up against certain other impossibilities: for example it is not possible for the spectator to watch a program and to simultaneously record another when it operates this type of device.

 In addition, in this type of transmission of coded signals, certain modifications to the standards of the SECAM system have been made which require a restoration of what has been modified or even deleted (in particular the frame identification signals).

 It should be remembered that according to the SECAM color television system the chrominance information of a line (RY) for red and (BY) for blue is transmitted sequentially so that on reception part of the signals is put in memory during the reception of the other signals which makes it possible to process all the information simultaneously. Thus, in a SECAM encoder, an electronic switch alternately selects the chrominance signals in red and in blue at the line scan frequency. For a given frame, if the line corresponds to red, the next line n + 2 corresponds to blue, while in the next frame due to interlacing, red corresponds to n + 1 and blue to n + 3 .

In practice, two frequency subcarriers are used:
f0R = 4.406 250 MHz = 282 fL for red and
fOB = 4,250,000 MHz = 272 fL for blue, being the line frequency, i.e. 15,625 Hz.

 This takes into account the fact that it is possible to insert the lateral chrominance bands between the harmonics of the luminance signal.

The signals modulating the subcarriers deriving from the chrominance signals are weighted differently so that in the absence of preaccentuation, the derivation associated with the RY modulation exceeds that of
BY in a given ratio, the deviation limit frequencies being 4.756 250 MHz and 3.900 000 MHz. This pre-emphasis of the high frequency components of the chrominance spectrum makes it possible to increase the signal / noise ratio.

 In the receivers, after separation of the audio and video signals, the chrominance components are oriented towards their respective demodulation and decoding channels, a bell circuit (fo = 4.286 MHz) compensating for the modulation of the emission bell circuit which gives at the subcarrier a variable level as a function or of the amplitude of the modulation signal to preserve the advantages of frequency modulation with regard to noise and color drift, in particular for the components of the chrominance signals above 400 KHz.

 According to these prior techniques, upon reception, the orientation of the signals is ensured by means of the signals or identification lines (nine in number) which allow the blocking of the chrominance channel when these signals are not on that corresponding to their color.

These identification signals modulate the subcarrier and are emitted during the frame suppression stage which follows the equalization pulses. They are received by a particular circuit at the same time as the frame return pulses.

 Thus, during the backward landing of each line blanking interval, after the line synchronization pulse, the subcarrier is reintroduced at the rest frequency corresponding to the chrominance signal of the following horizontal scan.

 During each frame blanking interval, the subcarrier is deleted except during the line identification signal transmitted during the nine identification lines, after the balancing pulses, which leaves some line intervals free for the test signals of frame before resuming video signals. These intervals correspond to lines 16 to 20 of the frames of one parity, 329 to 333 of the frames of the other parity.

The frame identification BY line begins at the frequency f0B for the duration of the reverse stop, then the frequency decreases to 3,900 MHz, then the RY line begins at the frequency f0R for the duration of the reverse stop, then the frequency increases to 4.756 MHz.

During the other identification lines, interspersed with the first, the RY identification is transmitted upon the reappearance of the subcarrier at the frequency f0R, followed by a linear increase in the frequency of the subcarrier up to 4.765 MHz which is maintained for the rest of the identification line.

 In the particular case which concerns the present invention, in certain types of transmission, the frame identification signals are eliminated in order to replace them with certain additional information lines, which poses restoration problems when the reception receiver is not provided for this purpose.

 In recent years, television transmission systems have appeared using special channels requiring special decoding, in particular for specific marketing purposes, a payment, subscription or prepayment giving access to the code and thus allowing decoding on the receiver. However, this must be fitted with a socket suitable for this type of television device, which is only the case for new receivers in countries which have adopted such a system.

 The object of the present invention is to enable conventional color television receivers, not equipped with such adaptation devices, to connect the decoder apparatus thereto by means of an interface device according to the invention which can be connected to the receiver antenna socket.

In addition, the invention provides a solution to several other problems:
- The trend is for improved performance in
automatic gain control material. This problem may be
resolved, according to the invention and as will be seen below, in
using test lines 16 to 20 and 329 to 333 above
defined.

- The user experiences difficulties in adjusting both
different devices considered, what the invention
facilitates thanks to a pattern generator allowing adjustment
from the receiver to the modulator and then to the desired channel.

- The frame identification signals being, as has been
mentioned above, deleted to allow other opera
tions, especially in the case of the so-called ANTIOPE system,
should be restored what the invention allows by
marking with respect to the line identification signals.

The interface devices in accordance with the present invention provide a simple and convenient solution to all of these problems.

 The present invention uses interface devices receiving the video signals from the reception part on a synchronization separator and a line detector, said separator being followed by a line frequency oscillator and a test pattern generator for adjusting the receiver. on the detector, and said line detector being followed by a time reset and half-line frequency circuit, an oscillator stalls on the deviation limit frequencies and the as tation of the frame identification signals, said synchronization separator being connected downstream on the one hand to a monostable actuating the line detector and a control switching the frame identification signals, and on the other hand to a frame synchronization circuit followed by a counting device actuating the frame identification command, this counting device and the time and half-line frequency reset circuit being connected upstream to the line frequency oscillator, the counting device transmitting its frame synchronization signals on test lines.

To better understand the technical characteristics and advantages of the present invention, we will describe an embodiment and variants thereof, it being understood that these are not limiting as to their mode of implementation and to the applications which 'we can do it. We will refer to the following figures which schematically represent:
Figure 1 a block diagram of a device conforming to the
present invention;
figure 2 a more detailed diagram of this same example of
production;
Figure 3 a partial diagram illustrating a mode of use of
Figures 1 and 2,
figure 4 timing diagrams of device frequency signals
Figures 1 and 2 and
Figure 5 a partial diagram of another variant.

 Figure 1 very schematically shows an interface device according to the present invention.

The video signals coming from the special decoder device are brought on the one hand to a synchronization splitter on the other hand to a line detector; to fix the ideas, we will choose here the lines
RY. At the output of the splitter, the signals are oriented as will be explained in more detail below, some towards frame synchronization, others towards a monostable, others finally towards a line frequency oscillator via a stage d alignment on video signals. This oscillator is connected downstream to the test pattern generator, to a line and reset time half-frequency circuit and to a counting device. The monostable is also connected to the line detector. The line detector is also connected downstream to this line half-frequency circuit which is followed by an oscillator set to the limit frequencies 3.900 MHz and 4.756 MHz, transmitting the signals frame identification. A frame identification command connected upstream to the monostable and to the counting device, controls the output switching of the frame identification signals coming from the oscillator.

 The counting device emits signals at the time of the test lines: in the present example, lines 17 and 330 are chosen.

 The test pattern generator is equipped with a CM control which allows the operator to display the bar pattern and to adjust his receiver on the modulator and then on the desired channel.

 Referring to Figure 2, we find the blocks of Figure 1 with some additional details of construction.

 The separator is of any conventional type ensuring synchronization-video separation.

 The intermediate stage between this separator and the line frequency oscillator ensures alignment of said oscillator with the video signals. This oscillator can be of any type also conventional. In the example illustrated in FIG. 2, the two diodes of the alignment stage short-circuit when the test pattern placed downstream of the oscillator does not work. This operation is controlled by the grounding switch CM connected to this alignment stage as illustrated in FIG. 2, as well as to the monostable.

 The white bar target generator is constituted as shown in the figure, around two monostables, the reverse gates being, according to a preferred embodiment of the invention, of the CMOS type. The two doors in series improve the sharpness of the bars.

 Although the generator of white bars is sufficient, it would be possible to envisage any other type of target, either in white and black, or in colors.

 The line frequency oscillator is also connected to the CLK inputs of the flip-flops of the half-frequency and reset time circuit, and of the counting device. These last two have the same type of D-type flip-flop which, in the present example, can be the two halves of a logic circuit of the CD 4013 type for example, employing the CMOS technique. This ensures the synchronization of the assembly with the lines.

The mounting of the scale of the half-frequency circuit and resetting the time allows, thanks to the DQ connection and the grounding of S, on the one hand of course to divide the frequency by 2 (indeed at each impulse arriving in CLK one of the outputs goes to state 1 and the other to state O and vice versa), and on the other hand the reset to time in the event of an offset. We will return later to the operation of these devices. Furthermore in the counting device, the operation of the flip-flop D is of the same type, which brings a frequency half to the clock input of the other logic circuit used for counting which can be for example, according to one embodiment preferred of the invention, of the CD 4017 type (manufactured by National Semiconductors according to the technique
CMOS).

 On the other hand, the connection of the synchro-video separator to the synchro-frame separator ensures the reset of the logic circuits of the counting device.

 On two test lines - (here, for example, lines 17 and 330) signals from the output 40 of the CD 4017 and at positive voltage (Figure 2) are collected half the frequency of the lines.

This system makes it possible to avoid parasites in the counting. Furthermore, if the automatic gain control is not entirely exact, the synchronization tops not being clear, there is a risk of imbalance, but according to the present example, the oscillator ensures the catching up and the counting accuracy.

 CD 4017 type circuits provide counting by successive transmission of signals on their outputs.

 In the case of FIG. 2, the output 6 corresponding to "7" gives the location signals on test lines; connection 11 (corresponding to "9") -13 ensures inhibition which causes blocking until the arrival of a new pulse from 15 (R) of frame synchronization.

 The switches C indicated in FIG. 2 can be analog switches of the CMOS type which can be associated (quadruple switch).

 The output 4 (corresponding to "2") of the CD 4017 controls the frame regeneration by charging the capacity located downstream, which discharges under the action of the 7 (output 6) acting on the CI switch.

The voltage present on the capacity actuates the switch C4 which supplies the dual frequency oscillator which controls the line identification switching which switches to modulation.

 The composite video signals arriving at line detection pass through a high-pass filter at the input followed by a limitation amplifier with head-to-tail diodes. We thus know what is happening at the beginning of the line, the chrominance information being the only one present, which gives a signal of approximately constant amplitude. The following ceramic filter is chosen so that, for R-Y frame identification signals, the voltage amplitude is higher and, for B-Y, lower. The processing of these signals will be explained below with regard to the half-frequency and time-reset circuits.

 The synchro-video separator is also connected to the monostab-lece which gives pulses corresponding to the rear line identification bearings. This activates the line detection transistor R-Y thanks to the switch C2 and the very long time constant resistance-capacitance assembly.

 There is thus collected at the output of the line detector R-Y a positive pulse (DL) every other line.

 In the line and time-reset half-frequency circuit, the R input of the flip-flop is normally at state 0. As indicated above, the QD connection ensures that the frequency is divided by 2, which introduces a possible error of fi whence sampling by the signal SECAM. If the pulses coming from the line detection R-Y correspond to the falling edge of the rectangular signals Q, R remains in the state O (see FIG. 4a).

 If the pulses from the detection correspond to the rising edge of the Q signals (see Figure 6b) the voltage in R rises in steps and when it reaches a predetermined value, it triggers the flip which results in an immediate relapse of the signal Q and therefore the resetting of the time and the return of R to state 0, and this thanks to the diode d and to the capacitance K (FIG. 2).

 If spurious signals appear, this has no influence, because the voltage in R goes up one step and the diode d brings it back to 0 (Figure 4c). If a series of false pulses F appear at the output of the detection, there is a return to -O thanks to the diode at the appearance of the first pulse set V (FIG. 4c).

 Downstream from the line half-frequency circuit and resetting the time is connected the frame identification double frequency oscillator which the diode switches from one frequency to another.

 Various simplifications and variants can be made by those skilled in the art without departing from the scope of the invention.

 As illustrated in FIG. 5, it is possible to compose the line half-frequency circuit and reset the time using two D-type flip-flops, which simplifies its construction. One can use to do this two halves of a CD 4013 circuit with double rocker which also simplifies the counting by eliminating its rocker.

 The combination of the two diodes is used at the outputs of the logic circuits to obtain non-conduction and the signals at the time of lines 17 and 330. The video level on the base of the transistor is maximum which detects the peaks. This method takes into account only these lines 17 and 330 and, in the absence of these signals at the output of the logic circuits, the peak is taken over the whole of the video signal at a different frequency.

 In this way it is constantly ensured that the automatic gain control is not deactivated, which provides good balancing, the automatic gain control being ensured even if the signal is not positive.

 Referring to Figure 3, there is the video input, the automatic gain control input, the clipping being provided by the transistor. If you connect by an inverter 6 and 13 of the CD 4017 circuit, you lock on 6 and the automatic gain control works permanently, so that you can receive broadcasts on other codes and in particular broadcasts foreign.

Claims (6)

 1.- Interface device receiving video signals from a device for receiving coded television signals, characterized in that the signals are received on a synchronization-video separator and on a line detector, said separator being followed by a line frequency oscillator and a pattern generator connected to the receiver to allow adjustment on the modulation, said line detector selecting the chrominance signals of a type and being followed by a line and reset half frequency circuit at the time connected to the line frequency oscillator, as well as an oscillator working at the deflection limit frequencies which transmits the frame identification signals, said synchronization-video separator being also connected downstream, on the one hand to a monostable connected to the line detector and to the command to switch the frame identification signals, and on the other hand to a frame synchronization circuit associated with a counting circuit connected to the o line frequency scillator, activating the frame identification control and transmitting on the test lines.  2.- Device according to claim 1, characterized in that the synchronization-video separator is connected to the line frequency oscillator via an alignment stage on the video signals.  3.- Device according to one of claims 1 to 2, characterized in that the half-frequency and time-reset circuit is formed around at least one flip-flop receiving in line between CLK the line frequency signals which divides this line frequency by 2 thanks to a QD connection and ensures the reconciliation of the chrominance signals from the detector with the line frequency by eliminating parasites and by phase-shifting the phase shifted signals  4.- Device according to one of claims 1 to 3, characterized in that the counting device is constituted around a logic circuit transmitting sequentially on its outputs counting signals and controlled at its CLICK input from l line frequency oscillator, this logic circuit transmitting frame synchronization signals on test lines.  5.- Device according to one of claims 3 or 4, characterized in that it has a CD 4013 circuit as flip-flops.  6.- Device according to one of claims 4 or 5, characterized in that it uses a CD 4017 circuit for counting.