FR2545957B1 - - Google Patents
Info
- Publication number
- FR2545957B1 FR2545957B1 FR8307793A FR8307793A FR2545957B1 FR 2545957 B1 FR2545957 B1 FR 2545957B1 FR 8307793 A FR8307793 A FR 8307793A FR 8307793 A FR8307793 A FR 8307793A FR 2545957 B1 FR2545957 B1 FR 2545957B1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3884—Pipelining
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8307793A FR2545957A1 (en) | 1983-05-10 | 1983-05-10 | High-throughput binary multiplier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8307793A FR2545957A1 (en) | 1983-05-10 | 1983-05-10 | High-throughput binary multiplier |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2545957A1 FR2545957A1 (en) | 1984-11-16 |
FR2545957B1 true FR2545957B1 (en) | 1989-01-13 |
Family
ID=9288750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8307793A Granted FR2545957A1 (en) | 1983-05-10 | 1983-05-10 | High-throughput binary multiplier |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2545957A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2611286B1 (en) * | 1987-02-23 | 1989-04-21 | Dassault Electronique | MULTIPLIER INTEGRATED CIRCUIT, AND COMPOSITION METHOD THEREOF |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4189767A (en) * | 1978-06-05 | 1980-02-19 | Bell Telephone Laboratories, Incorporated | Accessing arrangement for interleaved modular memories |
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1983
- 1983-05-10 FR FR8307793A patent/FR2545957A1/en active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2545957A1 (en) | 1984-11-16 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |