FR2337398A1 - Dispositif d'ecriture rapide pour cellules de memoire - Google Patents
Dispositif d'ecriture rapide pour cellules de memoireInfo
- Publication number
- FR2337398A1 FR2337398A1 FR7540418A FR7540418A FR2337398A1 FR 2337398 A1 FR2337398 A1 FR 2337398A1 FR 7540418 A FR7540418 A FR 7540418A FR 7540418 A FR7540418 A FR 7540418A FR 2337398 A1 FR2337398 A1 FR 2337398A1
- Authority
- FR
- France
- Prior art keywords
- flops
- flip
- current consumption
- cross coupled
- coupled transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7540418A FR2337398A1 (fr) | 1975-12-30 | 1975-12-30 | Dispositif d'ecriture rapide pour cellules de memoire |
DE19762654460 DE2654460A1 (de) | 1975-12-30 | 1976-12-01 | Schaltung zur erhoehung der schreibgeschwindigkeit fuer speicherzellen |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7540418A FR2337398A1 (fr) | 1975-12-30 | 1975-12-30 | Dispositif d'ecriture rapide pour cellules de memoire |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2337398A1 true FR2337398A1 (fr) | 1977-07-29 |
FR2337398B1 FR2337398B1 (fr) | 1980-05-30 |
Family
ID=9164452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7540418A Granted FR2337398A1 (fr) | 1975-12-30 | 1975-12-30 | Dispositif d'ecriture rapide pour cellules de memoire |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE2654460A1 (fr) |
FR (1) | FR2337398A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0021143A2 (fr) * | 1979-06-28 | 1981-01-07 | International Business Machines Corporation | Procédé et circuit de sélection et de décharge des capacités de lignes de bit d'une mémoire à haute intégration à semi-conducteurs |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5570993A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Memory circuit |
SE9002558D0 (sv) * | 1990-08-02 | 1990-08-02 | Carlstedt Elektronik Ab | Processor |
-
1975
- 1975-12-30 FR FR7540418A patent/FR2337398A1/fr active Granted
-
1976
- 1976-12-01 DE DE19762654460 patent/DE2654460A1/de not_active Withdrawn
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0021143A2 (fr) * | 1979-06-28 | 1981-01-07 | International Business Machines Corporation | Procédé et circuit de sélection et de décharge des capacités de lignes de bit d'une mémoire à haute intégration à semi-conducteurs |
EP0021143A3 (en) * | 1979-06-28 | 1981-01-14 | International Business Machines Corporation | Method and circuit for discharging bit lines capacitances in an integrated semi-conductor memory, especially for the mtl technique |
Also Published As
Publication number | Publication date |
---|---|
DE2654460A1 (de) | 1977-07-07 |
FR2337398B1 (fr) | 1980-05-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |