FR2381354A1 - ADVANCED ANTI-MEMORY WRITING ABILITY - Google Patents
ADVANCED ANTI-MEMORY WRITING ABILITYInfo
- Publication number
- FR2381354A1 FR2381354A1 FR7804514A FR7804514A FR2381354A1 FR 2381354 A1 FR2381354 A1 FR 2381354A1 FR 7804514 A FR7804514 A FR 7804514A FR 7804514 A FR7804514 A FR 7804514A FR 2381354 A1 FR2381354 A1 FR 2381354A1
- Authority
- FR
- France
- Prior art keywords
- memory
- write
- auxiliary
- local
- control modules
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Storage Device Security (AREA)
Abstract
Système d'entrées-sorties à capacité d'écriture d'anti-mémoire perfectionnée. Le système comprend une unité d'interface de système possédant une pluralité de portes d'accès à l'un des modules d'une pluralité de modules de commande et à un module de mémoire locale du système. Le module de mémoire locale comprend une anti-mémoire, une mémoire auxiliaire et un circuit de commande. Des instructions de mémoire engendrées par l'un quelconque des modules de commande permettent à l'anti-mémoire d'accéder rapidement à des blocs d'informations préalablement extraits de la mémoire auxiliaire et d'inscrire en anti-mémoire des données dont l'écriture est commandée dans la mémoire auxiliaire quand il est établi que ces données ont été antérieurement mémorisées dans l'anti-mémoire. Application : accès rapide partagé à des informations de module de mémoire locale entre plusieurs unités terminales.Advanced anti-memory write capability I / O system. The system includes a system interface unit having a plurality of access doors to one of a plurality of control modules and to a local memory module of the system. The local memory module includes an anti-memory, an auxiliary memory, and a control circuit. Memory instructions generated by any of the control modules allow the anti-memory to quickly access blocks of information previously retrieved from the auxiliary memory and to write anti-memory data whose Write is commanded to the auxiliary memory when it is determined that this data has been previously stored in the anti-memory. Application: Quick shared access to local memory module information between multiple terminal units.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/769,617 US4084234A (en) | 1977-02-17 | 1977-02-17 | Cache write capacity |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2381354A1 true FR2381354A1 (en) | 1978-09-15 |
FR2381354B1 FR2381354B1 (en) | 1985-12-06 |
Family
ID=25085994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7804514A Expired FR2381354B1 (en) | 1977-02-17 | 1978-02-17 | IMPROVED CAPACITY FOR WRITING IN MEMORY |
Country Status (7)
Country | Link |
---|---|
US (1) | US4084234A (en) |
JP (1) | JPS53108747A (en) |
AU (1) | AU510793B2 (en) |
CA (1) | CA1106074A (en) |
DE (1) | DE2806045A1 (en) |
FR (1) | FR2381354B1 (en) |
GB (1) | GB1599837A (en) |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4142234A (en) * | 1977-11-28 | 1979-02-27 | International Business Machines Corporation | Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system |
US4354232A (en) * | 1977-12-16 | 1982-10-12 | Honeywell Information Systems Inc. | Cache memory command buffer circuit |
US4195340A (en) * | 1977-12-22 | 1980-03-25 | Honeywell Information Systems Inc. | First in first out activity queue for a cache store |
US4432050A (en) * | 1978-10-02 | 1984-02-14 | Honeywell Information Systems, Inc. | Data processing system write protection mechanism |
US4323968A (en) * | 1978-10-26 | 1982-04-06 | International Business Machines Corporation | Multilevel storage system having unitary control of data transfers |
US4268907A (en) * | 1979-01-22 | 1981-05-19 | Honeywell Information Systems Inc. | Cache unit bypass apparatus |
US4298929A (en) * | 1979-01-26 | 1981-11-03 | International Business Machines Corporation | Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability |
USRE36989E (en) * | 1979-10-18 | 2000-12-12 | Storage Technology Corporation | Virtual storage system and method |
US4386399A (en) * | 1980-04-25 | 1983-05-31 | Data General Corporation | Data processing system |
EP0039227A3 (en) * | 1980-04-25 | 1982-09-01 | Data General Corporation | Data processing system |
US4424561A (en) | 1980-12-31 | 1984-01-03 | Honeywell Information Systems Inc. | Odd/even bank structure for a cache memory |
US4434465A (en) | 1981-04-13 | 1984-02-28 | Texas Instruments Incorporated | Shared microinstruction states in control ROM addressing for a microcoded single chip microcomputer |
CA1183274A (en) * | 1981-05-08 | 1985-02-26 | Barry B. White | Virtual storage system and method |
US4490782A (en) * | 1981-06-05 | 1984-12-25 | International Business Machines Corporation | I/O Storage controller cache system with prefetch determined by requested record's position within data block |
US4410946A (en) * | 1981-06-15 | 1983-10-18 | International Business Machines Corporation | Cache extension to processor local storage |
US4464713A (en) * | 1981-08-17 | 1984-08-07 | International Business Machines Corporation | Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store |
US4467417A (en) * | 1981-09-16 | 1984-08-21 | Honeywell Information Systems Inc. | Flexible logic transfer and instruction decoding system |
US4466059A (en) * | 1981-10-15 | 1984-08-14 | International Business Machines Corporation | Method and apparatus for limiting data occupancy in a cache |
US4500954A (en) * | 1981-10-15 | 1985-02-19 | International Business Machines Corporation | Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass |
JPS59136859A (en) * | 1983-01-27 | 1984-08-06 | Nec Corp | Buffer controller |
US4587610A (en) * | 1984-02-10 | 1986-05-06 | Prime Computer, Inc. | Address translation systems for high speed computer memories |
US4680702A (en) * | 1984-04-27 | 1987-07-14 | Honeywell Information Systems Inc. | Merge control apparatus for a store into cache of a data processing system |
JPH0616272B2 (en) * | 1984-06-27 | 1994-03-02 | 株式会社日立製作所 | Memory access control method |
JPS6167156A (en) * | 1984-09-07 | 1986-04-07 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Data reading/altering apparatus |
US4941088A (en) * | 1985-02-05 | 1990-07-10 | Digital Equipment Corporation | Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses |
AU5634086A (en) * | 1985-05-06 | 1986-11-13 | Wang Laboratories, Inc. | Information processing system with enhanced instruction execution and support control |
US4768148A (en) * | 1986-06-27 | 1988-08-30 | Honeywell Bull Inc. | Read in process memory apparatus |
ATE63011T1 (en) * | 1987-02-16 | 1991-05-15 | Siemens Ag | METHOD FOR CONTROLLING THE DATA EXCHANGE BETWEEN PROCESSING UNITS AND A STORAGE SYSTEM WITH CACHE MEMORY IN DATA PROCESSING EQUIPMENT, AND A CORRESPONDENTLY WORKING CACHE MEMORY. |
US4953077A (en) * | 1987-05-15 | 1990-08-28 | International Business Machines Corporation | Accelerated data transfer mechanism using modified clock cycle |
US4939641A (en) * | 1988-06-30 | 1990-07-03 | Wang Laboratories, Inc. | Multi-processor system with cache memories |
JP2826857B2 (en) * | 1989-12-13 | 1998-11-18 | 株式会社日立製作所 | Cache control method and control device |
US5251310A (en) * | 1990-06-29 | 1993-10-05 | Digital Equipment Corporation | Method and apparatus for exchanging blocks of information between a cache memory and a main memory |
US5426771A (en) * | 1992-07-14 | 1995-06-20 | Hewlett-Packard Company | System and method for performing high-sped cache memory writes |
JP2675981B2 (en) * | 1993-09-20 | 1997-11-12 | インターナショナル・ビジネス・マシーンズ・コーポレイション | How to avoid snoop push operations |
US5603046A (en) * | 1993-11-02 | 1997-02-11 | Motorola Inc. | Method for complex data movement in a multi-processor data processing system |
JP3724001B2 (en) * | 1994-12-12 | 2005-12-07 | 富士通株式会社 | Information processing device |
US5960453A (en) | 1996-06-13 | 1999-09-28 | Micron Technology, Inc. | Word selection logic to implement an 80 or 96-bit cache SRAM |
US5862154A (en) | 1997-01-03 | 1999-01-19 | Micron Technology, Inc. | Variable bit width cache memory architecture |
US6658526B2 (en) | 1997-03-12 | 2003-12-02 | Storage Technology Corporation | Network attached virtual data storage subsystem |
WO1998040810A2 (en) | 1997-03-12 | 1998-09-17 | Storage Technology Corporation | Network attached virtual tape data storage subsystem |
US6094605A (en) * | 1998-07-06 | 2000-07-25 | Storage Technology Corporation | Virtual automated cartridge system |
US6330621B1 (en) | 1999-01-15 | 2001-12-11 | Storage Technology Corporation | Intelligent data storage manager |
US6629262B1 (en) * | 1999-09-30 | 2003-09-30 | Toshiba Tec Kabushiki Kaisha | Multiplexed storage controlling device |
US6834324B1 (en) | 2000-04-10 | 2004-12-21 | Storage Technology Corporation | System and method for virtual tape volumes |
US20030126132A1 (en) * | 2001-12-27 | 2003-07-03 | Kavuri Ravi K. | Virtual volume management system and method |
US7017006B2 (en) * | 2003-04-28 | 2006-03-21 | Texas Instruments Incorporated | System and method to enable efficient communication with a dynamic information storage and retrieval system, or the like |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3588839A (en) * | 1969-01-15 | 1971-06-28 | Ibm | Hierarchical memory updating system |
FR2202611A5 (en) * | 1972-10-05 | 1974-05-03 | Honeywell Inf Systems | |
FR2238191A1 (en) * | 1973-07-19 | 1975-02-14 | Int Computers Ltd | |
FR2260830A1 (en) * | 1974-02-09 | 1975-09-05 | Philips Nv | |
FR2305792A1 (en) * | 1975-03-26 | 1976-10-22 | Honeywell Inf Systems | DIRECTION CODE GENERATOR SYSTEM FOR AN INPUT / OUTPUT PROCESSING SYSTEM |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3588829A (en) * | 1968-11-14 | 1971-06-28 | Ibm | Integrated memory system with block transfer to a buffer store |
GB1432835A (en) * | 1972-07-03 | 1976-04-22 | Ibm | Data storage system |
US3820078A (en) * | 1972-10-05 | 1974-06-25 | Honeywell Inf Systems | Multi-level storage system having a buffer store with variable mapping modes |
US3806888A (en) * | 1972-12-04 | 1974-04-23 | Ibm | Hierarchial memory system |
US3911401A (en) * | 1973-06-04 | 1975-10-07 | Ibm | Hierarchial memory/storage system for an electronic computer |
US3896419A (en) * | 1974-01-17 | 1975-07-22 | Honeywell Inf Systems | Cache memory store in a processor of a data processing system |
-
1977
- 1977-02-17 US US05/769,617 patent/US4084234A/en not_active Expired - Lifetime
-
1978
- 1978-01-23 CA CA295,430A patent/CA1106074A/en not_active Expired
- 1978-02-13 AU AU33249/78A patent/AU510793B2/en not_active Expired
- 1978-02-14 DE DE19782806045 patent/DE2806045A1/en not_active Withdrawn
- 1978-02-16 GB GB6192/78A patent/GB1599837A/en not_active Expired
- 1978-02-17 FR FR7804514A patent/FR2381354B1/en not_active Expired
- 1978-02-17 JP JP1751578A patent/JPS53108747A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3588839A (en) * | 1969-01-15 | 1971-06-28 | Ibm | Hierarchical memory updating system |
FR2202611A5 (en) * | 1972-10-05 | 1974-05-03 | Honeywell Inf Systems | |
FR2238191A1 (en) * | 1973-07-19 | 1975-02-14 | Int Computers Ltd | |
FR2260830A1 (en) * | 1974-02-09 | 1975-09-05 | Philips Nv | |
FR2305792A1 (en) * | 1975-03-26 | 1976-10-22 | Honeywell Inf Systems | DIRECTION CODE GENERATOR SYSTEM FOR AN INPUT / OUTPUT PROCESSING SYSTEM |
Also Published As
Publication number | Publication date |
---|---|
US4084234A (en) | 1978-04-11 |
DE2806045A1 (en) | 1978-08-24 |
GB1599837A (en) | 1981-10-07 |
CA1106074A (en) | 1981-07-28 |
AU510793B2 (en) | 1980-07-10 |
FR2381354B1 (en) | 1985-12-06 |
AU3324978A (en) | 1979-08-23 |
JPS53108747A (en) | 1978-09-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |