FR1400731A - Two-level inverter circuit - Google Patents
Two-level inverter circuitInfo
- Publication number
- FR1400731A FR1400731A FR977117A FR977117A FR1400731A FR 1400731 A FR1400731 A FR 1400731A FR 977117 A FR977117 A FR 977117A FR 977117 A FR977117 A FR 977117A FR 1400731 A FR1400731 A FR 1400731A
- Authority
- FR
- France
- Prior art keywords
- inverter circuit
- level inverter
- level
- circuit
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/084—Diode-transistor logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR977117A FR1400731A (en) | 1963-06-04 | 1964-06-04 | Two-level inverter circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US285493A US3299363A (en) | 1963-06-04 | 1963-06-04 | Phase inverting direct current amplifier circuit |
FR977117A FR1400731A (en) | 1963-06-04 | 1964-06-04 | Two-level inverter circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1400731A true FR1400731A (en) | 1965-05-28 |
Family
ID=26208097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR977117A Expired FR1400731A (en) | 1963-06-04 | 1964-06-04 | Two-level inverter circuit |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR1400731A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1286097B (en) * | 1965-10-28 | 1969-01-02 | Ncr Co | Temperature stable, interference voltage insensitive, fast switching logic circuit for execution in integrated circuit technology |
EP0344613A2 (en) * | 1988-06-03 | 1989-12-06 | National Semiconductor Corporation | TTL current sinking circuit with transient performance enhancement during output transition from high to low |
-
1964
- 1964-06-04 FR FR977117A patent/FR1400731A/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1286097B (en) * | 1965-10-28 | 1969-01-02 | Ncr Co | Temperature stable, interference voltage insensitive, fast switching logic circuit for execution in integrated circuit technology |
EP0344613A2 (en) * | 1988-06-03 | 1989-12-06 | National Semiconductor Corporation | TTL current sinking circuit with transient performance enhancement during output transition from high to low |
EP0344613A3 (en) * | 1988-06-03 | 1991-02-06 | National Semiconductor Corporation | Ttl current sinking circuit with transient performance enhancement during output transition from high to low |
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