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ES475088A1 - Decoder for binary coded data - Google Patents

Decoder for binary coded data

Info

Publication number
ES475088A1
ES475088A1 ES475088A ES475088A ES475088A1 ES 475088 A1 ES475088 A1 ES 475088A1 ES 475088 A ES475088 A ES 475088A ES 475088 A ES475088 A ES 475088A ES 475088 A1 ES475088 A1 ES 475088A1
Authority
ES
Spain
Prior art keywords
type
transitions
decoder
local clock
coded data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES475088A
Other languages
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Safran Electrical and Power SAS
Precision Mecanique Labinal SA
Original Assignee
Labinal SA
Precision Mecanique Labinal SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Labinal SA, Precision Mecanique Labinal SA filed Critical Labinal SA
Publication of ES475088A1 publication Critical patent/ES475088A1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

A decoder for recovering data received as a signal having phase transitions of a first type at the frequency of a transmission clock and, in the time intervals between transitions of the first type, second type transitions representative of the data comprises a local clock 16 having a frequency higher than that of the transmission clock. The number n1 of pulses of the local clock between two successive first type transitions is counted and those second type transitions which occur during time intervals corresponding to a number n2 of periods of the local clock such as n1/2 <n2 <n1 are detected by an arrangement including a down counter 24 which is loaded with the number n1 and which counts down at a speed double that of counter 21.
ES475088A 1977-11-02 1978-11-02 Decoder for binary coded data Expired ES475088A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7732908A FR2408255A1 (en) 1977-11-02 1977-11-02 IMPROVEMENTS TO THE METHODS AND SYSTEMS FOR THE RESTITUTION OF INFORMATION

Publications (1)

Publication Number Publication Date
ES475088A1 true ES475088A1 (en) 1979-04-01

Family

ID=9197150

Family Applications (1)

Application Number Title Priority Date Filing Date
ES475088A Expired ES475088A1 (en) 1977-11-02 1978-11-02 Decoder for binary coded data

Country Status (5)

Country Link
DE (1) DE2847149C3 (en)
ES (1) ES475088A1 (en)
FR (1) FR2408255A1 (en)
GB (1) GB2007944B (en)
IT (1) IT1099896B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380761A (en) 1980-02-04 1983-04-19 Xerox Corporation Digital phase decoder with collision detection
DE3172394D1 (en) * 1980-02-04 1985-10-31 Xerox Corp Data communication system
EP0087664B1 (en) * 1980-02-04 1985-09-11 Xerox Corporation Phase decoder for data communication systems
EP1721406A1 (en) * 2004-02-27 2006-11-15 Koninklijke Philips Electronics N.V. Reset circuit, data carrier and communication device

Also Published As

Publication number Publication date
IT7829357A0 (en) 1978-11-02
IT1099896B (en) 1985-09-28
GB2007944A (en) 1979-05-23
DE2847149B2 (en) 1980-04-24
GB2007944B (en) 1982-04-21
FR2408255A1 (en) 1979-06-01
DE2847149A1 (en) 1979-05-03
FR2408255B1 (en) 1981-08-07
DE2847149C3 (en) 1981-01-08

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