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EP3617914A4 - Vehicle control system validation technique and validation device, and control device - Google Patents

Vehicle control system validation technique and validation device, and control device Download PDF

Info

Publication number
EP3617914A4
EP3617914A4 EP18791883.4A EP18791883A EP3617914A4 EP 3617914 A4 EP3617914 A4 EP 3617914A4 EP 18791883 A EP18791883 A EP 18791883A EP 3617914 A4 EP3617914 A4 EP 3617914A4
Authority
EP
European Patent Office
Prior art keywords
validation
control system
technique
vehicle control
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP18791883.4A
Other languages
German (de)
French (fr)
Other versions
EP3617914B1 (en
EP3617914A1 (en
Inventor
Satoshi Otsuka
Kohei Sakurai
Fumio Narisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Astemo Ltd
Original Assignee
Hitachi Automotive Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Automotive Systems Ltd filed Critical Hitachi Automotive Systems Ltd
Publication of EP3617914A1 publication Critical patent/EP3617914A1/en
Publication of EP3617914A4 publication Critical patent/EP3617914A4/en
Application granted granted Critical
Publication of EP3617914B1 publication Critical patent/EP3617914B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40267—Bus for use in transportation systems
    • H04L2012/40273—Bus for use in transportation systems the transportation system being a vehicle

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Debugging And Monitoring (AREA)
  • Small-Scale Networks (AREA)
EP18791883.4A 2017-04-27 2018-04-12 Vehicle control system validation technique and validation device, and control device Active EP3617914B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017087824A JP6890460B2 (en) 2017-04-27 2017-04-27 Vehicle control system verification method and verification device and control device
PCT/JP2018/015329 WO2018198783A1 (en) 2017-04-27 2018-04-12 Vehicle control system validation technique and validation device, and control device

Publications (3)

Publication Number Publication Date
EP3617914A1 EP3617914A1 (en) 2020-03-04
EP3617914A4 true EP3617914A4 (en) 2021-01-27
EP3617914B1 EP3617914B1 (en) 2023-09-06

Family

ID=63919700

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18791883.4A Active EP3617914B1 (en) 2017-04-27 2018-04-12 Vehicle control system validation technique and validation device, and control device

Country Status (5)

Country Link
US (1) US11372442B2 (en)
EP (1) EP3617914B1 (en)
JP (1) JP6890460B2 (en)
CN (1) CN110574027B (en)
WO (1) WO2018198783A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019203251B3 (en) 2019-03-11 2020-06-18 Volkswagen Aktiengesellschaft Process and system for safe signal manipulation for testing integrated safety functionalities
JP7495890B2 (en) * 2021-02-15 2024-06-05 日立Astemo株式会社 In-vehicle computer system and automated driving assistance system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050289492A1 (en) * 2004-06-29 2005-12-29 Oki Electric Co., Ltd. Method of LSI designing and a computer program for designing LSIs
US20160321037A1 (en) * 2015-04-28 2016-11-03 Renesas Electronics Corporation Performance verification device for verifying performance of program, method, and recording medium having program recorded thereon for causing computer to perform the method

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581738A (en) * 1993-06-07 1996-12-03 Xilinx, Inc. Method and apparatus for back-annotating timing constraints into simulation models of field programmable gate arrays
JP2967762B2 (en) 1997-06-06 1999-10-25 日本電気株式会社 Circuit layout method
US6396814B1 (en) * 1997-09-12 2002-05-28 Kabushiki Kaisha Toshiba Network construction method and communication system for communicating between different groups via representative device of each group
US6453451B1 (en) * 2000-10-02 2002-09-17 Lsi Logic Corporation Generating standard delay format files with conditional path delay for designing integrated circuits
EP1449126A4 (en) * 2001-08-29 2008-01-16 Infineon Technologies Ag Integrated circuit chip design
JP2004054756A (en) * 2002-07-23 2004-02-19 Nec Electronics Corp Power consumption estimation device and method
US7739095B2 (en) * 2007-03-13 2010-06-15 Synopsys, Inc. Method for determining best and worst cases for interconnects in timing analysis
JP2014102734A (en) * 2012-11-21 2014-06-05 Renesas Electronics Corp Performance verification program, performance verification method, and performance verification device
US9882705B2 (en) * 2014-05-23 2018-01-30 Mitsubishi Electric Corporation Communication apparatus, communication method, and computer readable medium using propagation delay for time synchronization
JP6248008B2 (en) * 2014-07-29 2017-12-13 日立オートモティブシステムズ株式会社 Software verification system and control device
WO2016017111A1 (en) * 2014-08-01 2016-02-04 日本電気株式会社 Information processing system and system designing method
US10235171B2 (en) * 2016-12-27 2019-03-19 Intel Corporation Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processor
US10607039B1 (en) * 2017-11-27 2020-03-31 Cadence Design Systems, Inc. Constrained metric optimization of a system on chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050289492A1 (en) * 2004-06-29 2005-12-29 Oki Electric Co., Ltd. Method of LSI designing and a computer program for designing LSIs
US20160321037A1 (en) * 2015-04-28 2016-11-03 Renesas Electronics Corporation Performance verification device for verifying performance of program, method, and recording medium having program recorded thereon for causing computer to perform the method

Also Published As

Publication number Publication date
JP6890460B2 (en) 2021-06-18
JP2018185244A (en) 2018-11-22
EP3617914B1 (en) 2023-09-06
CN110574027A (en) 2019-12-13
US11372442B2 (en) 2022-06-28
CN110574027B (en) 2023-10-03
EP3617914A1 (en) 2020-03-04
US20210165444A1 (en) 2021-06-03
WO2018198783A1 (en) 2018-11-01

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