EP3443369B1 - System and method for testing an integrated circuit - Google Patents

Description

The present invention relates generally to integrated circuits, and in particular to a system and method for testing an integrated circuit.

The manufacturing of electronic components requires extremely complex processes. In addition, the manufacture of such components requires a complex and expensive infrastructure, such as factories of the foundry type for manufacturing the integrated circuits of these electronic components from silicon and on the basis of masks.

The miniaturization of transistors in the manufacturing process of integrated circuits has made it possible to produce faster, less energy-consuming and less expensive integrated circuits for the same function. However, this technique reduces the reliability of the transistors and therefore the overall reliability of the integrated circuit.

The reliability of integrated circuits can vary depending on the technology used. For example, the function performed by the integrated circuit with a 28nm manufacturing technology may break down earlier during its use than with a 40nm technology or another more obsolete technology (65nm for example). In addition, the lifespan of electronic products tends to decrease with the progress of miniaturization. This trend is a major obstacle for on-board electronic systems, for example in the automotive, avionics and defense industries. Such embedded systems cannot benefit from the advantages of miniaturization to improve their performance, which can limit competitiveness in such areas. Indeed, the level of reliability of integrated circuits on fine technologies (eg 28nm) is below the requirements imposed by the certification authorities and current standards.

The decrease in the reliability of integrated circuits is due to the combination of physical phenomena and chemical phenomena which are manifested in the transistors of integrated circuits. Such phenomena cause a variation in the electrical parameters which tends to reduce the switching speed of each transistor. This slowing down results in the delayed propagation of the information signals which can ultimately result in an alteration of the information bits. Such an alteration can cause a fault in the integrated circuit: the integrated circuit then no longer performs the desired function correctly (for example malfunction of the braking function of a vehicle).

The manifestation of these physical and chemical phenomena in the transistors depends on several variables: the geometry, the materials used, the design of the pattern, the supply voltage and the junction temperature of the transistor, the sequence, and the alternation frequency bits (between a bit of value 0 and a bit of value 1) which pass through the transistor. The overall reliability of the integrated circuit also depends on the way of interconnecting the transistors.

The reliability problem of transistors is generally addressed by the semiconductor manufacturer of the integrated circuit. However, the reliability problem is now a major constraint in the design phase of integrated circuits. In known approaches, the designer uses software tools capable of providing a preliminary indication of the level of reliability of the integrated circuit, before its manufacture. However, such tools require the use of a database which includes technological constants. These technological constants depend on the geometry, the materials used, the design of the pattern, the supply voltage and the temperature of the transistor. They are essential for obtaining an accurate estimate of the level of reliability.

The content of these databases is generally obtained empirically by the manufacturer with the help of internal testing facilities. Such a database is not available from all semiconductor manufacturers. Furthermore, this information is confidential in nature so that their access is severely limited (access subject to license conditions, access limited to third parties who subcontract the manufacture of their IC only, etc.).

In addition, the database is not complete because its construction requires a very long process of characterization of each type of transistors. Generally, the manufacturer builds this base for a few representative cases. However, designers of integrated circuits need to know the impact of a design choice - for example of an IP processor X rather than a Y processor - on the risks of the integrated circuit under development, whatever the technology used.

In addition to the influence of design choices, the risks on the integrated circuit are also influenced by the mission profile envisaged by the end user of the Cl. The mission profile represents the expected operating conditions of the integrated circuit during its use in the final system. A mission profile is notably characterized by the following parameters: the operating time of the integrated circuit under voltage, the supply voltage of the integrated circuit, the internal temperature of the integrated circuit and the manufacturing technology of the integrated circuit.
To date, there are no outsourced design solutions for manufacturing plants allowing the designer to analyze internally and precisely the impact of a technology on the overall reliability of its integrated application circuit.

The patent application US2012 / 0245879A1 describes a programmable test bench to characterize an integrated circuit manufacturing process, and in particular the electrical properties of a transistor. This test chip can be used before the fabrication of an integrated circuit by a design engineer. The test bench includes a wafer of semiconductor (“die”) test material which contains devices under test (DUT) of the transistor type and on-board test and measurement electronics. This reference integrated circuit is designed, manufactured and sold by the supplier of the test bench. The test bench can be configured by a user to launch the characterization and retrieve the measurement results. The results are stored in the form of a file in the machine. This solution allows to characterize the variations and the reliability of the circuit manufacturing process for different mission profiles. However, this solution requires expertise in reliability to configure the test bench, while design engineers do not generally have such expertise. Furthermore, this solution does not make it possible to directly estimate the impact of a choice of design of the integrated circuit on its reliability. Indeed, the test bench measurement outputs cannot be used to make such an estimate.
There is therefore a need for a system and a method for testing an integrated circuit, in the design phase.

We also know the solution described in the American patent application US 2009/027990 .

The invention provides a system and a method for testing an integrated circuit which allows the estimation of the variation over time, due to aging, of certain physical quantities of an internal circuit. For example greatness estimated physics can be an internal propagation time or a current consumed by the circuit.
The effect of aging is simulated according to a mission profile given by a design engineer and this without a priori knowledge of the physics of aging and technological parameters related to the manufacturing process.
The mission profile represents the operating conditions of the integrated circuit during its use. A mission profile is defined in particular by four parameters: the operating time of the live circuit, the supply voltage of the circuit, the internal temperature of the circuit and the manufacturing technology of the circuit.
The invention makes it possible to estimate the variation over time of quantities or physical parameters of an integrated circuit from its description without requiring any particular expertise to define the characterization protocol to be applied to the test system.

The invention is based on a test system on a hardware support comprising on the one hand test equipment and on the other hand an integrated characterization circuit dedicated to tests. The specification of the integrated characterization circuit is independent of that of the application integrated circuit to be produced.
The invention is also based on a test method which uses the test system and in particular the content of the integrated characterization circuit to estimate the variation of a physical quantity characteristic of the application integrated circuit from the first stages of the phase Design.

• un dispositif de contrôle du circuit intégré de caractérisation configuré pour faire varier au moins un paramètre physique d'au moins une structure de test configurable pour accélérer son vieillissement de sorte à obtenir au moins une structure de test dégradée,
• une interface pour recevoir au moins une description d'un circuit intégré d'application et extraire au moins un chemin de la description,
• un dispositif de configuration du circuit intégré de caractérisation pour activer et interconnecter au moins un sous-ensemble des cellules logiques d'au moins une structure de test dégradée et d'au moins une structure de test non dégradée, pour qu'elles réalisent chacune une topologie identique à au moins une partie d'un chemin extrait,
• un dispositif de contrôle de mesure pour effectuer au moins une première mesure d'une grandeur physique sur ladite au moins une structure de test dégradée et au moins une deuxième mesure, identique à la première mesure, sur ladite au moins une structure de test non dégradée.

Selon une variante particulière de l'invention, chaque structure de test comprend des cellules logiques combinatoires et des cellules logiques de mémorisation.
Selon une variante particulière de l'invention, le dispositif de contrôle du circuit intégré de caractérisation comprend un dispositif de contrôle de la température d'au moins une structure de test.
Selon une variante particulière de l'invention, le dispositif de contrôle du circuit intégré de caractérisation comprend un générateur de stimuli destinés à être injectés en un point d'entrée d'au moins une structure de test.
Selon une variante particulière de l'invention, le dispositif de contrôle du circuit intégré de caractérisation comprend un dispositif de contrôle de la tension d'alimentation d'au moins une structure de test.
Selon une variante particulière, le système selon l'invention comprend en outre un dispositif d'estimation configuré pour déterminer, à partir des mesures fournies par le dispositif de mesure, une estimation d'une variation dans le temps d'au moins une grandeur physique du circuit intégré d'application.
Selon une variante particulière de l'invention, la grandeur physique est un temps de propagation et le dispositif de contrôle de mesure est apte à mesurer un temps de propagation d'un signal entre deux cellules logiques de mémorisation.
Selon une variante particulière de l'invention, la grandeur physique est un courant consommé et le circuit intégré de caractérisation comporte en outre, pour chaque structure de test, un dispositif de mesure du courant consommé dans la structure de test apte à coopérer avec le dispositif de contrôle de mesure.The subject of the invention is therefore a system for testing an integrated application circuit represented by a description comprising a set of paths connecting several logic cells, the test system comprising an integrated characterization circuit comprising at least two test structures configurable, each comprising a plurality of activatable logic cells and a plurality of connectors for activating and interconnecting the logic cells, and a test set comprising:

• a control device for the integrated characterization circuit configured to vary at least one physical parameter at least at least one configurable test structure to accelerate its aging so as to obtain at least one degraded test structure,
• an interface for receiving at least one description of an integrated application circuit and extracting at least one path from the description,
• a device for configuring the integrated characterization circuit to activate and interconnect at least a subset of the logic cells of at least one degraded test structure and at least one non-degraded test structure, so that they each carry out a topology identical to at least part of an extracted path,
• a measurement control device for carrying out at least a first measurement of a physical quantity on said at least one degraded test structure and at least a second measurement, identical to the first measurement, on said at least one non-degraded test structure .

According to a particular variant of the invention, each test structure comprises combinational logic cells and logic storage cells.
According to a particular variant of the invention, the device for controlling the integrated characterization circuit comprises a device for controlling the temperature of at least one test structure.
According to a particular variant of the invention, the control device of the integrated characterization circuit comprises a stimuli generator intended to be injected at an entry point of at least one test structure.
According to a particular variant of the invention, the device for controlling the integrated characterization circuit comprises a device for controlling the supply voltage of at least one test structure.
According to a particular variant, the system according to the invention further comprises an estimation device configured to determine, from the measurements provided by the measuring device, an estimate of a variation over time of at least one physical quantity of the application integrated circuit.
According to a particular variant of the invention, the physical quantity is a propagation time and the measurement control device is able to measure a propagation time of a signal between two logic storage cells.
According to a particular variant of the invention, the physical quantity is a consumed current and the integrated characterization circuit further comprises, for each test structure, a device for measuring the current consumed in the test structure capable of cooperating with the device measurement control.

• faire varier au moins un paramètre physique d'au moins une structure de test configurable pour accélérer son vieillissement de sorte à obtenir au moins une structure de test dégradée,
• recevoir une description d'un circuit intégré d'application et extraire au moins un chemin de la description,
• activer et interconnecter au moins un sous-ensemble des cellules logiques d'au moins une structure de test dégradée et d'au moins une structure de test non dégradée, pour qu'elles réalisent chacune une topologie identique à au moins une partie d'un chemin extrait,
• effectuer au moins une première mesure d'une grandeur physique sur ladite au moins une structure de test dégradée et au moins une deuxième mesure, identique à la première mesure, sur ladite au moins une structure de test non dégradée.

Selon un aspect particulier du procédé selon l'invention, la partie du chemin extrait de la description du circuit intégré d'application comprend au moins trois cellules logiques connectées en série.
Selon un aspect particulier du procédé selon l'invention, ledit sous-ensemble de cellules logiques activées et interconnectées comprend en outre :

• Une cellule logique de mémorisation supplémentaire connectée en amont des trois cellules logiques extraites si la première cellule logique de la partie du chemin extrait n'est pas une cellule logique de mémorisation,
• Une cellule logique de mémorisation supplémentaire connectée en aval des trois cellules logiques extraites si la dernière cellule logique de la partie du chemin extrait n'est pas une cellule logique de mémorisation.

Selon un aspect particulier du procédé selon l'invention, la mesure d'au moins une grandeur physique est réalisée au moins sur une cellule logique de mémorisation dudit sous-ensemble.
Selon un aspect particulier du procédé selon l'invention, le procédé est itéré en faisant varier la partie du chemin extrait selon une fenêtre glissante pour parcourir tout le chemin.
Selon un aspect particulier du procédé selon l'invention, ledit paramètre physique est pris parmi une température du circuit, une tension d'alimentation, un stimulus injecté en entrée du circuit de nature et de durée variables.
Selon une variante particulière, le procédé selon l'invention comprend en outre une estimation d'une variation dans le temps d'au moins une grandeur physique du circuit intégré d'application à partir des mesures réalisées sur ladite au moins une structure de test dégradée et sur ladite au moins une structure de test non dégradée.
Selon une variante particulière, l'estimation comprend le calcul de la différence entre deux mesures identiques réalisées sur ladite au moins une structure de test dégradée et sur ladite au moins une structure de test non dégradée.
Selon une variante particulière, l'estimation comprend le calcul d'un ratio entre une somme des différences entre deux mesures identiques réalisées sur ladite au moins une structure de test dégradée et sur ladite au moins une structure de test non dégradée et une somme des mesures réalisées sur ladite au moins une structure de test non dégradée.
Selon un aspect particulier du procédé selon l'invention, la grandeur physique est un temps de propagation ou un courant consommé.The invention also relates to a method for testing an integrated application circuit represented by a description comprising a set of paths connecting several logic cells, the method being implemented by means of a test system comprising a circuit integrated characterization comprising at least two configurable test structures, each comprising a plurality of activatable logic cells and a plurality of connectors for activating and interconnecting the logic cells and a test assembly, the method comprising the steps of:

• varying at least one physical parameter of at least one configurable test structure to accelerate its aging so as to obtain at least one degraded test structure,
• receive a description of an integrated application circuit and extract at least one path from the description,
• activate and interconnect at least a subset of the logical cells of at least one degraded test structure and at least one non-degraded test structure, so that they each achieve a topology identical to at least part of a extracted path,
• perform at least a first measurement of a physical quantity on said at least one degraded test structure and at least a second measurement, identical to the first measurement, on said at least one non-degraded test structure.

According to a particular aspect of the method according to the invention, the part of the path extracted from the description of the application integrated circuit comprises at least three logic cells connected in series.
According to a particular aspect of the method according to the invention, said subset of activated and interconnected logic cells further comprises:

• An additional logical storage cell connected upstream of the three extracted logical cells if the first logical cell in the part of the extracted path is not a logical storage cell,
• An additional logical storage cell connected downstream of the three extracted logical cells if the last logical cell in the part of the extracted path is not a logical storage cell.

According to a particular aspect of the method according to the invention, the measurement of at least one physical quantity is carried out at least on a logic cell for storing said subset.
According to a particular aspect of the method according to the invention, the method is iterated by varying the part of the extracted path according to a sliding window to cover the entire path.
According to a particular aspect of the method according to the invention, said physical parameter is taken from a circuit temperature, a supply voltage, a stimulus injected at the input of the circuit of variable nature and duration.
According to a particular variant, the method according to the invention further comprises an estimate of a variation over time of at least one physical quantity of the application integrated circuit from measurements carried out on said at least one degraded test structure and on said at least one non-degraded test structure.
According to a particular variant, the estimation comprises the calculation of the difference between two identical measurements carried out on said at least one degraded test structure and on said at least one non-degraded test structure.
According to a particular variant, the estimation comprises the calculation of a ratio between a sum of the differences between two identical measurements carried out on said at least one degraded test structure and on said at least one non-degraded test structure and a sum of measurements performed on said at least one non-degraded test structure.
According to a particular aspect of the method according to the invention, the physical quantity is a propagation time or a consumed current.

• La figure 1, un schéma synoptique d'un système de test d'un circuit intégré selon l'invention,
• La figure 2, un schéma d'une structure de test selon l'invention,
• La figure 3, un schéma illustrant plusieurs agencements possibles de cellules dans une structure de test selon un premier mode de fonctionnement,
• La figure 4, un schéma illustrant plusieurs agencements possibles de cellules dans une structure de test selon un second mode de fonctionnement,
• La figure 5, un schéma illustrant un agencement possible de deux structures de test au sein d'un circuit de caractérisation,
• La figure 6, un organigramme détaillant les étapes de mise en œuvre d'un procédé de test d'un circuit intégré selon l'invention,
• La figure 7, une courbe d'approximation utilisée pour estimer un temps de propagation, dans un mode particulier de réalisation de l'invention,
• La figure 8, un schéma illustrant une structure de test dans une variante de réalisation de l'invention appliquée à l'estimation de la variation du courant consommé dans le circuit,
• La figure 9, un schéma d'un système de test d'un circuit intégré selon une variante de l'invention appliquée à l'estimation de la variation du courant consommé dans le circuit.

Other characteristics and advantages of the present invention will appear better on reading the description which follows in relation to the appended drawings which represent:

• The figure 1 , a block diagram of a test system of an integrated circuit according to the invention,
• The figure 2 , a diagram of a test structure according to the invention,
• The figure 3 , a diagram illustrating several possible arrangements of cells in a test structure according to a first mode of operation,
• The figure 4 , a diagram illustrating several possible arrangements of cells in a test structure according to a second mode of operation,
• The figure 5 , a diagram illustrating a possible arrangement of two test structures within a characterization circuit,
• The figure 6 , a flowchart detailing the steps for implementing a method for testing an integrated circuit according to the invention,
• The figure 7 , an approximation curve used to estimate a propagation time, in a particular embodiment of the invention,
• The figure 8 , a diagram illustrating a test structure in an alternative embodiment of the invention applied to the estimation of the variation of the current consumed in the circuit,
• The figure 9 , a diagram of a test system of an integrated circuit according to a variant of the invention applied to the estimation of the variation of the current consumed in the circuit.

The figure 1 represents a block diagram of a SYS test system according to the invention which mainly comprises a characterization circuit CAR and an EDT test set. The test system is also connected to an EST estimation device via a communication link which can be a wired link, a wireless link or a communication network, for example the internet network. In one embodiment of the invention, the EST estimation device can be integrated into the SYS test system. In another embodiment of the invention, the EST estimation device can be remote from the SYS test system.

The characterization circuit CAR includes a plurality of test structures ST1, ST2. In particular, the number of test structures implemented in a characterization circuit must be sufficient to take into account the effects of the variability of the manufacturing process.
The CAR characterization circuit can be manufactured in any manufacturing technology associated with a semiconductor manufacturer. An example of manufacturing technology is the so-called “bulk 40nm low-power” technology.
Manufacturing technology defines a library of standard logic cells. Each cell defines a function, for example a logic gate of the AND, OR or NAND type, or an inverter or a flip-flop or any other logical function. These logic cells can be combined with one another by design assistance tools.
Logic cells are mainly of two types. Combinatorial logic cells perform logic functions, for example Boolean logic functions, while logic storage cells perform storage functions of the flip-flops and latches type.
Each test structure ST1, ST2 comprises several logic cells defined according to the manufacturing technology chosen and several means of activation and interconnection of these cells with one another. An example of such a means is a switch. A characterization circuit includes at least two identical test structures. Each test structure is configurable to activate and interconnect certain logic cells. The configuration of a test structure is done by controlling the activation and interconnection means.

The test system according to the invention also comprises a test assembly which comprises at least one configuration device CONF of the integrated characterization circuit CAR, a control device CTR of the integrated characterization circuit CAR, a measurement device MES for measuring a physical quantity internal to the integrated characterization circuit CAR and an INT interface (or controller) for the exchange of information between the EST estimation device and the EDT test set.
The configuration device CONF is used to configure each test structure from elements of description of the application integrated circuit to be designed.
The CTR control device is used to vary at least one physical parameter of at least one test structure to cause accelerated aging of the components of this test structure.
The CTR control device can comprise a CTEMP temperature control device, for example a driver associated with a temperature sensor. temperature. It may also include a GSTIM stimuli generator for generating and injecting a signal of a given shape at the input of a test structure for a given duration. It may also include a device for controlling the CTENS supply voltage of the test structure.
Different variants of the SYS test system are possible. In a first variant, the EDT test set can be integrated directly into the integrated characterization circuit CAR.
In a second variant, the EDT test set can be installed on an electronic card which also contains the integrated characterization circuit CAR.
In these first two variants, the integrated characterization circuit can be encapsulated.
In a third variant, the EDT test set is separated from the integrated characterization circuit CAR.
The first two variants have the advantage of proposing a compact integrated device which does not require separate test equipment. The second variant also has the advantage of being less complex to implement than the first variant.
The third variant has the advantage of allowing precise measurements on the integrated characterization circuit without resorting to design and integration efforts of the test set in a chip or an electronic card.

The EST estimation device can be implemented by software means, for example in the form of client software intended for the design engineer. The client software can connect remotely to the SYS test system via a remote server to which the system is linked.

The figure 2 shows a diagram of an ST test structure according to the invention.

A test structure includes several logic cells and several activation and interconnection means. A possible example of activation and interconnection means is a switch. The remainder of the description is given by considering this example, it being understood that the invention is not limited to this particular embodiment. An electronic switch can be produced, for example, using the technology known as “spoiling pass”. However, the invention is not limited to the use of switches to perform the activation and interconnection function of the cells, this function being able to be performed by other components.
A logic cell has an output and at least one input on which an information signal carrying a binary message can be injected. A logic cell also has two power contacts.

A test structure comprises at least two groups of storage cells CM1, CM2 and a group of combinatorial cells CC as shown in the figure 2 . Each group of cells contains at least one cell and at least one switch.
The test structure ST also includes several programming inputs EP for configuring the arrangement of the logic cells, at least two power inputs EA1, EA2, a clock input EH, a signal input ES and an output of signal S.
The programming inputs are used to activate certain switches in order to configure a particular arrangement of cells connected in series.
According to a particular embodiment, the activation and interconnection means can comprise two switches for each cell. A first switch is used to control the activation of a cell. For this purpose, it can be connected between the supply terminal of a cell and a supply terminal EA1 of the test structure. A second switch is used to control the connection from one cell to another.
Each EP programming input can control a switch. Advantageously, an address decoder makes it possible to reduce the number of programming inputs and thus reduce the number of terminals to be provided on the integrated characterization circuit.

• activer une cellule de mémorisation parmi les cellules disponibles dans un premier groupe de cellules de mémorisation CM1,
• activer au moins une cellule logique combinatoire parmi celles présentes dans le groupe de cellules combinatoires CC,
• activer une cellule de mémorisation parmi les cellules disponibles dans le second groupe de cellules de mémorisation CM2,
• connecter les cellules activées aux bornes d'entrée de signal ES et de sortie S.

The signal input ES and signal output S are respectively used for the injection and measurement of a test signal or stimulus in the cells previously connected to each other by means of the switches and from the configuration transmitted via the programming inputs EP.
The configuration of a test structure consists in particular in:

• activate a storage cell among the cells available in a first group of storage cells CM1,
• activate at least one combinatorial logic cell among those present in the group of CC combinatorial cells,
• activate a storage cell among the cells available in the second group of storage cells CM2,
• connect the activated cells to the ES signal input and S output terminals.

The figure 3 represents, on the same diagram, three examples of arrangements in series of several logical cells.
In the three examples shown in the figure 3 , each group of storage cells CM1, CM2 each comprises a storage cell R1, R2.
The group of CC combinatorial cells comprises from one to three combinatorial cells A, B, C connected in series.
These particular arrangements are used in an embodiment of the test method according to the invention which will be described in detail later in the text.

The figure 4 represents another example of arrangement, in parallel, of several logic cells.
In this example, the first group of storage cells CM1 comprises two storage cells R1, R2 connected in parallel to the signal input ES.
The second group of storage cells CM2 comprises two storage cells R3, R4 connected in parallel to the signal input ES.
The group of combinatorial cells CC comprises three combinatorial cells A, B, C connected in parallel to the signal input ES.
According to this arrangement, all the cells are connected in parallel to the signal input ES. The other possible entries of the cells are forced to a fixed value '0' or '1'. The cell outputs are not connected. The cell supply contacts are connected to the same supply terminal.
The particular arrangement of the figure 4 is used in a particular step of the test method according to the invention.

The figure 5 represents a set of two test structures arranged within an integrated characterization circuit.
According to a first alternative embodiment described in figure 5 , the two test structures ST1, ST2 share the same input and output terminals of the integrated characterization circuit. The number of test structures thus connected in parallel can be greater than two.
The outputs of the test structures are connected to a multiplexer MUX associated with a selection terminal which controls the connection of the output of one of the test structures to the output of the integrated characterization circuit.
Thus, the test structures ST1, ST2 can simultaneously receive the same configuration on the programming inputs and the same signals on the signal input.

According to a second embodiment not shown in the figure 5 , the inputs and outputs of the test structures are physically separated from each other, in other words, they are connected to separate terminals of the integrated characterization circuit.
The two aforementioned variants can also be combined on the same integrated characterization circuit.

According to a particular embodiment of the invention, the test structures can include heating devices to increase the junction temperature of the transistors of the logic cells as well as temperature sensors. The heaters and sensors are then connected to the CTEMP temperature control device of the EDT test set.

An integrated characterization circuit may include one or more pairs of test structures. The number of test structures depends on the cost of production and the production yield.
Several integrated characterization circuits can be produced using different manufacturing technologies. The specification of the integrated characterization circuit developed for a first technology can be reused to address another technology.
The invention can be based on the use of a single test chip comprising a test system. Advantageously, the invention can also use several identical chips from different positions of the same wafer and / or from different wafers. After manufacture, the integrated characterization circuits are tested for manufacturing defects. Only flaws free from defects are retained.

We now describe, in support of the figure 6 , an exemplary embodiment of a method for testing an application integrated circuit, according to the invention, which uses the SYS test system described above.

A first step 601 of the method consists in implementing a so-called “stress” protocol to accelerate the activation of phenomena linked to the aging of the transistors which make up the logic cells of a test structure. This first step 601 is applied to at least one test structure of the integrated characterization circuit but can, advantageously, be applied to several test structures.
The purpose of a stress protocol is to vary at least one physical parameter of a test structure in order to accelerate its aging and to obtain a degraded test structure which is capable of reproducing the faults which may appear on a circuit at over time.

The physical parameter to be varied can, for example, be chosen from the following four parameters: the internal temperature of the circuit, the supply voltage of the circuit, the form of a stimulus (signal) injected into the circuit, the duration for which the circuit is subjected to the variation of one of the preceding parameters.
A stress protocol may include the variation of one or more physical parameters of the test structure. It can be defined from a mission profile which is chosen by the system user who can be a design engineer. The mission profile is chosen in particular according to test standards which are defined from knowledge of the aging physics of a circuit.
In particular, the stimuli injected into the test structure can take three different forms. A first stimulus corresponds to a signal of constant value '0' injected on the input of all the cells for a given duration. Another stimulus corresponds to a signal with a constant value '1'. Another stimulus corresponds to a signal alternating the values '0' and '1'.
Advantageously, the stress protocol 601 is applied to a test structure configured according to the arrangement described in the figure 4 . So a stimulus can be injected, via the input terminal of the test structure, directly into each combinatorial cell.
Once step 601 is applied to a test structure, it is artificially degraded or worn out.
Step 601 is implemented using the EDT test set described in the figure 1 and in particular using the CTR control device.

The following steps 602,603,604,605 describe a method making it possible to estimate a variation, over time, of certain physical quantities characteristic of an integrated application circuit that the user wishes to design.
In a first embodiment, the physical quantity targeted is a propagation time of a signal in the circuit.

A point of entry for the method is a description of the targeted application integrated circuit and more precisely a list of all the paths implemented by the integrated circuit. A path is a set of logic cells crossed by a signal which propagates from an entry point of the circuit towards an exit point of the circuit. A signal can be an uplink signal (i.e. a signal performing a transition from state '0' to a state '1') or a downlink signal (i.e. a signal performing a transition from state '1' to state '0'). A circuit entry point can be a storage cell or an input terminal. Likewise, an output point of the circuit can be a storage cell or an output terminal. There is at least one path in an integrated circuit. A path is described by the reference of the logical cells which compose it. Each cell has a unique reference which indicates the origin of the manufacturer, the function performed, the number of internal transistors, the number of inputs ...
The list of paths is generally obtained with the help of a logical synthesis which transforms a description of type VHDL or VERILOG abstract of the integrated circuit towards a description of type "gate". The transformation relies on the circuit manufacturer's library. Thus, the path description contains only standard cells from this library.

1. A- Une phase de modélisation du circuit (sur le plan matériel et logiciel) dans laquelle le circuit est modélisé à très haut niveau;
2. B- Une phase de description en langage haut niveau, après validation de l'architecture en phase de modélisation, dans laquelle l'implémentation du circuit est décrite au niveau transfert de registres (RTL) sous forme d'éléments séquentiels (registres, bascules) et d'éléments combinatoires logiques correspondant aux combinaisons entre les entrées/sorties des éléments séquentiels et les entrées/sorties principales du circuit ; cette description, appelée « description comportementale », est codée à l'aide d'un langage de programmation haut niveau (par exemple VHDL, VERILOG, etc.) ;
3. C- Une phase de simulation logique pour simuler la description en utilisant un simulateur. Le simulateur simule dans le temps chaque signal d'interconnexion en fonction d'un stimulus d'entrée décrit au préalable;
4. D- Une phase de vérification fonctionnelle peut être mise en œuvre en complément de la simulation notamment pour simuler des durées de fonctionnement plus importantes, en utilisant des langages basés sur une modélisation par assertion pour définir les propriétés fonctionnelles que doit vérifier le circuit ;
5. E- Une phase de synthèse logique dans laquelle la description comportementale du circuit est transformée en une description structurelle au niveau des portes logiques (« netlist »), à partir d'une bibliothèque de portes logiques (par exemple portes ET, OU, Bascules, etc.) spécifique à la technologie visée et/ou au fondeur qui fabriquera le circuit. La synthèse logique peut être mise en œuvre au moyen d'un outil EDA configuré pour transformer la description comportementale en langage haut niveau en description structurelle générique (indépendamment de la bibliothèque de portes logiques) en décrivant les éléments logiques combinatoires et séquentiels sous forme générique, puis en les remplaçant par des éléments de la bibliothèque de portes logiques de manière à respecter des conditions portant sur les caractéristiques du circuit (e.g. chemins logiques du circuits) par rapport à des contraintes de temps (par exemple, fréquence de fonctionnement du circuit) et d'espace (taille en silicium). À l'issue de la synthèse logique, un fichier informatique correspondant à la description structurelle peut être obtenu dans un format choisi tel que Verilog, VHDL, EDIF. Ce fichier correspondant au circuit intégré représente l'instanciation des portes de la bibliothèque et leur interconnexion (« netlist ») ;
6. F- Le circuit peut être ensuite fabriqué en usine.

Conventionally, the process for manufacturing an integrated application circuit comprises:

1. A- A circuit modeling phase (in terms of hardware and software) in which the circuit is modeled at a very high level;
2. B- A description phase in high-level language, after validation of the architecture in the modeling phase, in which the implementation of the circuit is described at the transfer of registers level (RTL) in the form of sequential elements (registers, flip-flops) and of logic combinational elements corresponding to the combinations between the inputs / outputs of the sequential elements and the main inputs / outputs of the circuit; this description, called "behavioral description", is coded using a high-level programming language (for example VHDL, VERILOG, etc.);
3. C- A logical simulation phase to simulate the description using a simulator. The simulator simulates each interconnection signal over time according to an input stimulus described previously;
4. D- A functional verification phase can be implemented in addition to the simulation, in particular to simulate longer operating times, using languages based on assertion modeling to define the functional properties that the circuit must verify;
5. E- A phase of logical synthesis in which the behavioral description of the circuit is transformed into a structural description at the level of the logic gates (“netlist”), from a library of logic gates (for example AND, OR gates, Bascules, etc.) specific to the target technology and / or to the founder who will manufacture the circuit. Logical synthesis can be implemented using an EDA tool configured to transform behavioral description in high-level language into generic structural description (independently of the library of logic gates) by describing the combinatorial and sequential logic elements in generic form, then by replacing them with elements from the logic gate library so as to comply with conditions relating to the characteristics of the circuit (eg logic paths of the circuit) with respect to time constraints (for example, operating frequency of the circuit) and of space (silicon size). At the end of the logical synthesis, a computer file corresponding to the structural description can be obtained in a chosen format such as Verilog, VHDL, EDIF. This file corresponding to the integrated circuit represents the instantiation of the library doors and their interconnection (“netlist”);
6. F- The circuit can then be manufactured in the factory.

The description of the application circuit can be derived from any of the descriptions of the circuit obtained in the different phases of the design flow. In certain embodiments, the description of the application circuit can be a structural description of step E of the integrated application circuit from among the possible descriptions: logical “netlist” or physical “netlist”.

The following steps 602, 603 and 604 can be iterated for several paths extracted from the description of the application integrated circuit. Advantageously, all the paths are treated in order from longest to shortest. The length is determined for example by the number of cells making up this path. Alternatively, the length can also be determined by the estimated propagation time with the help software tools and value libraries provided by the semiconductor manufacturer.

In one embodiment of the invention, all the cells making up a path can be transmitted and processed directly by the configuration step 603. This embodiment relates in particular to application cases where the integrated characterization circuit n is not constrained in size and the application circuit contains few paths.
In another embodiment, in order to limit the dimensions of the integrated characterization circuit, it is possible to process a path by an iterative loop using a sliding window comprising a limited number of logic cells.
Step 602 thus consists in extracting, via a selection window, a set of logical cells from the path, starting with the entry point of the path. In subsequent iterations, the selection window is moved to the exit of the path one cell at a time. The selection window contains at least three logical cells. When the three logical cells extracted from the path do not include a storage cell at the start of the sequence, a storage cell is added at the start of the window which then includes at least four cells. Similarly, when the three logical cells extracted from the path do not include a storage cell at the end of the sequence, a storage cell is added at the end of the window which then comprises at least four cells.
For example, we can consider a path composed of five cells ordered as follows: A, B, C, D and E. In the first iteration of step 602, the method selects cells A, B and C. In the second iteration of step 602, the method selects cells B, C and D. In the third iteration of step 602, the method selects cells C, D and E. In this example, cells A and E are memory cells.

Step 603 then consists in configuring at least one degraded test structure by application of step 601 and at least one sound test structure, that is to say undegraded, so that each of these test structures reproduces the arrangement of extracted cells in the selection window.
Step 603 is executed by the configuration device CONF of the EDT test unit which receives the paths of the description of the application integrated circuit via the interface INT.
An exemplary embodiment of step 603 consists in recovering the reference of each extracted cell. The method has, for example, an associative table T1 called the configuration table which was previously filled during the design of the characterization circuit CAR. The index of table T1 is the reference of a cell in the characterization circuit. For each cell, the table T1 contains an address which indicates the number of the EP programming inputs to be checked. For each reference, the process searches for the entry in the corresponding table and then checks the programming entries found in the entry for the table to activate the corresponding switches. The table T1 is preferably stored in a non-volatile memory of the integrated characterization circuit. For example, the configuration device CONF receives the description of the paths via the INT interface and then comes to read the table T1 to apply the configuration corresponding to the selection window to the chosen test structures.

In a step 604, the method performs measurements on the test structures configured via step 603 which comprise at least one degraded test structure and at least one healthy test structure.
In the case where several degraded test structures are used, each degraded test structure may have been subjected to a stress protocol having different parameters, for example different forms of stimuli.

1. 1. Programmation de la plus grande fréquence disponible dans le générateur d'horloge,
2. 2. Application d'un signal d'horloge périodique sur les entrées dédiées des cellules de mémorisation,
3. 3. Initialisation des cellules de mémorisation actives à la valeur '0',
4. 4. Au premier front d'horloge, une valeur '0' est appliquée à l'entrée de signal ES de la structure de test, la valeur '0' est observée sur la sortie S,
5. 5. Au second front d'horloge, une valeur '1' est appliquée sur l'entrée de signal ES de la structure de test, la valeur '0' est observée sur la sortie S,
6. 6. Au troisième front d'horloge, la valeur '1' est maintenue sur l'entrée de signal ES, la sortie S peut prendre deux valeurs possibles :
   1. a. Si la valeur observée est '1', cela signifie que le temps de propagation est inférieur à la période d'horloge programmée (inverse de la fréquence). Dans ce cas, on choisi une valeur de fréquence d'horloge supérieure à l'aide d'une méthode par dichotomie et on itère le procédé en retournant à l'étape 3.
   2. b. Si la valeur observée est '0', cela signifie que le temps de propagation est supérieur à la période d'horloge programmée. Dans ce cas, on choisi une valeur de fréquence d'horloge inférieure avec l'aide d'une méthode par dichotomie et on itère le procédé en retournant à l'étape 3.

Le procédé s'arrête lorsque la différence entre la valeur de fréquence obtenue (Fob) et la valeur de fréquence actuelle (Fac) est inférieure au pas de programmation (incrément ou décrément minimal) du générateur d'horloge. La valeur de temps de propagation montant (tm) peut être obtenue à l'aide de la formule suivante : $$\mathrm{tm}=\frac{2}{\frac{1}{{\mathrm{F}}_{\mathrm{ac}}}+\frac{1}{{\mathrm{F}}_{\mathrm{ob}}}}$$

In a first embodiment of the invention, the measurements carried out relate to propagation time measurements. A propagation time for a signal injected at the input of the group of cells selected in step 602 and measured at the output of this group of cells is measured on each test structure. Advantageously, the propagation time measurement is carried out at the level of the output storage cell. A so-called “amount” propagation time is measured corresponding to the propagation of an amount signal (passing from state '0' to state '1'). We also measure a propagation time called "down" corresponding to the propagation of a down signal (going from state '1' to state '0').
The propagation time in a test structure designates the time it takes for a signal to pass from the input storage cell of the test structure to the output storage cell of the test structure. A possible realization of these measurements is based on the technique of finding the maximum frequency of the test structure or technique called "at-speed".
In the case of the integrated characterization circuit, the objective is to determine the propagation time of a signal propagating through the activated cells. The measurement of this time is based on the use of a clock generator which produces a periodic signal whose frequency is programmable and the stimuli generator. Whatever the configuration envisaged for the test structure, the method requires the activation of a storage cell in each of the two groups of storage cells CM1, CM2.
The rest of the paragraph describes an example of a method for measuring the uplink. The steps described may be applied identically to the measurement of the downward propagation time.
The measurement is based on the propagation of an upward transition through the cell located in the center of the sliding window. In the case of a sliding window comprising three cells extracted from a path, the cell located at center of the sliding window is the second cell in the group of three cells.
The measurement can be carried out via the following steps:

1. 1. Programming the highest frequency available in the clock generator,
2. 2. Application of a periodic clock signal on the dedicated inputs of the storage cells,
3. 3. Initialization of the active storage cells to the value '0',
4. 4. At the first clock edge, a value '0' is applied to the signal input ES of the test structure, the value '0' is observed on the output S,
5. 5. On the second clock edge, a value '1' is applied to the signal input ES of the test structure, the value '0' is observed on the output S,
6. 6. At the third clock edge, the value '1' is maintained on the signal input ES, the output S can take two possible values:
   1. at. If the observed value is '1', this means that the propagation time is less than the programmed clock period (inverse of the frequency). In this case, a higher clock frequency value is chosen using a dichotomy method and the process is iterated by returning to step 3.
   2. b. If the observed value is '0', this means that the propagation time is greater than the programmed clock period. In this case, a lower clock frequency value is chosen with the help of a dichotomy method and the process is iterated by returning to step 3.

The process stops when the difference between the frequency value obtained (Fob) and the current frequency value (Fac) is less than the programming step (minimum increment or decrement) of the clock generator. The amount of uplink time (tm) can be obtained using the following formula: $$\mathrm{tm}=\frac{2}{\frac{1}{{\mathrm{F}}_{\mathrm{ac}}}+\frac{1}{{\mathrm{F}}_{\mathrm{ob}}}}$$

The method described above corresponds to the case of a combinational logic cell without inversion. In the case where the output of a cell takes the inverse of the input value, the values applied to the ES signal input must be complemented ('0' becomes '1' and vice versa).
The invention is not limited, for measuring a propagation time, to the method described above. Any other method for measuring an up and down propagation time between the input and the output of a test structure is compatible with the invention. In particular, any method using delay sensors making it possible to detect the variation in the propagation time of signals between two storage cells can be envisaged.

The steps 602,603,604 are iterated by dragging the selection window gradually from one cell to each iteration until the end of a path.

At the end of step 604, a set of measurements is obtained which can be stored in one or more tables. For example, you can use one table for degraded test structures and another table for healthy test structures. Each table can be indexed by the reference of a cell of the group of cells selected in step 602. Each entry of the table stores all of the measurements carried out which include at least one value of uplink and propagation time. downward spread. The table (s) can be stored in a memory of the EST estimation device. In this case, the measurements carried out in step 604 via the measurement device MES are transmitted to the estimation device EST via an interface INT.
For each path, one obtains a measurement per cell in the case where a sliding selection window is used.

In the case where several degraded test structures are used, with different forms of stimuli, for each entry, the table comprises as many pairs of measurements (uplink propagation time, descending propagation time) as there are degraded test structures used.

In a step 605, the estimation device EST, which can be implemented by software interfaced with the test system SYS, receives the measurements made on the different test structures and applies a set of processing on these measurements in order to '' deduce an a priori estimate of the evolution over time of the physical quantity measured. In the presently described embodiment, the physical quantity is a propagation time, the EST estimation device compares the propagation time measurements carried out on the one hand on the degraded test structures and on the other hand on the healthy test.

The measurements made on a degraded test structure can be corrected, using weighting coefficients, to take into account the artificial acceleration of the aging of the test structure and reduce the measurements to values representative of the effect of aging. over a long period.

The comparison can be made by calculating the relative variation of the propagation time measured on a degraded test structure compared to the propagation time measured on a healthy test structure.

When a selection window is used to traverse a path of the application integrated circuit, the measurements made for several positions of the selection window are aggregated together in order to provide a single final measurement.

• t_d(i) sont les mesures de temps de propagation (montant ou descendant) réalisées sur une structure de test dégradée,
• t_s(i) sont les mesures de temps de propagation (montant ou descendant) réalisées sur une structure de test saine.

As an example, an estimate of overall variation in propagation time can be calculated using the following formula: $$\mathrm{\Delta }t=\frac{{\displaystyle \sum t_d\left(i\right)-{\displaystyle \sum t_s\left(i\right)}}}{{\displaystyle \sum t_s\left(i\right)}}$$

• t _d (i) are the propagation time measurements (up or down) carried out on a degraded test structure,
• t _s (i) are the propagation time measurements (up or down) carried out on a healthy test structure.

• le nombre de commutation par cycle d'horloge, noté TR
• les probabilités à '0' et '1' par cycle d'horloge d'un signal, notées respectivement SP0 et SP1.

In the case where several degraded test structures are used by the injection of several different stimuli, it is possible to take into account in a differentiated manner the measurements carried out on these degraded test structures in the calculation of the final estimate.
For example, it is possible to retain only the highest variation among the variations calculated for several test structures. We can also use the average of the variations calculated for several test structures or the average subtracted from the standard deviation or any other statistical metric.
In another alternative embodiment, the choice of the propagation time value retained can be guided by the knowledge of the real activity of the input of a cell G forming part of the path processed by the method and corresponding to a path in the application integrated circuit.

The real activity of each cell can be obtained by a logico-temporal simulation of the integrated application circuit previously carried out with input stimuli defined by the user (eg applications executed on a microprocessor). The simulation reports are analyzed in order to calculate the activity of the input of each cell of the application integrated circuit. Two metrics can be used:

• the number of switching operations per clock cycle, denoted TR
• the probabilities at '0' and '1' per clock cycle of a signal, noted respectively SP0 and SP1.

Each entry in cell G is associated with a value triplet (TR, SP0 and SP1).
When a cell has at least two entries, the choice of triplet for cell G is that of the entry crossed by path P.
In this alternative embodiment, the value which will be retained for cell G is obtained by an interpolation operation from all the values contained, for this cell G, in the table of measurements made on several degraded test structures.
An exemplary embodiment of the interpolation step is illustrated on the figure 7 which represents, on a diagram, on the abscissa 701, information on the activity of the input of a cell G and, on the ordinate 702, the propagation time measurements, for this cell G, obtained for several test structures degraded. The input activity of the cell is measured by an SP0 metric. The activity values SP0_1, SP0_2, SP0_3 are reference values associated with three measurements tg (3.1), tg (3.2), tg (3.3) made on three different degraded test structures. From the three points of the curve, we use statistical theory to determine the approximation curve C which passes closest to these three points.
Then, from the SP0_real activity value actually measured on the input of cell G, we obtain an interpolated measurement tg_approx (3).

We now describe another embodiment of the invention in which the physical quantity measured can be a current consumed in a logic cell and no longer a propagation time.
This embodiment presents a solution for estimating the variation of the current consumed by the circuit over time. The variation is caused by the aging of the cells of the circuit. This solution is interested in the static current (when the input of the cell is in a state '0' or '1') and in the dynamic current (when an input switches from the value '0' towards '1' and vice -versa) consumed by the cells of the application circuit.

To implement this embodiment, the integrated characterization circuit CAR must be modified to insert a current measurement device in each test structure. An example of a modified test structure according to this variant of the invention is shown in figure 8 .

The DMC current measurement device can distinguish the current consumed in each test structure separately. For this, the DMC device is inserted into the power rail of each test structure. The power rail of each test structure is physically separate from that of the other structures. The measurement of the current of a test structure is the sum of the currents consumed by each active cell in the three groups of cells CM1, CC, CM2.

In addition, the SYS test system according to the invention must also be modified in order to insert, into the EDT test set, a DCMC control device for measuring the current consumed in the test structures. This DCMC device has the function of reading and memorizing the current values measured in each test structure separately. The SYS test system modified according to this variant of the invention is shown in figure 9 .

The measurement step 604 of the method according to this variant embodiment of the invention notably consists on the one hand in measuring a static current and on the other hand in measuring a dynamic current.
Static current is measured by applying a constant signal in state '0' to the ES signal input of the test structure. The maximum current consumed by the test structure is measured by the DMC measuring device.
The dynamic current is measured by applying, to the signal input ES of the test structure, a signal making a transition from state '0' to state '1'. The maximum current consumed during the switching phase of the output from a cell is measured. When a sliding selection window is used, the current is measured in the cell in the center of the window, for example the second cell when the window contains three cells.

The measurements are stored and communicated to the EST estimation device in the same way as for the propagation time measurements.
The calculation of the estimate of the variation of the measured current is identical to that of the calculation of the estimate of the variation of the propagation time previously described. In other words, the estimation step 605 is identical between the two variants of the invention.

The invention has the advantage of allowing a user to estimate the reliability of an integrated application circuit by relying on a SYS test system according to the invention. The configuration and handling of the system can be hidden from the user thanks to the EDT test set.

The test system and method according to the embodiments of the invention have several advantages. In particular, they allow risk analysis and decision-making as early as possible in the development flow, the implementation of the invention being able to use a description of the circuit resulting from the result of the first logical synthesis.

Furthermore, they allow a precise estimate of the overall level of reliability of the integrated circuit to be produced according to its implementation and the mission profile.
It is also an advantage of the invention to allow an estimate of reliability independent of the conditions of access to the confidential data of the semiconductor manufacturer. The invention further guarantees the non-disclosure of confidential information which will be extracted from the test system.
In addition, the estimate does not require special expertise on the part of the designer in the area of reliability.

The test system and method according to the embodiments of the invention can rely on standardized characterization techniques, and apply to any semiconductor technology whatever the sources of failures in the transistors.

Those skilled in the art will understand that the test method according to the embodiments can be implemented in various ways by hardware, software, or a combination of hardware and software, in particular in the form of code of program which can be distributed as a program product in various forms. In particular, the program code may be distributed using computer readable media, which may include computer readable storage media and communication media. The methods described in the present description can in particular be implemented in the form of computer program instructions executable by one or more processors in a computer computing device. These computer program instructions may also be stored in computer readable medium.

The invention is not limited to the embodiments described above by way of nonlimiting example. It encompasses all the variant embodiments which may be envisaged by those skilled in the art. In particular, the invention is not limited to particular types of logic or combinatorial cells for producing integrated characterization circuits.

Claims (18)

1. System (SYS) for testing an application-specific integrated circuit represented by a description comprising a assembly of paths linking several logic cells, the test system (SYS) comprising a characterization integrated circuit (CAR) comprising at least two configurable test structures (ST1, ST2), each comprising a plurality of activatable logic cells (A, B, C, R1, R2) and a plurality of connectors for activating and interconnecting the logic cells, and a test assembly (EDT) comprising:

   - a device (CTR) for controlling the integrated characterization circuit, configured to vary at least one physical parameter of at least one test structure configurable to accelerate its aging so as to obtain at least one degraded test structure,

   - an interface (INT) for receiving at least one description of an application-specific integrated circuit and extracting at least one path from the description,

   - a device (CONF) for configuring the integrated characterization circuit to activate and interconnect at least one subset of logical cells of at least one degraded test structure and at least one non-degraded test structure, so that they each produce a topology identical to at least one portion of an extracted path,

   - a measurement control device (MES) for performing at least one first measurement of a physical quantity on said at least one degraded test structure and at least a second measurement, identical to the first measurement, on said at least one non-degraded test structure.
2. The test system according to claim 1, wherein each test structure (ST) comprises combinatorial logic cells (A, B, C) and memory logic cells (R1, R2).
3. The test system as claimed in one of the preceding claims, wherein the device (CTR) for controlling the integrated characterization circuit comprises a device (CTEMP) for controlling the temperature of at least one test structure.
4. The test system as claimed in one of the preceding claims, wherein the device (CTR) for controlling the integrated characterization circuit comprises a generator (GSTIM) of stimuli that are intended to be injected at an input point of at least one test structure.
5. The test system as claimed in one of the preceding claims, wherein the device (CTR) for controlling the integrated characterization circuit comprises a device (CTENS) for controlling the supply voltage of at least one test structure.
6. The test system as claimed in one of the preceding claims, wherein the system further comprises an estimation device (EST) configured to determine, from the measurements supplied by the measurement device, an estimation of a variation over time of at least one physical quantity of the application-specific integrated circuit.
7. The test system as claimed in one of the preceding claims, wherein the physical quantity is a propagation time and the measurement control device (MES) is able to measure a propagation time of a signal between two memory logical cells.
8. Test system as claimed in one of claims 1 to 6 wherein the physical quantity is a current that is consumed and the characterization integrated circuit (CAR) furthermore comprises, for each test structure (ST1, ST2), a device (DMC) for measuring the current consumed in the test structure that is able to interact with the measurement control device (MES).
9. A method for testing an application-specific integrated circuit represented by a description comprising a set of paths linking a plurality of logic cells, the method being implemented by way of a test system (SYS) comprising an integrated characterization circuit (CAR) comprising at least two configurable test structures (ST1, ST2), each comprising a plurality of activatable logic cells and a plurality of connectors for activating and interconnecting the logic cells and a test assembly (EDT), the method comprising the steps of:

   - varying (601) at least one physical parameter of at least one configurable test structure so as to accelerate its aging so as to obtain at least a degraded test structure,

   - receiving (602) a description of an application-specific integrated circuit and extracting at least one path from the description,

   - activating and interconnecting (603) at least a subset of logic cells of at least one degraded test structure and of at least one non-degraded test structure, so that each produces a topology identical to at least one part of an extracted path,

   - performing (604) at least one first measurement of a physical quantity on said at least one degraded test structure and at least one second measurement, identical to the first measurement, on said at least one non-degraded test structure.
10. The method for testing an application-specific integrated circuit as claimed in claim 9, wherein the portion of the path extracted from the description of the integrated application circuit comprises at least three logic cells connected in series.
11. The method for testing an application-specific integrated circuit as claimed as in claim 10, wherein said subset of activated and interconnected logic cells furthermore comprises:

    - an additional memory logical cell connected upstream of the three extracted logical cells if the first logical cell of the portion of the extracted path is not a memory logical cell,

    - an additional logical memorization cell connected downstream of the three extracted logical cells if the last logical cell of the portion of the extracted path is not a memorization logical cell.
12. The method for testing an application-specific integrated circuit as claimed as in either of claims 10 or 11 wherein the measurement of at least one physical quantity is carried out at least on a memory logic cell of said subset.
13. The method for testing an application-specific integrated circuit as claimed as in claim 12, wherein the method is iterated by varying the portion of the extracted path using a sliding window to cover the entire path.
14. The method for testing an application-specific integrated circuit as claimed as in one of claims 9 to 13 wherein said physical parameter is selected among a temperature of the circuit, a supply voltage, a stimulus injected at the input of the circuit of the variable nature and duration.
15. The method for testing an application-specific integrated circuit as claimed as in one of claims 9 to 14, furthermore comprising estimating (605) a variation over time of at least one physical quantity of the application-specific integrated circuit from the measurements performed on said at least one degraded test structure and on said at least one non-degraded test structure.
16. The method for testing an application-specific integrated circuit as claimed as in claim 15, wherein the estimation (605) comprises calculating the difference between two identical measurements performed on said at least one degraded test structure and on said at least non-degraded test structure.
17. The method for testing an application-specific integrated circuit as claimed as in claim 16 wherein the estimation (605) comprises calculating a ratio between a sum of the differences between two identical measurements performed on said at least one degraded test structure and on said at least one non-degraded test structure and a sum of the measurements performed on said at least one non-degraded test structure.
18. The method for testing an application-specific integrated circuit as claimed as in claim 17, wherein the physical quantity is a propagation time or a current that is consumed.

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