EP2701028B1

EP2701028B1 - An integrated circuit with an external reference resistor network

Info

Publication number: EP2701028B1
Application number: EP12175926.0A
Authority: EP
Inventors: Rob Fronen; Adrian Joita; Adriana Butur
Original assignee: Rohm Co Ltd
Current assignee: Rohm Co Ltd
Priority date: 2012-07-11
Filing date: 2012-07-11
Publication date: 2017-04-05
Anticipated expiration: 2032-07-11
Also published as: EP2701028A1

Description

The invention relates to an integrated circuit comprising an integrated reference current generation circuit connected via network connection pins to an external reference resistor network.
In many applications an integrated circuit IC integrated on a chip comprises an integrated reference current generation circuit which is provided to generate a reference current for different circuits integrated on the chip. An on-chip reference current is created in conventional integrated circuits by means of an external resistor across which the reference circuit maintains a constant and well-defined reference voltage V_ref. This can be accomplished by means of a differential amplifier which regulates the gate voltage of a MOSFET in a closed loop manner. A current flowing through the transistor is equal to I_ref = V_ref/R, wherein R forms the resistance of the external reference resistor. The reference current I_ref provided by the integrated reference current generation circuit connected to the external reference resistor can therefore be adjusted in a wide range of values by selecting the external resistor value R accordingly. The generated reference current can be used within the integrated circuit for different functionalities such as adjusting a frequency, output current or a delay time etc.
Further, it may happen that the external resistor is partly damaged or broken with the consequence that the integrated circuit receives a reference current I_ref generated by the integrated reference current generation circuit connected to the external reference resistor with a wrong current strength and operates outside specified parameter ranges. Moreover, a deviation of the generated reference current from a desired set reference current cannot be detected or diagnosed and no correction of the situation will be performed.
Fig. 1 shows a conventional circuit which is used in a conventional integrated circuit to avoid the above-mentioned disadvantages, in particular a situation where a reference current with a wrong reference current value is generated because an external reference resistor has been damaged or a wire to the external reference resistor has been cut. As can be seen in Fig. 1 the integrated circuit IC comprises a reference voltage source V_ref which supplies a reference voltage to corresponding amplifiers that regulate a gate voltage of an associated MOSFET in a closed loop manner, wherein a current flowing through each MOSFET is given by: I_ref = V_ref/R_ref. As can be seen the integrated circuit IC comprises the reference current generation circuit three times each circuit being connected to a corresponding external resistor R_ref. The reference current generation circuits in the conventional integrated circuit IC as shown in Fig. 1 are connected to an arbiter circuit which monitors if any of the three reference currents is deviating more than a preset percentage from the other two reference currents. If the arbiter circuit detects that one of the reference currents I_ref is deviating too far from the other two reference currents, it selects one of the unaffected two other reference currents and outputs an error flag indicating that an error in one of the reference current generation circuits has occurred.
A disadvantage of the conventional integrated circuit IC shown in Fig. 1 is that three network connection pins have to be used to connect three external reference resistors R_ref to the integrated circuit IC. Further, the space for providing pins connecting the integrated circuit IC to the external electronic circuitry is limited. Moreover, each network connection pin used for one of the integrated reference current generation circuits can not be used for other purposes so that the functionality of the integrated circuit IC is limited.
US 2008/0073976 A1 relates to a method for increasing the availability and redundancy of an analogue current output. A first set of current sources is activated to generate an output current. A current source of this first set of current sources is cyclically checked for serviceability, and a resulting output current is generated in equal parts by other current sources of the first set of current sources. If an unserviceability of a checked current source is determined, the respective current source is disconnected.
Accordingly, it is an object of the present invention to provide an integrated circuit having an integrated reference current generation circuit which provides a constant reference current even when one external resistor value deviates from a set value and which needs less connection pins for connecting external reference resistors to the integrated circuit.
This object is achieved by an integrated circuit comprising the features of claim 1.
Accordingly, the integrated circuit according to the present invention provides an integrated reference circuit that detects any deviation of a resistor value and compensates this deviation such that the value of the generated reference current I_ref remains unaffected and unchanged.
In a further possible embodiment of the integrated circuit according to the present invention a fourth integrated switch is adapted to interrupt a first external current flowing through an integrated transistor and a first network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fourth switch by said integrated control circuit.
In a further possible embodiment of the integrated circuit according to the present invention further a fifth integrated switch is adapted to interrupt a second external current flowing through an integrated transistor via a second network connection pin of said integrated circuit to said external reference resistor network in response to a control signal applied to said fifth switch by said integrated control circuit.
In a further possible embodiment of the integrated circuit according to the present invention if said integrated control circuit detects a change from a predetermined ratio between the first and second external current it turns off consecutively the first external current and the second external current by controlling the fourth and fifth integrated switch and compares measured voltages at the first and second network connection pin of said integrated circuit with expected voltages at the first and second network connection pin of said integrated circuit to identify a failing resistor of said external reference resistor network.
In a further possible embodiment of the integrated circuit according to the present invention the control circuit is adapted to control the integrated switches such that the identified failing resistor of said external reference resistor network is shortened to maintain the reference current generated by said integrated reference current generation circuit constant.
In a further possible embodiment of the integrated circuit according to the present invention the reference resistor network is connected via wires to the network connection pins of said integrated circuit and comprises resistors each having a predetermined reference resistance.
In a further possible embodiment of the integrated circuit according to the present invention the external reference resistor network comprises three reference resistors in a Π-configuration connected to a first and second network connection pin of said integrated circuit.
In a further possible embodiment of the integrated circuit according to the present invention a first reference resistor of said external reference resistor network is connected between both network connection pins of said integrated circuit.
In a further possible embodiment of the integrated circuit according to the present invention a second reference resistor of said external reference resistor network is connected between a first network connection pin of said integrated circuit and a reference potential.
In a further possible embodiment of the integrated circuit according to the present invention a third reference resistor is connected between a second network connection pin of said integrated circuit and a reference potential.
In a further possible embodiment of the integrated circuit according to the present invention the integrated reference current generation circuit comprises
a first reference voltage source adapted to generate a first reference voltage and
a second reference voltage source adapted to generate a second reference voltage being higher than the first reference voltage by a predetermined voltage ratio.
In a further possible embodiment of the integrated circuit according to the present invention the reference current is a weighted sum of the first external current flowing through a first integrated transistor and the first connection pin of said integrated circuit to said external reference resistor network and of the second external current flowing through a second integrated transistor of the second network connection pin of said integrated circuit to said external reference resistor network,
wherein the reference current I_ref is given by: $I_{ref} = I_{1} + m \cdot I_{2},$
wherein m is a predetermined weighting factor.
In a further possible embodiment of the integrated circuit according to the present invention the reference current generated by said integrated reference current generation circuit is in a normal operation of said integrated circuit given by: $I_{ref} = [\frac{1}{R 2} + (m - 1) (K - 1) \frac{1}{R 1} + m \cdot K \frac{1}{R 3}] \cdot \frac{Vref 1}{2}$

wherein R1, R2, R3 are resistance values of the first, second and third reference resistors of said reference resistor network,
m is the weighting factor,
K is the predetermined voltage ratio,
V_ref is the reference voltage generated by the first reference voltage source of the integrated circuit.

In a further possible embodiment of the integrated circuit according to the present invention the sum of the weighting factor m and the voltage ratio K is set to the value two: $m + K = 2$
with
the weighting factor (m) being smaller than one (m < 1), and the voltage ratio (K) being higher than one (K > 1).
In a further possible embodiment of the integrated circuit according to the present invention the resistance value of the first and second reference resistors of said reference resistor network are equal (R1 = R2 = R).
In a further possible embodiment of the integrated circuit according to the present invention the voltage ratio K is set to K = 1,5 and the weighting factor m is set to m = 0,5 and the third reference resistor has a resistance value of 3/5 R with R being the resistance values of the first and second reference resistors R1, R2 of said reference resistor network.
In a further possible embodiment of the integrated circuit according to the present invention if a wire connecting said external reference resistor network with said integrated circuit is cut the reference current generated by said integrated reference current generation circuit is maintained and does decrease by a predetermined percentage.
In a further possible embodiment of the integrated circuit according to the present invention the integrated control circuit generates an error flag signal indicating that a failure has occurred in said external reference resistor network if such a failure is detected by said integrated control circuit.
In the following possible embodiments of the integrated circuit having an integrated reference current generation circuit connected to an external reference resistor network are explained in more detail with reference to the enclosed figures.

Fig. 1: shows a conventional circuit as used in a conventional integrated circuit for detecting a faulty resistor of an external reference resistor network;
Fig. 2: shows a block diagram for illustrating a possible embodiment of an integrated circuit comprising an integrated reference current generation circuit connected to an external reference resistor network according to the present invention;
Fig. 3: shows a circuit diagram of a possible implementation of an integrated circuit comprising an integrated reference current generation circuit connected to an external reference resistor network according to the present invention;
Fig. 4: shows a possible circuit board design which can be used for connecting an external reference resistor network to an integrated reference current generation circuit used by an integrated circuit according to the present invention.

As can be seen from Fig. 2 the integrated circuit IC 1 according to the present invention comprises at least one integrated reference current generation circuit 2 generating an internal reference current I_ref used by circuits of the integrated circuit IC for different functions such as adjusting a frequency, an output current or a delay time etc. The reference current generation circuit 2 is connected to an integrated control circuit 3 of the IC 1. The reference current generation circuit 2 of the IC 1 is connected via a first and second network connection pin 4-1, 4-2 to an external reference resistor network 5 comprising in the shown implementation three resistors 6-1, 6-2, 6-3 connected to each other in a Π circuit configuration and having the reference resistor values R1, R2, R3, respectively. The integrated reference current generation circuit 2 is adapted to generate a reference current I_ref for the integrated circuit 1 and has reference voltage sources each supplying a reference voltage via a first and second integrated switch to a corresponding amplifier that is adapted to regulate a control voltage of an integrated transistor connected to the respective amplifier such that the generated reference current is a weighted sum of the external currents I₁, I₂ each flowing through one of the integrated transistors via the network connections pins 4-1, 4-2 of the integrated circuit 1 to the external reference resistor network 5 connected to the integrated circuit 1 as shown in Fig. 2. The network connection pins 4-1, 4-2 are connectable to each other by means of a third integrated switch SW3 and to a reference potential GND by means of a first switch SW1 and second switch SW2 integrated in the integrated circuit IC 1 as shown in Fig. 3.
The integrated control circuit 3 as shown in Fig. 2 is adapted to detect a failure in the external reference resistor network 5 on the basis of the monitored external currents I₁, I₂ of the integrated switches IC such that the reference current I_ref generated by said integrated reference current generation circuit 2 is maintained constant even if a failure occurs in said external reference resistor network 5.
Fig. 3 shows a possible embodiment of an integrated circuit 1 according to the present invention in more detail. As can be seen in Fig. 3 the integrated reference current generation circuit 2 comprises a first reference voltage source 7 connected by means of a connection pin 8 to a reference potential GND as shown in Fig. 3. Moreover, the integrated circuit 1 comprises a second reference voltage source 9 generating a second reference voltage. The second reference voltage source 9 is adapted to generate a second reference voltage V_ref2 being higher than the first reference voltage V_ref1 generated by the first reference voltage source 7 by a predetermined voltage ratio K (V_ref2 = K·V_ref1). The first reference voltage source 7 is connected via first controllable switch SW1 of the IC 1 to a corresponding amplifier 10 being a differential amplifier that is adapted to regulate a control voltage of an integrated transistor 11 connected to the output of the respective differential amplifier 10 such that a first external current I₁ flows through the first network connection pin 4-1 to the external reference resistor network 5. The second reference voltage source 9 supplies the generated reference voltage also to an input of a differential amplifier 12 whose output is connected to a second transistor 13. The differential amplifier 12 is connected to regulate a control voltage of the integrated second transistor 13 connected to the differntial amplifier such that a second current I₂ flows through the second network connection pin 4-2 to the external reference resistor network 5. The currents flowing to the external reference resistor network 5 are split or minored with predefined ratios using associated transistors connected in parallel to the transistors 11, 13, respectively. As can be seen transistor 11 is a MOSFET having a gate connected to the output of the operational amplifier 10 to which a similar transistor 11' is connected in parallel such that the external current I₁ flowing through the connection pin 4-1 is split according to a 1:1 ratio so that half of the amplitude of the external current I₁ is applied to integrated control circuit 3 if a fourth integrated switch SW4 of the IC 1 is closed. In the same manner the transistors 13', 13" are connected in parallel to the other transistor 13 so that the external current I₂ is split and a predetermined fraction of the current I₂ is applied to the integrated control circuit 3 if the switch SW5 of the IC 1 is closed. As can be seen in Fig. 3 the generated reference current I_ref is output by the integrated reference current generation circuit 2 ??? is a weighted sum of the external currents I₁, I₂ flowing through one of the integrated transistors 11, 13 and the network connection pins 4-1, 4-2 of said integrated circuit 1 to the external reference resistor network 5 connected to the integrated circuit 1.
As can be seen from Fig. 3 the first and second network connection pin 4-1, 4-2 can be connected to each other by means of a third integrated switch SW3 controlled by the integrated control circuit 3. Moreover, the network connection pins 4-1, 4-2 can also be connected to a reference potential GND by means of the controlled first and second switch SW1, SW2 as shown in Fig. 3.
The integrated circuit 1 further comprises a fourth integrated switch SW4 which is adapted to interrupt a first external current I₁ flowing through a first integrated transistor 11 of the first network connection pin 4-1 of said integrated circuit 1 to said external reference resistor network 5 in response to a control signal applied to the fourth switch SW4 by said integrated control circuit 3 as shown in Fig. 3.
The fifth integrated switch SW5 is adapted to interrupt the second external current I₂ flowing through an integrated transistor 13 of the second network connection pin 4-2 of said integrated circuit 1 to said external reference resistor network 5 in response to a control signal applied to said fifth switch SW5 by said integrated control circuit 3.
In a possible embodiment of the integrated circuit 1 according to the present invention if the integrated control circuit 3 detects a change from a predetermined ratio between the first and second external current I₁, I₂ it turns off consecutively the first external current I₁ and the second external current I₂ by controlling the fourth and fifth integrated switch SW4, SW5 and then compares the measured voltages at the first and second network connection pin 4-1, 4-2 of said integrated circuit IC 1 with expected voltages at the first and second network connection pin 4-1, 4-2 of said integrated circuit 1 to identify a failing resistor of the external reference resistor network 5.
The integrated control circuit 3 is further adapted to control the integrated switches SW1, SW2, SW3, SW4, SW5 such that the identified failing resistor of the external reference resistor network 5 is shortcut to maintain the reference current I_ref generated by the integrated reference current generation circuit 2 constant.
In the embodiment shown in Fig. 3 the external reference resistor network 5 comprises three reference resistors 6-1, 6-2, 6-3 with a Π configuration connected to the first and second network connection pin 4-1, 4-2 of the integrated circuit 1. The first reference resistor 6-1 of said external reference resistor network 5 is connected between both network connection pins 4-1, 4-2 of the integrated circuit 1. A second reference resistor 6-2 of said external reference resistor network is connected between a first network connection pin 4-1 of said integrated circuit 1 and a reference potential that can be formed by a ground potential GND. A third reference resistor 6-3 of the reference resistor network 5 is connected between the second network connection pin 4-2 of said integrated circuit 1 and the reference potential GND as shown in Fig. 3.
The generated reference current I_ref is a weighted sum of the first external current I₁ flowing through the first integrated transistor 11 of the IC 1 and the first network connection pin 4-1 of the integrated circuit IC 1 to said external reference resistor network 5 and of the second external current I₂ flowing through a second integrated transistor 13 of the IC 1 and the second network connection pin 4-2 of said integrated circuit 1 to said external reference resistor network 5,
wherein the reference current I_ref is given by: $I_{ref} = I_{1} + m \cdot I_{2},$
wherein m is a predetermined weighting factor.
In a possible implementation the reference current I_ref generated by said integrated reference current generation circuit 2 is given by: $I_{ref} = [\frac{1}{R 2} + (m - 1) (K - 1) \frac{1}{R 1} + m \cdot K \frac{1}{R 3}] \cdot \frac{Vref 1}{2}$

wherein R1, R2, R3 are resistance values of the first, second and third reference resistors 6-1, 6-2, 6-3 of the reference resistor network 5,
m is the predetermined weighting factor,
K is the predetermined voltage ratio, and
V_ref1 is the reference voltage generated by the first reference voltage source 7 of the integrated circuit 1.

In a possible implementation the sum of the predetermined weighting factor m and the voltage ratio K is set to a value 2: $m + K = 2$
wherein in a possible implementation the weighting factor (m) is smaller than one (m < 1), and the voltage ratio (K) is higher than one (K > 1).
In a possible embodiment the resistance value of the first and second resistor R1, R2 of said reference resistor network 5 are equal (R1 = R2 = R). In a possible implementation if the voltage ratio is set to K = 1,5 and the weighting factor m is set to m = 0,5 the third reference resistor 6-3 comprises a resistance value of 3/5 R wherein R is the resistance values of the two other reference resistors 6-1, 6-2 of the reference resistor network 5. Other combinations such as K = 4/3 and m = 2/3 are also possible leading to R3 = 8 x R. After a detection of a deviation of a resistor the control circuit 3 can identify the failing resistor by consecutively switching off I₁ and I₂ and by comparing the sensed voltage at the terminals with expected reference voltages. Accordingly, the integrated control circuit 3 is able to identify at each of the three resistors 6-1, 6-2, 6-3 within the external reference resistor network 5 an occurred malfunction and then to shortcut the identified faulty resistor such that the generated reference current I_ref is maintained constant.
If one of the resistors 6-1, 6-2, 6-3 has a resistor value R1, R2, R3 deviating from a preset value R_set more than 10% the control circuit 3 can deactivate the identified faulty resistor by controlling the integrated switches SW1, SW2, SW 3 accordingly. By closing switch SW3 the first resistor 6-1 is shortcut in case that its resistance value deviates from a preset value too much. Consequently, if a single faulty resistor within the external resistor network 5 is detected the control circuit 3 can perform a switching operation such that the generated reference current I_ref is constant and is unaffected by the faulty resistor. In case of another type of malfunction where a wire connecting the external reference resistor network 5 of the integrated circuit 1 is cut the reference current I_ref generated by the integrated reference current generation circuit 2 is maintained constant and decreases by a predetermined percentage. Accordingly, in this scenario or situation the circuit according to the present invention operates such that a predetermined percentage of the reference current I_ref is still generated although a wire has been cut. In a possible embodiment if a wire cut is detected this causes a decrease of the reference current I_ref of less than 19%.
In a possible embodiment the control circuit 3 generates in case of a malfunction an error signal (ERROR) indicating that a malfunction of the external reference resistor network 5 has occurred. This error signal can also indicate what type of malfunction has occurred, i.e. it can indicate whether there is a faulty resistor 6 in the reference resistor network 5 or a cut wire. In a possible embodiment the ERROR signal also indicates which resistor 6-i is faulty or which wire has been interrupted to a higher software layer.
Fig. 4 shows a possible printed circuit board PCB design which can be used for connecting an integrated circuit 1 according to the present invention with an external reference resistor network 5. As can be seen in Fig. 4 the separation of wires for all three resistors 6-1, 6-2, 6-3 reduces the risk of a wire cut. Moreover, a wire cut error can only occur as a soldering error or a IC pin to the PCB. This is diagnosed and has an effect in reducing less than 19% of the reference current I_ref generated by the reference current generation circuit 2. Further, a loss of ground wire is prevented by double ground wires via ground connection of the integrated circuit 1. In a possible embodiment the integrated circuit 1 according to the present invention can be used in automotive applications. The integrated circuit IC 1 is compliant with ISO 26262 being an automotive safety standard.

Claims

An integrated circuit, IC, (1) connectable to an external resistor network (5) comprising three resistors (6-1, 6-2, 6-3) in a π-configuration, the integrated circuit (1) comprising:
- an integrated reference current generation circuit (2) adapted to generate a reference current (I_ref) for said integrated circuit (1) and having a first reference voltage source (7), a first integrated switch (SW1), a first amplifier (10), a first integrated transistor (11), a first network connection pin (4-1), a second reference voltage source (9), a second integrated switch (SW2), a second amplifier (12,) a second integrated transistor (13) and a second network connection pin (4-2),

- wherein said first reference voltage source (7) supplying a reference voltage (V_ref1) via said first integrated switch (SW1) to said first amplifier (10);

- said second reference voltage source (9) supplying a reference voltage (V_ref2) via said second integrated switch (SW2) to said second amplifier (12);

- the generated reference current (I_ref) is a weighted sum of a first current (I₁) flowing through said integrated first transistor (11) via said first network connection pin (4-1) and a second current (I₂) flowing through said integrated second transistor (13) via said second network connection pin (4-2) of said integrated circuit (1) to said external reference resistor network (5) connectable to said integrated circuit, IC (1); and

- said network connection pins (4-1, 4-2) are connectable to each other by means of a third integrated switch (SW3) and to a reference potential (GND) by means of said first and second switch (SW1, SW2);

- the said integrated circuit (1) further comprising an integrated control circuit (3) adapted to detect a failure in said external reference resistor network (5) on the basis of the first and the second current (I₁, I₂) and to control said integrated switches (SW1, SW2, SW3) such that the reference current (I_ref) generated by said integrated reference current generation circuit (2) is maintained constant if a failure occurs in said external reference resistor network (5) ;

- a fourth integrated switch (SW4) adapted to interrupt the first current (I₁) flowing through said first integrated transistor (11) and said first network connection pin (4-1) of said integrated circuit (1) to said external reference resistor network (5) in response to a control signal applied to said fourth switch (SW4) by said integrated control circuit (3); and

- a fifth integrated switch (SW5) adapted to interrupt said second current (I₂) flowing through an said second integrated transistor (13) via said second network connection pin (4-2) of said integrated circuit (1) to said external reference resistor network (5) in response to a control signal applied to said fifth switch (SW5) by said integrated control circuit (3).
The integrated circuit according to claim 1,
wherein if said integrated control circuit (3) detects a change from a predetermined ratio between the first and second external current (I₁, I₂) it turns off consecutively the first current (I₁) and the second current (I₂) by controlling the fourth and fifth integrated switch (SW4, SW5) and compares measured voltages at the first and second network connection pin (4-1, 4-2) of said integrated circuit (1) with expected voltages at the first and second network connection pin (4-1, 4-2) of said integrated circuit (1) to identify a failing resistor (6-1) of said external reference resistor network (5).
The integrated circuit according to claim 2,
wherein the integrated control circuit (3) is adapted to control the integrated switches (SW1, SW2, SW3, SW4, SW5) such that the identified failing resistor of said external reference resistor network (5) is shortened to maintain the reference current (I_ref) generated by said integrated reference current generation circuit (2) constant.
The integrated circuit according to one of the preceding claims 1 to 3,
wherein said reference resistor network (5) is connectable via wires to the network connection pins (4-1, 4-2) of said integrated circuit (1) and comprises resistors (6) each having a predetermined reference resistance.
The integrated circuit according to one of the preceding claims 1 to 4,
wherein the three reference resistors (6-1, 6-2, 6-3) of said external reference resistor network (5) are connectable to said first and second network connection pins (4-1, 4-2) of said integrated circuit (1).
The integrated circuit according to one of the preceding claims 1 to 5,
- wherein a first reference resistor (6-1) of said external reference resistor network (5) is connectable between both network connection pins (4-1, 4-2) of said integrated circuit,

- a second reference resistor (6-2) of said external reference resistor network (5) is connectable between a first network connection pin (4-1) of said integrated circuit (1) and a reference potential, and

- a third reference resistor (6-3) is connectable between a second network connection pin (4-2) of said integrated circuit (1) and said reference potential.
The integrated circuit according to one of the preceding claims 1 to 6,
wherein said second reference voltage (V_ref2) being higher than the first reference voltage by a predetermined voltage ratio (K).
The integrated circuit according to one of the preceding claims 1 to 7,
wherein said reference current (I_ref) is a weighted sum of the first current (I₁) flowing through a first integrated transistor (11) and the first connection pin (4-1) of said integrated circuit (1) to said external reference resistor network (5) and of the second current (I₂) flowing through a second integrated transistor (13) and the second network connection pin (4-2) of said integrated circuit to said external reference resistor network (5): $I_{ref} = I_{1} + m \cdot I_{2},$
wherein m is a predetermined weighting factor.
The integrated circuit according to claim 8,
wherein the reference current (I_ref) generated by said integrated reference current generation circuit (2) in a normal operation given by: $I_{ref} = [\frac{1}{R 2} + (m - 1) (K - 1) \frac{1}{R 1} + m \cdot K \frac{1}{R 3}] \cdot \frac{Vref 1}{2}$

wherein R1, R2, R3 are resistance values of the first, second and third reference resistors (6-1, 6-2, 6-3) of said reference resistor network (5),

m is the weighting factor,

K is the predetermined voltage ratio,

V_ref1 is the reference voltage generated by the first reference voltage source (7).
The integrated circuit according to claim 8 or 9,
wherein the sum of the weighting factor (m) and the voltage ratio (K) is set to the value two: $m + K = 2$
with
the weighting factor (m) being smaller than one (m < 1), and

the voltage ratio (K) being higher than one (K > 1).
The integrated circuit according to one of the preceding claims 5 to 10,
wherein the resistance value (R1, R2) of the first and second reference resistors (6-1, 6-2) of said reference resistor network (5) are equal (R1 = R2 = R).
The integrated circuit according to claim 10 or 11,
wherein for the voltage ratio (K) being set to K = 1,5 and the weighting factor (m) being set to m = 0,5 the third reference resistor (6-3) has a resistance value of 3/5 R with R being the resistance values of the first and second reference resistors (6-1, 6-2) of said reference resistor network (5).
The integrated circuit according to one of the preceding claims 1 to 12,
wherein if a wire connecting said external reference resistor network (5) with said integrated circuit (1) is cut the reference current (I_ref) generated by said integrated reference current generation circuit (2) is maintained and does decrease by a predetermined percentage.
The integrated circuit according to one of the preceding claims 1 to 13,
wherein said integrated control circuit (3) generates an error flag signal indicating that a failure has occurred in said external reference resistor network (5) if such a failure is detected by said integrated control circuit (3).