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EP2603805A4 - Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations - Google Patents

Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

Info

Publication number
EP2603805A4
EP2603805A4 EP11816812.9A EP11816812A EP2603805A4 EP 2603805 A4 EP2603805 A4 EP 2603805A4 EP 11816812 A EP11816812 A EP 11816812A EP 2603805 A4 EP2603805 A4 EP 2603805A4
Authority
EP
European Patent Office
Prior art keywords
oscilloscope
jitter
facilitating
circuitry
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11816812.9A
Other languages
German (de)
French (fr)
Other versions
EP2603805A2 (en
Inventor
Peng Li
Masashi Shimanouchi
Sergey Shumarayev
Weiqi Ding
Sriram Narayan
Daniel Tun Lai Chow
Mingde Pan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/884,305 external-priority patent/US8504882B2/en
Application filed by Altera Corp filed Critical Altera Corp
Publication of EP2603805A2 publication Critical patent/EP2603805A2/en
Publication of EP2603805A4 publication Critical patent/EP2603805A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31709—Jitter measurements; Jitter generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/3171—BER [Bit Error Rate] test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31716—Testing of input or output with loop-back
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
EP11816812.9A 2010-08-13 2011-08-02 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations Withdrawn EP2603805A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US85622610A 2010-08-13 2010-08-13
US12/884,305 US8504882B2 (en) 2010-09-17 2010-09-17 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
PCT/US2011/046239 WO2012021332A2 (en) 2010-08-13 2011-08-02 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

Publications (2)

Publication Number Publication Date
EP2603805A2 EP2603805A2 (en) 2013-06-19
EP2603805A4 true EP2603805A4 (en) 2016-10-19

Family

ID=45568125

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11816812.9A Withdrawn EP2603805A4 (en) 2010-08-13 2011-08-02 Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations

Country Status (3)

Country Link
EP (1) EP2603805A4 (en)
CN (1) CN103140768B (en)
WO (1) WO2012021332A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8837571B1 (en) * 2013-08-02 2014-09-16 Altera Corporation Apparatus and methods for on-die instrumentation
CN105162543B (en) * 2015-08-17 2017-12-08 华北水利水电大学 A kind of device and method for the test of SDH clock jitters
CN106656229B (en) * 2016-11-25 2019-02-26 硅谷数模半导体（北京）有限公司 The method for implanting and circuit and eye figure monitor of shake data
CN110446935B (en) * 2017-03-17 2021-09-14 光梓信息科技（上海）有限公司 Method and apparatus for built-in self-test
KR102264159B1 (en) * 2017-06-08 2021-06-11 삼성전자주식회사 Serial communication interface circuit performing external loopback test and electrical device including the same
CN109217979B (en) * 2017-06-30 2021-06-15 华为技术有限公司 Communication method, device and storage medium
CN115086588A (en) * 2021-03-10 2022-09-20 苏州佳世达电通有限公司 Signal improvement system and signal improvement method
TWI806539B (en) * 2022-04-08 2023-06-21 瑞昱半導體股份有限公司 Testing system and testing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030023912A1 (en) * 2001-07-24 2003-01-30 Xilinx, Inc. Integrated testing of serializer/deserializer in FPGA
US20090304054A1 (en) * 2008-06-04 2009-12-10 Stmicroelectronics, Inc. Serdes with jitter-based built-in self test (bist) for adapting fir filter coefficients
US7743288B1 (en) * 2005-06-01 2010-06-22 Altera Corporation Built-in at-speed bit error ratio tester

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002329836A1 (en) * 2001-08-22 2003-06-10 Wavecrest Corporation Method and apparatus for measuring a waveform
US7251764B2 (en) * 2003-05-27 2007-07-31 International Business Machines Corporation Serializer/deserializer circuit for jitter sensitivity characterization
US7869544B2 (en) * 2008-01-03 2011-01-11 International Business Machines Corporation System for measuring an eyewidth of a data signal in an asynchronous system
US20100097087A1 (en) * 2008-10-20 2010-04-22 Stmicroelectronics, Inc. Eye mapping built-in self test (bist) method and apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030023912A1 (en) * 2001-07-24 2003-01-30 Xilinx, Inc. Integrated testing of serializer/deserializer in FPGA
US7743288B1 (en) * 2005-06-01 2010-06-22 Altera Corporation Built-in at-speed bit error ratio tester
US20090304054A1 (en) * 2008-06-04 2009-12-10 Stmicroelectronics, Inc. Serdes with jitter-based built-in self test (bist) for adapting fir filter coefficients

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2012021332A2 *

Also Published As

Publication number Publication date
EP2603805A2 (en) 2013-06-19
CN103140768B (en) 2016-01-27
CN103140768A (en) 2013-06-05
WO2012021332A2 (en) 2012-02-16
WO2012021332A3 (en) 2012-04-12

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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17P Request for examination filed

Effective date: 20130305

AK Designated contracting states

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Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20160916

RIC1 Information provided on ipc code assigned before grant

Ipc: H04L 7/033 20060101ALI20160912BHEP

Ipc: G01R 31/317 20060101ALI20160912BHEP

Ipc: G01R 31/303 20060101AFI20160912BHEP

17Q First examination report despatched

Effective date: 20190625

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20190725