EP2394494A1

EP2394494A1 - Electronic array comprising a plurality of electronic units

Info

Publication number: EP2394494A1
Application number: EP09779020A
Authority: EP
Inventors: Michaël DEMEYERE
Original assignee: AGC Glass Europe SA
Current assignee: AGC Glass Europe SA
Priority date: 2009-02-06
Filing date: 2009-02-06
Publication date: 2011-12-14
Also published as: WO2010088961A1

Abstract

The invention relates to an electronic array comprising a power supply unit (6), a plurality of electronic units being arranged in series to one another, wherein the plurality of electronic units each comprise a management unit adapted for addressing each electronic unit comprised by the plurality of electronic units individually. In this way, a simple, cheap and a steadily ready-to-operate electronic array preferably adapted for electronic circuit applications is provided.

Description

ELECTRONIC ARRAY COMPRISING A PLURALITY OF ELECTRONIC

UNITS

FIELD OF THE INVENTION

The invention relates to the field of electronic arrays comprising a plurality of electronic units being arranged in series to one another, wherein such electronic arrays are preferably adapted for electronic circuit applications especially for lighting and/or displays and signage as well as to methods of manufacturing and operating such arrays and methods of use of lighting.

BACKGROUND OF THE INVENTION

It is generally known for printed circuit boards, PCB for short that the physical arrangement of electronic units is not significantly influenced by the connection mode of the electronic units with respect to one another because the resistivity of the conductive tracks, e.g. made of copper, is usually negligible. Therefore, in conventional electronics on PCB' s, such conductive tracks can have any dimensions. In particular, these dimen- sions can be as long as necessary while the system performance is not suffering. The most conventional and effective way to proceed is to connect all electronic units in parallel.

However, on a conductive resistive substrate such as glass comprising a resistive con- ductive layer applied to the glass, it becomes necessary to ensure that the conductive tracks are as short and as wide as possible. It is conventional to remove portions of the conductive layer in order to form conductive tracks which sometimes show a large resistance.

A conventional efficient solution is to arrange an electronic array (also referred to as an electronic matrix in the following) of electronic units such that it is provided in a column, i.e. in a first dimension of such an electronic array arranged in a current direction, a plurality of electronic units that are connected in series to one another. Columns of electronic components are connected in parallel with each other. The conventional solution is illustrated in Fig. 1. This figure shows a DC power supply unit 1 and an electronic array 12 comprising a plurality of electronic units. Conductive areas which are isolated from one another and the link between such areas performed by electronic units are illustrated in this figure. The electronic units are shown as small squares in Fig. 1. Fig. 2 illustrates the implementation of a data bus unit 2 in such an electric array 12 comprising a plurality of electronic units. The electronic units are indicated as squares in Fig. 2.

If it is needed to individually address each of the electronic units, it is well known that the supply of distinct control signals to the electronic units is mandatory.

However, a problem of such an electronic array arrangement is that the electronic units are not individually addressable: the electric current flowing through the electronic units connected in series to one another is bound to be the same for each electronic unit.

In conclusion, there is a need for improved individual method and apparatus for addressing of electronic units connected in series to one another, and more particularly in the case of a conductive resistive substrate.

SUMMARY OF THE INVENTION

It is the object of the present invention to provide alternative electronic arrays comprising a plurality of electronic units being arranged in series to one another especially to lighting and/or displays and/or signage, as well as methods of manufacturing and operating such arrays and methods of use of lighting.

An advantage of embodiments of the present invention is a possibility for realizing a simple, cheap and a steadily ready-to-operate electronic array preferably adapted for electronic circuit applications such as lighting and/or displays and/or signage. The above object is achieved by an electronic array according to independent claim 1. The electronic array comprises a power supply unit, a plurality of electronic units being arranged in series to one another, wherein the plurality of electronic units each comprise a management unit adapted for addressing each electronic unit individually within the plurality of electronic units.

Therefore, it is an essential idea of the invention to provide an electronic array comprising a plurality of electronic units, wherein each electronic unit is optionally identical or almost identical with the others and further being individually addressable. The plurality of electronic units is most preferably arranged on a conductive resistive substrate such as glass comprising a conductive layer adapted for conducting electricity. According to a preferred embodiment of the invention, the management unit comprises a decoding unit adapted for decoding a command being addressed to the management unit. Most preferably, the management unit further comprises a driving unit adapted for selecting a portion of a physical parameter associated with the plurality of electronic units. Preferably, the physical parameter comprises at least one of electric current, electric voltage, temperature and impedance.

According to another preferred embodiment of the invention, the management unit fur- ther comprises a dissipation unit adapted for dissipating a surplus of a physical parameter, preferably an electric current, being directed to the plurality of electronic units. Most preferably, the plurality of electronic units is arranged on a conductive resistive substrate. Preferably, the conductive resistive substrate corresponds to glass comprising a conductive layer adapted for conducting electricity.

According to yet another preferred embodiment of the invention, the plurality of electronic units comprises a plurality of light emitting devices such as organic light emitting diodes and/or a plurality of light emitting diodes.

It is an aspect of the invention to provide an electronic array comprising a plurality of electronic units, wherein each electronic unit comprises a management unit and each electronic unit is preferably arranged on a conductive resistive substrate. The connection method used is preferably the method described in connection with Fig. 1. The minimum size of electronic array preferably corresponds to two times one, i.e. two lines of two components which are connected in series to each other. All electronic units con- nected in series to one another consume the same electric current. Further, a management unit associated with each electronic unit preferably comprises a decoding unit adapted for decoding a command addressed to it, for instance via a microcontroller. Furthermore, the management unit comprises a control unit adapted for diverting the necessary portion of a physical parameter, preferably the electric current flowing through the electronic unit, in order to fulfil the function of an electronic unit in function of the command addressed to it, preferably via a power driver. Moreover, the management unit comprises a dissipating unit adapted for dissipating the surplus portion of the physic parameter, preferably the electric current flowing through the given electronic unit, preferably via a variable resistive element, such as a varistor, shunting the basic electronic unit.

The present invention also provides a method for use with an electronic array comprising a power supply unit, and a plurality of electronic units being arranged in series to one another, the method comprising: addressing an electronic unit of the plurality of electronic units individually and dissipating a surplus of a physical parameter the electronic unit locally to the electronic unit.

The method may further comprise the step of decoding a command being addressed to the electronic unit.

The physical parameter preferably comprises at least one of electric current through the electronic unit, electric voltage across the electronic unit, temperature of the electronic unit and impedance of the electronic unit.

The step of dissipating a surplus of the physical parameter the electronic unit locally to the electronic unit is preferably a lossy dissipation, e.g. via a variable resistor. To sum up, the present invention provides a possibility to realize an electronic array and a method for use with this array that allows individual addressing of each electronic unit with commands within the plurality of the electronic units, wherein the electronic units are connected in series to one another and are preferably arranged on a conductive resistive substrate.

In this way, a simple, cheap and a steadily ready-to-operate electronic array preferably adapted for electronic circuit applications is provided.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

In the drawings:

Fig. 1 depicts a conventional electronic array;

Fig. 2 depicts the conventional electronic array comprising a data bus unit;

Fig. 3 depicts a schematic implementation of an electronic array according to an embodiment of the invention; and

Fig. 4 depicts a schematic implementation of an electronic unit according to an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the draw- ings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of op- eration in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other ele- ments or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

Similarly, it is to be noticed that the term "coupled", also used in the claims, should not be interpreted as being restricted to direct connections only. The terms "coupled" and "connected", along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Thus, the scope of the expression "a device A coupled to a device B" should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means. "Coupled" may mean that two or more elements are either in direct physical or electrical contact, or that two or more elements are not in direct contact with each other but yet still co-operate or interact with each other.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive as- pects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodi- ments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination. Furthermore, some of the embodiments are described herein as a method or combination of elements of a method that can be implemented by a processor of a computer system or by other means of carrying out the function. Thus, a processor with the necessary instructions for carrying out such a method or element of a method forms a means for carrying out the method or element of a method. Furthermore, an element described herein of an apparatus embodiment is an example of a means for carrying out the function performed by the element for the purpose of carrying out the invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practised without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

The invention will now be described by a detailed description of several embodiments of the invention. It is clear that other embodiments of the invention can be configured according to the knowledge of persons skilled in the art without departing from the true spirit or technical teaching of the invention, the invention being limited only by the terms of the appended claims.

In the following the invention is described in the case of an electronic array comprising at least two dimensions, wherein in each dimension identical or nearly identical electronic units are arranged preferably on a conductive resistive substrate such as glass comprising a conductive layer adapted for conducting electricity. The two dimensions may be defined by Cartesian co-ordinates or polar co-ordinates, for example. The two dimensions may, for instance, be arranged orthogonally within the co-ordinate system chosen. The electronic array comprises a plurality of electronic units being arranged in series to one another wherein each electronic unit comprises a management unit. The present invention is not limited to two dimensions. For example, a lighting scheme in three dimensions is provided by the present invention e.g. an array of a plurality of parallel electronic arrays having two dimensions. As an example, each electronic unit comprises a light emitting device such as one single color LED or a mulitcolour LED such as an RGB LED, and a management unit. The management unit preferably comprises a dissipating element which can be a lossy ele- ment, e.g. variable resistive element (such as a variable resistor) arranged in parallel with the light emitting device, e.g. LED.

The invention may be applied to a panel of laminated glass, comprising a first panel of glass, a second panel of glass, and a plastics interlayer, wherein the first panel of glass and the second panel of glass are laminated together via the plastics interlayer. One glass panel (the conductive resistive substrate) has a conductive layer, preferably a transparent conductive layer and the conductive layer is patterned to make the conductive paths, e.g. by laser ablation. The electronic units and components are arranged on the conductive layer and connected thereto and are laminated between first and second panels of glass. The invention may also be applied to all kind of panel comprising at least one conductive resistive substrate, for instance in a double glazing panel comprising a glass made conductive resistive substrate (first glass panel) carrying the electronic units, an air gap and a second glass panel, the air gap being sandwiched between the first and the second glass panels.

The conductive layer is preferably provided as coplanar and/or thin tin oxide films, e.g. indium tin oxide (ITO) films, and may be applied by any suitable method such as chemical vapour deposition (CVD) coatings or magnetron (sputtered) coatings, thus providing an electrically conductive layer. The conductive layer can also be provided as metallic layer(s) or layer(s) made of any suitable electrically conductive material. The conductive layer can also be applied by other methods such as serigraphy, screen printing, and other suitable method. For instance, the conductive layer may comprises an underlying coating comprising a conductive oxide such as silicon oxide carbide and an overlying coating comprising a conductive metal oxide such as SnO₂IF. The conductive layer may also comprises a substantially color neutral coating stack, e.g. a chemical vapor deposition (CVD) coating stack comprising a silicon oxide carbide undercoat and an overlying SnO₂IF coating, wherein the coating has preferably a resistance of about 15 ohms per square.

Fig. 3 shows a schematic implementation of an electronic array according to an em- bodiment of the invention. An electronic unit 3 is arranged in series with other electronic units 3. This means that its power supply is in the form of a current I and/or in form of an external supply, i.e. an electric voltage V that provides the current with an electric voltage being equivalent to the sum of the operational voltages at each of the electronic units and the voltage drops at the substrate 5 between the connections of the electronic unit 3 and the substrate 5. Therefore, the voltage drop is the current I is multiplied by the respective resistance Rsp. The electronic units can be arranged on a conductive layer applied to a glass panel. Insulating stripes and regions can be removed from the conductive layer, e.g. by etching or laser ablation, to provide conductive paths and isolated regions. Alternatively the conductive paths and isolated regions may be provided be depositing a conductive layer in the relevant pattern. The electronic units 3 are deposited and fixed in electrical contact with the conductive paths.

Moreover, according to an embodiment of the invention, the data path 4 shown in Fig. 3 is represented by a bus of differential type. The bus is also provided by paths in the conductive layer on the glass panel. The bus provides signals to each electronic unit in a range of a common mode voltage which is compatible with the characteristics of each respective electronic unit in the chain of the plurality of electronic units. This can be obtained in the following way: On one side of the data path 4, there is a driver which transmits the data in a differential form under a common mode voltage U_MCH close to the most positive voltage on the substrate 5, and, on the other hand, there is a driver sending the same data under a common mode voltage U_MCL close to the most negative voltage at the substrate 5. Therefore, the data path 4 comprises the sum of n times the resistance R_SD, wherein n indicates the number of electronic units connected in series to one another. The resistance R_SD is provided as conductive paths adjacent to the network of electronic units, i.e. the conductive paths in the conductive layer of a glass panel are arranged adjacent to the network of electronic units 3. Hence, an almost identical and constant electric current flows through each pin at the differential connection, whereby the data drivers drive both sides of the same path simultaneously and in the same direction with an electric voltage.

Fig. 4 shows a schematic implementation of an electronic unit according to a embodiment of the invention. There are four connections of the electronic unit : an input contact 6 for the supply current and an output contact 6 for the supply current both indicated as reference numeral 6 in Fig. 4 but with a following positive and negative sign, respectively. Further, there are two contacts for the differential input of the data path 10 with a positive and negative sign, respectively. The unit shown in Fig. 4 can be one of the electronic units 3 of Fig. 3. When neglecting the data path, the dynamic impedance of the bipolar unit is practically zero in the range of the operational current (e.g. in comparison with the resistance of the conductive paths formed in the conductive layer on the substrate, e.g. glass substrate). A large range of electric current is admissible through the electronic unit independent of its functionality. This means that the electric current flowing through an electronic unit equals i_lin and i_lout. Each electronic unit is individually addressable, independently of the operational state or functional state of the other electronic units being connected in series in the chain of the plurality of electronic units.

It must be noted that each electronic unit 3 preferably remains insensitive to the electric current flowing through it, as the latter may be substantially larger than the current needed for the electronic unit in its actual operational state. According to other preferred embodiments of the invention, also other physical parameters different from the electric current are used. Furthermore, the functioning of the electronic unit preferably has electrically no influence on the rest of the electronic units in the electronic array.

Assuming that the electric current flowing through the chain of electronic units is always at least slightly larger than the electric current needed by each electronic unit in the worst-case scenario, in which its functionality needs the largest current, at least a variable part of the electric current will have to be diverted or dissipated rather than flow directly through the electronic unit and provide the functionality thereof.

On the other hand, the changing needs in electric current for the functioning of the electronic unit preferably does not allow a variation of the voltage drop at its contacts. This can be achieved, for example, by means of an ideal Zener diode. However, a conventional Zener diode needs an operational voltage which is important in order to present a small dynamic resistance. Furthermore, this dynamic resistance remains negligible at the optimal operational point. Hence, what has to be achieved is a functionality equivalent to a smaller operational electric current, a smaller dynamic resistance and an impor- tant possibility of thermal dissipation.

One aspect of the present invention is shown in Fig. 4 representing an embodiment of the invention. The principle involves using an integrated circuit ICl which allows regulation of a voltage of a Zener diode and which can be regulated in a more precise way. In order to amplify the operational state an amplifier in the form of an external transistor Ql is added. The regulated operational voltage used by the operational part of the electronic unit is defined by the ratio of the resistances (R3 + R4)/R4 multiplied by the internal reference voltage of ICl that corresponds to one or a few Volts. ICl needs an electric current of a few milliamperes or less in order to function properly. If the electric voltage at the feedback input contacts is larger than the reference voltage, the impedance of the electronic unit decreases and, therefore, forces a larger current to flow through it. Usually, a part of the electric current flows through the load thereby causing a voltage drop at the contacts of the bipolar unit.

When a small resistance R2 is arranged in series with ICl and a transistor Ql is arranged in parallel, the electric voltage at the contacts of this resistance should come in the range of 0.7 V. Furthermore, if the small signal forward current gain hFE of the transistor Ql is large, it represents in a first approximation the constant operational current of ICl. In this case, the current diversion capability of ICl is transferred to the pair Ql and Rl. Indeed, when ICl tries to reduce operational voltage it also reduces its impedance and thus causes a need for i₂₂ which is larger and thus causes an increase in the base voltage of Ql which starts driving the electric current towards Rl. With a large gain of the transistor, the electric voltage and the electric current i₂₂ at the contacts of ICl are almost constant, independent of the deviated current i₂₁. i₂₃ is constant as well because the voltage at the contacts of the pair of the resistances R3 and R4 is also con- stant. Since i_lin equals the sum of i₂ and i₃ and further assuming that i_lin > i₃, i₂, i₃ this current represents the electric current used for providing the principle function of the electronic unit. This electric current is variable and depends on the function and application of the electronic unit. Hence, it is important to determine the best mode of setting such electric currents fixed at certain predefined values. The electric currents i₃ and i₂ should automatically complement the electric current so that the general current ii remains constant.

If the impedance of the principle functional block 11 is positive, which is almost always the case even if it varies largely during use, a surplus of a physical parameter (according to the second embodiment of the invention this is the electric current) in the block 11 is bound to go along with an increase of the electric voltage at its contacts. Hence, there is a combination of two parts: The regulating part will consume the electric current i₂ needed to maintain the electric voltage at the contacts of the functional block 11 at a constant level, independent of the electric current i₃ which flows through the electronic unit.

It is worth noting that i₃ can be decomposed in i₃₁ which is approximately constant and which is consumed by the control unit 7 or control electronics, respectively, and i₃₂ which is the electric current consumed by the load unit 9 (for instance one single color LED or a RGB LED) of the electronic unit. i₃₂ can be excessively variable. On the other hand, i₂ can be decomposed in i₂₁ which is the variable deviated current, further in i₂₂ which is quasi constant and small and which supplies ICl, and finally in i₂₃ which is constant in a resistive dividing bridge. The current i₃₂ also flows through the driver unit 8 which is connected in parallel to the load unit 9.

Consequently, when neglecting all these almost constant currents, i₃₂ is integrally com- pensated by i₂₁. In other words, the sum of the currents 1₃₂ and i₂₁ is always constant. Furthermore, Cl is used for stabilizing the entire regulation process. It is noted that the use of the resistance Rl shows two effects: Firstly, it is used for dissipating the power which is not used by the functional block 11. Indeed, as the electronic unit functions at a constant voltage, the principle applied for the electric currents can be extended to powers as well. In order not to overload Ql, an external resistance of appropriate power distributes the dissipated power. Secondly, it also allows by measuring the voltage at its contacts, to measure the quantity of deviated current which allows the control unit 7 to manage the available extra current. Indeed, in order for the entire device to function properly, i₂₁ must always be larger than zero. The value of the resistance Rl must then be selected in an adequate way so that the voltage at its contacts is sufficient for causing a voltage drop which can be used. However, it is not likely that the transistor Ql is brought to saturation.

Once the operational voltages are stabilized at the contacts of the electronic units and the general electric current of the electronic array is fixed and also constant, independent from the use of the electronic units, the absolute operational voltages at the contacts of the electronic units will also be constant. The absolute operational voltages will be predictable and linearly increasing in a dimension of the electronic array.

Alternatively, the data path can be implemented as described in context with the first embodiment of the invention. According to the first embodiment, the common mode voltage at the places directly adjacent to the electronic units will be rather close to the voltage present at the electronic units. The difference in potential of common mode should also be quasi constant between the connection point of the electronic unit on the data path and the electronic unit itself. Hence, it becomes possible to make the data transit at this place by means of the majority of conventional methods. A simple differential connection may thus be converted into a conventional digital signal by a receiver which is sufficiently tolerant to the differences in the potential of common mode. The signal may then be sent to a control unit which is comprised by the electronic unit, for instance to a microcontroller through a suitable interface such as a Universal Asynchro- nous Receiver/Transmitter (UART) input.

Finally, it is worth noting that as each electronic unit shows a unique address information, each electronic unit can be addressed in an individual way through an appropriate protocol, whereby each electronic unit receives all the data but filters the data directed to the respective electronic unit.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

A single unit may fulfil the functions of several items recited in the claims. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. An electronic array comprising: a power supply unit (6), a plurality of electronic units being arranged in series to one another, wherein each electronic unit of the plurality of electronic units comprises a management unit adapted for addressing the electronic unit of the plurality of electronic units individually and wherein each management unit further comprises a dissipation unit adapted for dissipating a surplus of a physical parameter associated with the electronic unit.

2. The electronic array according to claim 1, wherein the management unit comprises a decoding unit adapted for decoding a command being addressed to the management unit.

3. The electronic array according to claim 2, wherein the management unit further comprises a driving unit (8) adapted for selecting a portion of the physical parameter associated with the electronic unit.

4. The electronic array according to claim 3, wherein the physical parameter com- prises at least one of electric current through the electronic unit, electric voltage across the electronic unit, temperature of the electronic unit and impedance of the electronic unit.

5. The electronic array according to any previous claim, wherein each electronic unit of the plurality of electronic units comprises an electronic component and the management unit and wherein the dissipation unit comprises a variable load arranged in parallel with the electronic component.

6. The electronic array according to claim 5, wherein the variable load is a variable re- sistive element.

7. The electronic array according to any of the preceding claims, wherein the plurality of electronic units is arranged on a conductive resistive substrate.

8. The electronic array according to claim 7, wherein the conductive resistive sub- strate corresponds to glass comprising a conductive layer adapted for conducting electricity.

9. The electronic array according to any of the preceding claims, wherein the plurality of electronic units comprises a plurality of organic light emitting diodes and/or a plurality of light emitting diodes.

10. The electronic array according to any of the claims 7 to 9, wherein the conductive resistive substrate is a first glass panel and is laminated to a second glass panel with the electronic array laminated between the first and second glass panel.

11. The electronic array according to claim 10, wherein the first and second glass panel are laminated together with a plastic sheet laminated therebetween.

12. The electronic array according to any of the claims 7 to 10 wherein the conductive resistive substrate is a first glass panel and is associated to a second glass panel with the electronic array being provided on the first glass panel and in an air gap between the first and second glass panel.

13. A method for use with an electronic array comprising a power supply unit (6), and a plurality of electronic units being arranged in series to one another, the method compris- ing: addressing an electronic unit of the plurality of electronic units individually and dissipating a surplus of a physical parameter the electronic unit locally to the electronic unit.

14. The method according to claim 13, further comprising the step of decoding a command being addressed to the electronic unit.

15. The method according to claim 13 or 14, wherein the physical parameter comprises at least one of electric current through the electronic unit, electric voltage across the electronic unit, temperature of the electronic unit and impedance of the electronic unit.

16. The method according to any of claims 13 to 15, wherein the step of dissipating a surplus of the physical parameter the electronic unit locally to the electronic unit is a lossy dissipation.

17. The method according to any of the preceding claims, wherein the plurality of electronic units are formed on a conductive resistive substrate.

18. The method according to claim 17, wherein the conductive resistive substrate is formed by applying a conductive layer adapted for conducting electricity to a glass panel.

19. The method according to any of the claims 17 to 19, further comprising the step of laminating a first glass panel to a second glass panel with the electronic array laminated between the first and second glass panel.

20. The method according to claim 19, further comprising the step of laminating the first and second glass panel together with a plastic sheet laminated therebetween.

21. The method according to any of the claims 17 to 19 wherein the step of forming the conductive resistive substrate includes providing the electronic array on the first glass panel associated to a second glass panel with in an air gap between the first and second glass panel.