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EP2195830A2 - Method and apparatus for forming arbitrary structures for integrated circuit devices - Google Patents

Method and apparatus for forming arbitrary structures for integrated circuit devices

Info

Publication number
EP2195830A2
EP2195830A2 EP08807647A EP08807647A EP2195830A2 EP 2195830 A2 EP2195830 A2 EP 2195830A2 EP 08807647 A EP08807647 A EP 08807647A EP 08807647 A EP08807647 A EP 08807647A EP 2195830 A2 EP2195830 A2 EP 2195830A2
Authority
EP
European Patent Office
Prior art keywords
electrical
mechanical structure
providing
mechanical
design file
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08807647A
Other languages
German (de)
French (fr)
Inventor
Christopher Wyland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of EP2195830A2 publication Critical patent/EP2195830A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P80/00—Climate change mitigation technologies for sector-wide applications
    • Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities

Definitions

  • the invention relates to integrated circuits and more particularly to forming arbitrary structures for interfacing and packaging integrated circuits.
  • Intel's arrayed microprocessor containing 80 microprocessors each capable of independent processing as well as shared processing.
  • the step comprises a group of operations including die attachment or die placement, IC bonding such as by wire bonding, flip-chip solder bump, TAB etc, encapsulation, marking, lead trimming, and lead forming. Accordingly to the requirements of the packaging style a complete sequence of these steps or a predetermined subset are performed for each and every discrete IC. As a result packaging accounts typically for approxiamately 80% to 90% of the costs for an IC.
  • MCP multi-chip packages
  • S-CSP stacked chip- scale packages
  • a method of packaging comprising providing a design file relating to a mechanical structure for interfacing to at least an electrical device, the design file comprising at least two of electrical input and output coordinates of the mechanical structure, electrical path information for paths interconnecting the electrical input and outputs, mechanical attributes of the semiconductor die, mechanical attributes of the mechanical structure, and a list of materials.
  • the method further comprising executing the design file with a three dimensional manufacturing system; the three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of any material from the list of materials with a thickness less than the thickness of any element within the mechanical structure.
  • a method of packaging comprising providing a design file relating to a mechanical structure for interfacing to at least an electrical device and comprising at least two of electrical input and output coordinates of the mechanical structure, electrical path information for paths interconnecting the electrical input and outputs, mechanical attributes of the semiconductor die, mechanical attributes of the mechanical structure, and a list of materials, the design file relating to controlling a three dimensional manufacturing system capable of generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations involving the addition of any material from the list of materials with a thickness less than the thickness of any element within the mechanical structure.
  • a method of packaging comprising providing at least an electrical device of a plurality of electrical devices and providing a mechanical structure, the mechanical structure for interfacing to at least a predetermined portion of at least one electrical device of the plurality of electrical devices, the mechanical structure manufactured with a three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of material with a thickness less than the smallest thickness of any element within the mechanical structure.
  • the method further comprising interconnecting the mechanical structure to the at least one electrical device of the plurality of electrical devices.
  • a method of packaging comprising providing at least an electrical device of a plurality of electrical devices, and generating a mechanical structure in association with the at least an electrical device of the plurality of electrical devices, the mechanical structure for interfacing to at least a predetermined portion of at least one electrical device of the plurality of electrical devices, the mechanical structure manufactured with a three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of material with a thickness less than the smallest thickness of any element within the mechanical structure.
  • Fig. 1 illustrates the evolution of industry standard IC packaging over the past 30 years.
  • Fig. 2 illustrates a prior art pin configuration for a 2116 pin package from Renesas Technology.
  • Fig. 3A illustrates a prior art approach to electrical interconnection from die to package with a cross- sectional view of a Low Temperature Co-Fired Ceramic substrate.
  • Fig. 3B illustrates the process flow for manufacturing the Low Temperature Co- Fired Ceramic substrate of Fig. 3A.
  • Fig. 4 illustrates a prior art approach to electrical interconnection for a stacked IC structure in a Stacked Chip Scale Package (S-CSP).
  • S-CSP Stacked Chip Scale Package
  • Fig. 5 illustrates a prior art approach for three-dimensional electrical interconnections according to Kunishi.
  • Fig. 6A illustrates an exemplary embodiment of the invention providing interspersed electrical interconnections between two elements.
  • Fig. 6B illustrates the electrical interconnection provided by the exemplary structure according to Fig. 6 A.
  • Fig. 7 illustrates a cross-section of an exemplary embodiment of the invention providing arbitrary electrical interconnections.
  • Fig. 8 illustrates a cross-section of an exemplary embodiment of the invention providing arbitrary packaging incorporating electrical interconnections, mechanical structures and thermal management.
  • Fig. 9A illustrates a plan cross-section of an exemplary embodiment of the invention providing thermal management and electrical interconnection for an IC.
  • Fig. 9B illustrates a first cross-section Y-Y of the exemplary embodiment of Fig. 9A.
  • Fig. 9C illustrates a first cross-section Y-Y of the exemplary embodiment of Fig. 9A.
  • Fig. 10 illustrates an exemplary embodiment of the invention providing an arbitrary package with electrical interconnections on multiple sides of the arbitrary package.
  • each "industry standard” is plotted according its balance of meeting needs for increased input / output counts and high performance, represented by proximity to X-axis 110, and meeting the needs to reduced cost and reduced footprint, represented by proximity to Y-axis 120.
  • FPGA Fine Pitch Ball Grid Array
  • LLCC Leadless Chip Carrier
  • QFN Quad Flat No Lead
  • MCP Multi- Chip Package
  • SIP System In Package
  • CSP Chip Scale Package
  • S-CSP Stacked Chip Scale Package
  • WLP Wafer Level Package
  • FIG. 2 An example of the scale of packaging provided by FPGA 163 today in the 2000s 160 from it's evolution in the 1980s 140 from the PGA 141 is shown by the pin configuration 200 in Fig. 2 for a 2116 contact FPGA 163 offered by Renesas Technology Corporation of Japan.
  • Such pin configuration 200 being defined by row 210, wherein the rows 210 are separated by an industry standard pitch d y 240, and column 220, wherein the columns 220 are separated similarly by an industry standard pitch d x 230.
  • d x 230 and d y 240 are 1.00mm. As such providing 2116 pins requires
  • multi-layer structure 350 of Fig. 3A An exemplary cross-section of a prior art substrate forming the mounting base of an FPGA 163 is shown by multi-layer structure 350 of Fig. 3A.
  • LTCCs low temperature co-fired ceramics
  • the multi-layer structure 350 comprises 6 LTCC layers 321 through 325 respectively, each of which has been patterned to a varying degree with metallization, see for example upper surface metallizations 331 and 332 on LTCC layers 321 and 322 respectively, plated metallization 333 on the upper surface of LTCC layer 326 and bottom surface metallization 334 on the lower surface of LTCC layer 326.
  • These metallization patterns are determined in respect of the circuit design wherein the multilayer structure 350 has been designed to meet specific circuits assembled to it or alternatively are determined in respect of a standard package geometry, grid array locations and internal bonding pads, all of which are not shown for clarity.
  • passive electrical structures may be patterned including capacitor 363, three dimensional resistor 362, buried resistor 361 and electrical vias 370 through one or more of the LTCC layers 321 through 326. Additional features may include cavities such as cavity 385 for housing a photodetector coupled to an optical fiber 390 that has been inserted into a cavity in LTCC layer 323, and thermal vias 380. Electrical interconnection to the multi-layer structure 350 may include solder reflow for surface mount resistor 341, solder bumping for flip-chip die 351, wire bonding 352 for epoxy attached die 353 and solder reflow for flip-chip carrier 354. In addition mounting components may be undertaken on both sides of the multi-layer structure, such as exemplified by lower solder-bump die 355 but this is uncommon in respect to packaging structures, and more common with LTCC circuit boards and carrier structures.
  • the first step 301 comprises blanking wherein the plurality of LTCC layers 311 is formed by cutting a sheet of "green tape", not shown for clarity.
  • green tape the term “green” refers to the unfired nature of the film which is comprised approximately 85-90% inorganic materials and approximately 10-15% organic materials.
  • tape refers to the continuous sheets of material manufactured from Typically the inorganic materials are silicon dioxide, aluminum oxide, aluminum nitride but can include borosilicate etc according to the requirements of the LTCC.
  • step 302 the electrical and thermal vias within each sheet are formed, for example LTCC sheets 312 through 315. These electrical vias are then plated to fill them in step 303.
  • Each of the LTCC sheets 312 through 315 having the pattern of electrical and thermal vias required to provide the necessary routing between each electrical layer that will be defined between each adjacent pair within the final multi-layer structure 350.
  • each LTCC sheet 312 through 315 is printed with the appropriate electrical structures.
  • these LTCC sheets 312 through 315 are orientated and stacked to form unfired stack 316.
  • the unfired stack 315 is laminated and the LTCC sheets 312 through 315 co-fired at temperatures typically approaching 900 0 C thereby driving off the organics within the "green tape” and fusing them together to form co-fired stack 317.
  • additional printing is performed, for example to provide thick film or thin film passive electrical structures such as resistors onto the outer surfaces of the co-fired stack 317 to yield finished stack 318. All that remains in step 309 is to electrically test the finished stack 318 and cut to the final dimensions thereby providing LTCC substrate 319. This cutting is generally the separation of a number of simultaneously fabricated LTCC substrates 319 from a single sheet.
  • Each LTCC sheet 312 through 315 is typically one of a range of standard thicknesses, such as offered by DuPont® with their Green TapeTM, of 51 ⁇ m, 114 ⁇ m, 165 ⁇ m and 254 ⁇ m. It would be evident therefore that any electrical traces implemented are thereby formed by a series of electrical traces on each layer with vertical vias interconnecting them through each layer of "green tape". As such all electrical routing and structures must comply with this vertical quantization of "vias" and horizontal traces.
  • the general form of LTCC substrates 319 providing multi-layer structure 350 is therefore one providing a single series of bond pads or bumps.
  • S-CSP Stacked Chip Scale Package
  • an exemplary chip stack 400 is shown in Fig. 4.
  • an LTCC substrate 470 has assembled a first semiconductor die 410, a first dielectric spacer 420, a second semiconductor die 430, second dielectric spacer 440, third semiconductor die 450 and fourth semiconductor die 460.
  • first wire bonds 492 interconnect to the first semiconductor die 410
  • second wire bonds 494 interconnect to the second semiconductor die 430
  • third wire bonds 496 interconnect to the third semiconductor die 450.
  • power bond pads 482 are interconnected to the fourth semiconductor die 460 as well as ground pads 484.
  • stitching wire bonds 498 which route from fourth semiconductor die 460 to a fifth semiconductor die, not shown for clarity, also mounted onto the third semiconductor die 450.
  • the approach is not particularly suited to provided three dimensional interconnects, and the three dimensional electrical routing within a structure is also limited.
  • Alternative prior art solutions such as that exemplified by three- dimensional interconnect structure 500 of Fig. 5 and the corresponding electrical interconnect 550.
  • the electrical interconnect 550 being taught by Kunishi as formed by stamping.
  • the three dimensional interconnect structure 500 comprises a body 510, latches 506, and the electrical interconnect 550 assembled together.
  • the body 510 has holes 504 with sidewalls 504a and 504b that allow the electrical interconnect 550 and latches to be positioned appropriately for interconnecting to the other elements of the device of which the three dimensional interconnect structure 500 is part.
  • the latches 506 protrude through holes 504 as do interconnect tabs 502b and 502c.
  • electrical interconnect 550 the plurality of electrical leads 502 can be clearly seen, each originating with an edge connector contact 502a and terminating at the other end in either a large interconnect tab 502b or small interconnect tab 502c. It would be apparent that whilst this allows for three dimensional interconnections, and suits a variety of systems such as automotive the approach is expensive and not compatible with the requirements of structures such as the Stacked Chip Scale Package (S-CSP) 165 in the exemplary chip stack 400 of Fig. 4.
  • S-CSP Stacked Chip Scale Package
  • Fig.6A shown is an exemplary embodiment of the invention for providing an arbitrary interconnection structure 600 between a first device 610 and second device 620.
  • the electrical interconnection implemented within the arbitrary interconnection structure 600 being shown by connection map 690 in Fig. 6B.
  • first pads 615, represented by A through F, of first device 610 are connected to the second pads 625, represented by 1 through 6, of second device 620 according to pairing (A-6), (B-5). (C-2), (D-4), (E-I), and (F-3).
  • Disposed between the first device 610 and a second device 620 is an arbitrary interconnect 630 comprising a plurality of electrical conductors 640 through 665 disposed within.
  • First electrical conductor 640 provides the routing (A-6), second electrical conductor 645 providing (B-5), third electrical conductor 650 implementing the connection (C-2), fourth electrical conductor providing (D-4), fifth electrical conductor providing (E-I), and the sixth electrical conductor providing the connection (F-3).
  • An side view of the arbitrary interconnection structure 600 is shown in Fig. 6C where the electrical conductors 640 through 665 are shown having arbitrary shapes in that each of the electrical conductors 640 through 665 are implemented in their vertical and horizontal transitions to provide the required electrical interconnection with smooth curves.
  • the LTCC substrate 319 providing multi-layer structure 350 only horizontal transitions could be implemented as continuous curves.
  • the provision of continuous curvilinear electrical conductors has benefits for routing high speed signals within an electrical interconnection between devices or packaging. As such routing may be implemented with the intentions of minimizing abrupt transitions rather than the typical intention of minimizing the number of layers within the structure.
  • the arbitrary interconnect 630 may be implemented using additive manufacturing technologies such as stereolithography and three-dimensional printing.
  • FIG. 7 a cross- sectional view of an arbitrary structure 700 is shown provided by another exemplary embodiment of the invention.
  • a semiconductor die 720 is mounted onto a carrier 710 between which a series of electrical interconnections are required. Accordingly the electrical interconnections are implemented with an arbitrary interconnect 730.
  • Shown on the upper surface of the semiconductor die 720 are first and second electrical pads 776 and 778 respectively, whilst on the upper surface of the carrier 710 are first and second electrical traces 772 and 774 respectively.
  • First electrical trace 772 is electrically connected to first arbitrary interconnect 781 which comprises a vertical transition followed by a transition out of the plane of the cross- section, the first arbitrary interconnect 781 routing towards the viewer as indicated by the conductor ⁇ 742.
  • Second electrical trace 774 is electrically interconnected to second arbitrary interconnect 782, being a vertical transition, and then interconnects to second electrical pad 778 via shaped interconnection 786 and third arbitrary interconnect 785.
  • shaped interconnection 786 provides not only a sloped vertical transition but also a graded reduction in thickness of metallization as the shaped interconnection 786 increases its separation from the semiconductor die 720 and carrier 710.
  • the shaped interconnection 786 is further implemented as a meta-material structure wherein isolated metallization structure 765 and embedded ground electrode 760 are designed to make the signal within the shaped interconnection 786 act in such a way as to make the shape of the signal behave as though the permittivity and permeability are different than the real component permittivity and permeability of the insulator used in providing the body of the arbitrary interconnect 730.
  • embedded ground electrode 760 must be interconnected to a ground potential each end of it comprises a left conductor ⁇ 744 and right conductor ⁇ 746 which route to a ground potential connection, not shown for clarity.
  • First electrical pad 776 is depicted with two electrical interconnections 783 and 784 respectively.
  • First electrical interconnection 783 transitioning to a conductor ® routing away from the viewer
  • second electrical interconnection 784 transitioning to a conductor ⁇ 748 towards the viewer.
  • a coaxial connection 750 embedded within the upper left corner of the arbitrary interconnect 730 is a coaxial connection 750.
  • the coaxial connection 750 comprising central signal line 750C, outer ground ring 750B and dielectric 750A.
  • the dielectric 750A is optionally different to the dielectric forming the body of the arbitrary interconnect 730.
  • Fig. 8 shown is a composite arbitrary structure 800 wherein the upper arbitrary structure 830 is combined with a lower arbitrary structure 810 in providing packaging and electrical interconnection to the semiconductor die 820.
  • the semiconductor die 820 of Fig. 8 is backside metallised with layer 825 to improve thermal conductance and provide grounding of the semiconductor die 820. This grounding being provided by the lower conductor 880 within the lower arbitrary structure 810, which is connected to first pad 812 and thereupon to first upper conductor 832 within the upper arbitrary structure 830 wherein it is routed away towards the viewer as indicated by ⁇ .
  • databus array 870 comprising conductors 874 within a dielectric 872 that has properties different to that of lower arbitrary structure 810.
  • a thermal liquid cooling element 880 is formed also within the lower arbitrary structure 810 of a further different material to that of the lower arbitrary structure 810 and dielectric 872, and comprising a series of liquid conduits 885 within which a liquid coolant may be pumped, with reservoir, heat exchange, pump etc not shown for clarity.
  • a second pad 814 on the upper surface of the lower arbitrary structure 810 is electrically connected to an upper electrical conductor formed by elements 852, 854, and 856 respectively in routing to second die pad 824.
  • First and third elements 852 and 854 transitioning away from the viewer with varying thickness and separation from the semiconductor die 820 with second element 854 linking them. Said transition away from the viewer required to implement the upper electrical conductor routing around the coaxial structure 865 that couples perpendicularly away from first die pad 822.
  • the coaxial structure 865 being comparable to coaxial connection 750 of Fig. 7. However, as shown the coaxial structure ends with a cavity 860 within the upper arbitrary structure 830.
  • the cavity 860 being dimensioned to allow the insertion of a coaxial connector, not shown for clarity.
  • Third die pad 826 couples directly through the body of the upper arbitrary structure 830 via power bar 864 that terminates in contact 862.
  • a coplanar waveguide structure 840 is shown embedded within the upper arbitrary structure 830.
  • lower arbitrary structure 810 comprises multiple materials deposited simultaneously as the three dimension structure is manufactured, and further includes embedded cavity structures of non-rectangular cross-section.
  • upper arbitrary structure 830 contains mechanical fixturing, c.f. cavity 860, as well as electrical structures.
  • the upper and lower arbitrary structures 810 and 830 respectively can be manufactured as a single piece part such that the semiconductor die 820 is inserted into a cavity. Referring to Fig.
  • FIG. 9 A an alternate approach to the thermal management of a semiconductor die 910 is presented with plan cross-section of package 900.
  • the semiconductor die 910 has been metallised on all four sidewalls, this metallization being shown as top metal 910A, left metal 910B, right metal 910C, and lower metal 910D.
  • thermal slugs 950 In contact with each of the four metallised walls 910A through 910D are thermal slugs 950, six interfacing on each of the upper and lower metals 910A and 91DC respectively, and two interfacing on each of the left and right metals 910B and 910C respectively.
  • thermal slugs 950 Disposed around the periphery of the package 900, on each sidewall are heat sinks 920A through 920D in thermal contact with the thermal slugs 950. Disposed between thermal slugs 950 are arrayed electrical traces 930 together with secondary trace arrays 940 disposed in two corners of the package 900.
  • the package 900 comprises multiple materials which are deposited simultaneously during manufacture, being the main dielectric of the package 900, metallization for electrical traces 930, which are typically copper, gold or aluminum, metal for thermal slugs, which may be molybdenum, copper, or copper-tungsten for example, and metal heat sinks, typically aluminum. Additionally deposited during the single manufacturing steps of three dimensional printing for example to form the package 900 would be for example tin- silver-copper, SnAgCu, to provide lead free soldering.
  • the thermal slugs may optionally be beryllia, beryllium oxide.
  • exemplary distributed interconnect package 1000 is shown in Fig. 10.
  • the distributed interconnect package 1000 comprising 26 surfaces, and having a structure similar to gem cuts in being a rectangular structure with bevel on each corner.
  • an upper surface 1010 comprises a first array of electrical interconnects 1015, a side wall 1030 provides a second array of electrical interconnects 1035, and the bevel surface 1020 between upper surface 1010 and sidewall 1030 provides a third array of electrical interconnects 1035.
  • End wall 1040 has first DC interconnect 1045, such as ground, as well as corner bevel 1050 which provides a second DC interconnect 1055.
  • the distributed interconnect package 1000 may be provided with pins or sockets respectively for each of the represented electrical interconnections 1015, 1025, 1035, 1045 and 1055. These pins and sockets thereby forming mating halves of electrical connectors.
  • the three dimensional printing of the distributed interconnect package 1000 may include mechanical features such as mounting holes, threaded inserts, etc allowing the distributed interconnect package 1000 to be physically interconnected to other distributed interconnect packages 1000, standard connectors, or circuit boards, device panels, etc. Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention.

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Abstract

A method of implementing arbitrary structures to provide electrical interconnection and mechanical fixturing for integrated circuits is provided. According to exemplary embodiments of the invention said arbitrary structures are manufactured using three dimensional manufacturing processes employing only additive steps for all materials within the arbitrary structure. Accordingly the arbitrary structure is provided in a single step incorporating mechanical, electrical, and thermal elements as required by the design incorporating simultaneously dielectric and metallic materials. The arbitrary structures may be manufactured directly in association with the integrated circuits or separately for subsequent assembly to the integrated circuits. Arbitrary structures ranging from a fraction of to all of the structural and electrical elements required for packaging the integrated circuit(s) being provided by the arbitrary structures according to the design boundary established.

Description

METHOD AND APPARATUS FOR FORMING ARBITRARY STRUCTURES FOR INTEGRATED CIRCUIT DEVICES
The invention relates to integrated circuits and more particularly to forming arbitrary structures for interfacing and packaging integrated circuits.
Only a half century after their development was begun, integrated circuits (ICs) have become ubiquitous. Computers, cellular phones, and other digital appliances are now inextricable parts of the structure of modern societies. That is, modern computing, communications, manufacturing and transport systems, including the Internet, all depend on the existence of ICs. The global consumption of ICs continues to grow apace as the complexity of the integrated circuits, the consumerization of electronic devices, and the functionality of consumer electronics continue to increase. Since the end of 2001, annual IC shipments have grown by more than 100 percent from 68.5 billion in 2001 to 137.4 billion in 2006. Accordingly over the period 2004 through 2006 worldwide monthly revenues from the sale of ICs have averaged $17 billion.
Today such ICs exploit a range of semiconductor materials, including silicon, gallium arsenide, indium phosphide, and silicon germanium in ICs operating from DC through to 40GHz and above, from discrete transistors to microprocessors containing approximately 55 million transistors (c.f. Intel® Pentium 4), and from die of a square millimeter to wafer scale integration prototypes such as Intel's arrayed microprocessor containing 80 microprocessors each capable of independent processing as well as shared processing. Towards the final stages of semiconductor device manufacturing of this diverse range of ICs, where ICs are processed and handled at the wafer level, is integrated circuit packaging.
Simply called "packaging" within the IC industry the step comprises a group of operations including die attachment or die placement, IC bonding such as by wire bonding, flip-chip solder bump, TAB etc, encapsulation, marking, lead trimming, and lead forming. Accordingly to the requirements of the packaging style a complete sequence of these steps or a predetermined subset are performed for each and every discrete IC. As a result packaging accounts typically for approxiamately 80% to 90% of the costs for an IC. The impact of packaging therefore is substantial in discrete ICs and is increasing with recent trends to multi-chip packages (MCP) and stacked chip- scale packages (S-CSP) wherein multiple ICs are co-packaged together as spaced die in a single layer or stacked vertically one above another. Such packaging formats as MCP and S-CSP becoming more prevalent as the demands for reductions in cost, footprint, and package profile continue alongside concurrent increases in functionality and performance, not only in speed but also power efficiency.
Over approximately the past thirty years nearly 20 different packaging formats have reached the status of "industry standard", each supporting a particular tradeoff in the above balance of improvements and each being offered in high numbers of variants in terms of dimensions, pin count etc. In many of these the electrical interconnections are of one specific format, such as wire bond in dual-in-line package (DIP), which may limit performance of ICs. As such it would be apparent therefore that it would be beneficial to provide a method of providing electrical interconnections within any of the different packaging formats wherein the electrical interconnection is tailored to the requirements of the IC. Further, it would be beneficial if the electrical interconnection allowed arbitrary formats to be provided such that the electrical interconnection was tailored to the specific requirements of the IC and not be limited to that usually employed within that "industry standard" package.
It would be further beneficial if the individual steps required within the "single" packaging step for an IC were reduced. It would be beneficial to combine electrical interconnection and encapsulation into a single step or the provisioning of electrical interconnections and thermal management as a single step. In essence it would be beneficial to provide a method of arbitrarily providing electrical interconnections, thermal interconnections, packaging, etc in a manner that enhances the cost-performance tradeoff rather than selecting a "best of the worst cases" from the "industry standards". Benefically such integrations of multiple aspects of the IC package thereby reducing complexity of operations, enhancing reproducibility, enhancing performance and reducing costs. It would be further beneficial if the manufacturing operations of the arbitrary packaging structure were achieved using a manufacturing process that was additive rather than subtractive, such that consumption of raw materials was minimised, waste reduced, environmental impacts lowered, electrical power consumption to produce the parts lowered, and costs reduced by using only the required amounts of raw materials necessary to form the piece part were consumed.
In accordance with the invention there is provided a method of packaging comprising providing a design file relating to a mechanical structure for interfacing to at least an electrical device, the design file comprising at least two of electrical input and output coordinates of the mechanical structure, electrical path information for paths interconnecting the electrical input and outputs, mechanical attributes of the semiconductor die, mechanical attributes of the mechanical structure, and a list of materials. The method further comprising executing the design file with a three dimensional manufacturing system; the three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of any material from the list of materials with a thickness less than the thickness of any element within the mechanical structure.
In accordance with another embodiment of the invention there is provided a method of packaging comprising providing a design file relating to a mechanical structure for interfacing to at least an electrical device and comprising at least two of electrical input and output coordinates of the mechanical structure, electrical path information for paths interconnecting the electrical input and outputs, mechanical attributes of the semiconductor die, mechanical attributes of the mechanical structure, and a list of materials, the design file relating to controlling a three dimensional manufacturing system capable of generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations involving the addition of any material from the list of materials with a thickness less than the thickness of any element within the mechanical structure. In accordance with another embodiment of the invention there is provided a method of packaging comprising providing at least an electrical device of a plurality of electrical devices and providing a mechanical structure, the mechanical structure for interfacing to at least a predetermined portion of at least one electrical device of the plurality of electrical devices, the mechanical structure manufactured with a three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of material with a thickness less than the smallest thickness of any element within the mechanical structure. The method further comprising interconnecting the mechanical structure to the at least one electrical device of the plurality of electrical devices. In accordance with another embodiment of the invention there is provided a method of packaging comprising providing at least an electrical device of a plurality of electrical devices, and generating a mechanical structure in association with the at least an electrical device of the plurality of electrical devices, the mechanical structure for interfacing to at least a predetermined portion of at least one electrical device of the plurality of electrical devices, the mechanical structure manufactured with a three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of material with a thickness less than the smallest thickness of any element within the mechanical structure. Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which:
Fig. 1 illustrates the evolution of industry standard IC packaging over the past 30 years.
Fig. 2 illustrates a prior art pin configuration for a 2116 pin package from Renesas Technology.
Fig. 3A illustrates a prior art approach to electrical interconnection from die to package with a cross- sectional view of a Low Temperature Co-Fired Ceramic substrate. Fig. 3B illustrates the process flow for manufacturing the Low Temperature Co- Fired Ceramic substrate of Fig. 3A. Fig. 4 illustrates a prior art approach to electrical interconnection for a stacked IC structure in a Stacked Chip Scale Package (S-CSP).
Fig. 5 illustrates a prior art approach for three-dimensional electrical interconnections according to Kunishi.
Fig. 6A illustrates an exemplary embodiment of the invention providing interspersed electrical interconnections between two elements. Fig. 6B illustrates the electrical interconnection provided by the exemplary structure according to Fig. 6 A.
Fig. 7 illustrates a cross-section of an exemplary embodiment of the invention providing arbitrary electrical interconnections.
Fig. 8 illustrates a cross-section of an exemplary embodiment of the invention providing arbitrary packaging incorporating electrical interconnections, mechanical structures and thermal management.
Fig. 9A illustrates a plan cross-section of an exemplary embodiment of the invention providing thermal management and electrical interconnection for an IC.
Fig. 9B illustrates a first cross-section Y-Y of the exemplary embodiment of Fig. 9A.
Fig. 9C illustrates a first cross-section Y-Y of the exemplary embodiment of Fig. 9A.
Fig. 10 illustrates an exemplary embodiment of the invention providing an arbitrary package with electrical interconnections on multiple sides of the arbitrary package.
Over approximately the past thirty years nearly 20 different packaging formats have reached the status of "industry standard" as shown in FIG. 1 by the packaging goal graph 100. Shown within the packaging goal graph 100 are "industry standard" packaging solutions for the decades 1970s 130, 1980s 140, 1990s 150, and 2000s 160 respectively. Within each decade 130 through 160 respectively each "industry standard" is plotted according its balance of meeting needs for increased input / output counts and high performance, represented by proximity to X-axis 110, and meeting the needs to reduced cost and reduced footprint, represented by proximity to Y-axis 120.
As such in the decade 1970s 130 the single "industry standard" Dual-In-Line Package DIP 131 is shown. By the 1980s 140 packaging has evolved to provide "industry standards" of Pin Grid Array (PGA) 141, Quad Flat Pack (QFP) 142, Leaded Chip Carrier (LCC) 143, and Small Outline Package (SOP) 144. These respectively moving away from pin count / performance to lower cost and footprint. In the 1990s 150 these "industry standards" evolve as technology improvements provide improved reproducibility of narrow electrical structures and low temperature soldering processes to providing Ball Grid Array (BGA) 151, Thin Quad Flat Pack (TQFP) 152, Fine Pitch Quad Flat Package (FQFP) 153, Shrink Small Outline Package (SSOP) 154, and Thin Shrink Small Outline Package (TSOP) 155.
By the 2000s 160 these trends continue with Fine Pitch Ball Grid Array (FPGA) 163, Leadless Chip Carrier (LLCC) 166, and Quad Flat No Lead (QFN) 167. However, new demands driven by the increased consumerization of many electronic devices such as laptop computers, Personal Digital Assistants (PDAs), cellular telephones, portable multimedia players etc combined with multiple International standards for wireless infrastructure etc which require elements of the circuit be implemented two, three, even four times within the same device (such as quad-band global roaming of cellular telephones) have driven new packaging "industry standards" also. These being Multi- Chip Package (MCP) 161, System In Package (SIP) 162, Chip Scale Package (CSP) 164, Stacked Chip Scale Package (S-CSP) 165, and Wafer Level Package (WLP) 166.
An example of the scale of packaging provided by FPGA 163 today in the 2000s 160 from it's evolution in the 1980s 140 from the PGA 141 is shown by the pin configuration 200 in Fig. 2 for a 2116 contact FPGA 163 offered by Renesas Technology Corporation of Japan. Such pin configuration 200 being defined by row 210, wherein the rows 210 are separated by an industry standard pitch dy 240, and column 220, wherein the columns 220 are separated similarly by an industry standard pitch dx 230. In the pin configuration 200 for the 2116 contact FPGA 162 (Renesas Technology Part No. PRBG2116FA-A) dx 230 and dy 240 are 1.00mm. As such providing 2116 pins requires
46 rows 210 (labeled A through BF) and 46 columns 220 (labeled 1 through 46). Other industry standard pitches for dx 230 and d 240 being 0.50mm, 0.65mm, 1.27mm, and
2.54mm. Whilst typically 230 and dy 240 are the typically equal within a package such as FPGA 163 this is not always the case such as a DIP 131 wherein the row 210 may be dx = 7.62mm and the column 220 dy = 2.54mm for example, c.f. a 14-pin DIP.
Typically packages such as FPGA 163 require that the electrical interconnections from the IC to the pins are routed through multiple layers of interconnections that are vertically interconnected using electrical via structures. An exemplary cross-section of a prior art substrate forming the mounting base of an FPGA 163 is shown by multi-layer structure 350 of Fig. 3A. The process flow for the multi-layer structure 350, which is typically manufactured using low temperature co-fired ceramics (LTCCs), is outlined below in respect of Fig. 3B.
As shown the multi-layer structure 350 comprises 6 LTCC layers 321 through 325 respectively, each of which has been patterned to a varying degree with metallization, see for example upper surface metallizations 331 and 332 on LTCC layers 321 and 322 respectively, plated metallization 333 on the upper surface of LTCC layer 326 and bottom surface metallization 334 on the lower surface of LTCC layer 326. These metallization patterns are determined in respect of the circuit design wherein the multilayer structure 350 has been designed to meet specific circuits assembled to it or alternatively are determined in respect of a standard package geometry, grid array locations and internal bonding pads, all of which are not shown for clarity.
Within the multi-layer structure 350 passive electrical structures may be patterned including capacitor 363, three dimensional resistor 362, buried resistor 361 and electrical vias 370 through one or more of the LTCC layers 321 through 326. Additional features may include cavities such as cavity 385 for housing a photodetector coupled to an optical fiber 390 that has been inserted into a cavity in LTCC layer 323, and thermal vias 380. Electrical interconnection to the multi-layer structure 350 may include solder reflow for surface mount resistor 341, solder bumping for flip-chip die 351, wire bonding 352 for epoxy attached die 353 and solder reflow for flip-chip carrier 354. In addition mounting components may be undertaken on both sides of the multi-layer structure, such as exemplified by lower solder-bump die 355 but this is uncommon in respect to packaging structures, and more common with LTCC circuit boards and carrier structures.
Referring to Fig. 3B there are shown process flow 300 and schematic flow 350 for forming an LTCC structure such as the multi-layer structure 350 presented above in respect of Fig. 3A. The first step 301 comprises blanking wherein the plurality of LTCC layers 311 is formed by cutting a sheet of "green tape", not shown for clarity. In the context of "green tape" the term "green" refers to the unfired nature of the film which is comprised approximately 85-90% inorganic materials and approximately 10-15% organic materials. Similarly "tape" refers to the continuous sheets of material manufactured from Typically the inorganic materials are silicon dioxide, aluminum oxide, aluminum nitride but can include borosilicate etc according to the requirements of the LTCC. Next at step 302 the electrical and thermal vias within each sheet are formed, for example LTCC sheets 312 through 315. These electrical vias are then plated to fill them in step 303. Each of the LTCC sheets 312 through 315 having the pattern of electrical and thermal vias required to provide the necessary routing between each electrical layer that will be defined between each adjacent pair within the final multi-layer structure 350.
Next in step 304 each LTCC sheet 312 through 315 is printed with the appropriate electrical structures. Next at step 305 these LTCC sheets 312 through 315 are orientated and stacked to form unfired stack 316. In step 306 the unfired stack 315 is laminated and the LTCC sheets 312 through 315 co-fired at temperatures typically approaching 9000C thereby driving off the organics within the "green tape" and fusing them together to form co-fired stack 317. At this point in step 307 additional printing is performed, for example to provide thick film or thin film passive electrical structures such as resistors onto the outer surfaces of the co-fired stack 317 to yield finished stack 318. All that remains in step 309 is to electrically test the finished stack 318 and cut to the final dimensions thereby providing LTCC substrate 319. This cutting is generally the separation of a number of simultaneously fabricated LTCC substrates 319 from a single sheet.
Each LTCC sheet 312 through 315 is typically one of a range of standard thicknesses, such as offered by DuPont® with their Green Tape™, of 51μm, 114μm, 165μm and 254μm. It would be evident therefore that any electrical traces implemented are thereby formed by a series of electrical traces on each layer with vertical vias interconnecting them through each layer of "green tape". As such all electrical routing and structures must comply with this vertical quantization of "vias" and horizontal traces. The general form of LTCC substrates 319 providing multi-layer structure 350 is therefore one providing a single series of bond pads or bumps. However, in addition to the design constraints and routing constraints imposed by the number of layers within the multilayer structure 350, evolving packaging requirements such as Stacked Chip Scale Package (S-CSP) 165 an exemplary chip stack 400 is shown in Fig. 4.
As shown an LTCC substrate 470 has assembled a first semiconductor die 410, a first dielectric spacer 420, a second semiconductor die 430, second dielectric spacer 440, third semiconductor die 450 and fourth semiconductor die 460. On the upper surface of the LTCC substrate 470 are signal bond pads 486, power bond pads 482 and ground pads 484. From the signal bond pads 486 first wire bonds 492 interconnect to the first semiconductor die 410, second wire bonds 494 interconnect to the second semiconductor die 430, and third wire bonds 496 interconnect to the third semiconductor die 450. As shown power bond pads 482 are interconnected to the fourth semiconductor die 460 as well as ground pads 484. Also shown are stitching wire bonds 498, which route from fourth semiconductor die 460 to a fifth semiconductor die, not shown for clarity, also mounted onto the third semiconductor die 450.
As noted supra in respect of the LTCC approach to providing electrical interconnection to semiconductor die the approach is not particularly suited to provided three dimensional interconnects, and the three dimensional electrical routing within a structure is also limited. Alternative prior art solutions such as that exemplified by three- dimensional interconnect structure 500 of Fig. 5 and the corresponding electrical interconnect 550. The electrical interconnect 550 being taught by Kunishi as formed by stamping. The three dimensional interconnect structure 500 comprises a body 510, latches 506, and the electrical interconnect 550 assembled together. According the body 510 has holes 504 with sidewalls 504a and 504b that allow the electrical interconnect 550 and latches to be positioned appropriately for interconnecting to the other elements of the device of which the three dimensional interconnect structure 500 is part. As a result the latches 506 protrude through holes 504 as do interconnect tabs 502b and 502c. Protruding through another array of holes, not shown for clarity, are the edge connector contacts 502a.
Now referring to electrical interconnect 550 the plurality of electrical leads 502 can be clearly seen, each originating with an edge connector contact 502a and terminating at the other end in either a large interconnect tab 502b or small interconnect tab 502c. It would be apparent that whilst this allows for three dimensional interconnections, and suits a variety of systems such as automotive the approach is expensive and not compatible with the requirements of structures such as the Stacked Chip Scale Package (S-CSP) 165 in the exemplary chip stack 400 of Fig. 4.
Accordingly referring to Fig.6A shown is an exemplary embodiment of the invention for providing an arbitrary interconnection structure 600 between a first device 610 and second device 620. The electrical interconnection implemented within the arbitrary interconnection structure 600 being shown by connection map 690 in Fig. 6B. As such first pads 615, represented by A through F, of first device 610 are connected to the second pads 625, represented by 1 through 6, of second device 620 according to pairing (A-6), (B-5). (C-2), (D-4), (E-I), and (F-3). Disposed between the first device 610 and a second device 620, is an arbitrary interconnect 630 comprising a plurality of electrical conductors 640 through 665 disposed within. First electrical conductor 640 provides the routing (A-6), second electrical conductor 645 providing (B-5), third electrical conductor 650 implementing the connection (C-2), fourth electrical conductor providing (D-4), fifth electrical conductor providing (E-I), and the sixth electrical conductor providing the connection (F-3). An side view of the arbitrary interconnection structure 600 is shown in Fig. 6C where the electrical conductors 640 through 665 are shown having arbitrary shapes in that each of the electrical conductors 640 through 665 are implemented in their vertical and horizontal transitions to provide the required electrical interconnection with smooth curves. Within the prior art such as the LTCC substrate 319 providing multi-layer structure 350 only horizontal transitions could be implemented as continuous curves.
The provision of continuous curvilinear electrical conductors has benefits for routing high speed signals within an electrical interconnection between devices or packaging. As such routing may be implemented with the intentions of minimizing abrupt transitions rather than the typical intention of minimizing the number of layers within the structure. The arbitrary interconnect 630 may be implemented using additive manufacturing technologies such as stereolithography and three-dimensional printing.
Now referring to Fig. 7 a cross- sectional view of an arbitrary structure 700 is shown provided by another exemplary embodiment of the invention. As shown a semiconductor die 720 is mounted onto a carrier 710 between which a series of electrical interconnections are required. Accordingly the electrical interconnections are implemented with an arbitrary interconnect 730. Shown on the upper surface of the semiconductor die 720 are first and second electrical pads 776 and 778 respectively, whilst on the upper surface of the carrier 710 are first and second electrical traces 772 and 774 respectively. First electrical trace 772 is electrically connected to first arbitrary interconnect 781 which comprises a vertical transition followed by a transition out of the plane of the cross- section, the first arbitrary interconnect 781 routing towards the viewer as indicated by the conductor Θ 742.
Second electrical trace 774 is electrically interconnected to second arbitrary interconnect 782, being a vertical transition, and then interconnects to second electrical pad 778 via shaped interconnection 786 and third arbitrary interconnect 785. As is evident shaped interconnection 786 provides not only a sloped vertical transition but also a graded reduction in thickness of metallization as the shaped interconnection 786 increases its separation from the semiconductor die 720 and carrier 710. The shaped interconnection 786 is further implemented as a meta-material structure wherein isolated metallization structure 765 and embedded ground electrode 760 are designed to make the signal within the shaped interconnection 786 act in such a way as to make the shape of the signal behave as though the permittivity and permeability are different than the real component permittivity and permeability of the insulator used in providing the body of the arbitrary interconnect 730. As embedded ground electrode 760 must be interconnected to a ground potential each end of it comprises a left conductor Θ 744 and right conductor Θ 746 which route to a ground potential connection, not shown for clarity.
First electrical pad 776 is depicted with two electrical interconnections 783 and 784 respectively. First electrical interconnection 783 transitioning to a conductor ® routing away from the viewer, and second electrical interconnection 784 transitioning to a conductor Θ 748 towards the viewer. Finally embedded within the upper left corner of the arbitrary interconnect 730 is a coaxial connection 750. The coaxial connection 750 comprising central signal line 750C, outer ground ring 750B and dielectric 750A. The dielectric 750A is optionally different to the dielectric forming the body of the arbitrary interconnect 730.
Referring to Fig. 8 shown is a composite arbitrary structure 800 wherein the upper arbitrary structure 830 is combined with a lower arbitrary structure 810 in providing packaging and electrical interconnection to the semiconductor die 820. Unlike previous semiconductor die the semiconductor die 820 of Fig. 8 is backside metallised with layer 825 to improve thermal conductance and provide grounding of the semiconductor die 820. This grounding being provided by the lower conductor 880 within the lower arbitrary structure 810, which is connected to first pad 812 and thereupon to first upper conductor 832 within the upper arbitrary structure 830 wherein it is routed away towards the viewer as indicated by Θ.
Also embedded within the lower arbitrary structure 810 is databus array 870 comprising conductors 874 within a dielectric 872 that has properties different to that of lower arbitrary structure 810. Further a thermal liquid cooling element 880 is formed also within the lower arbitrary structure 810 of a further different material to that of the lower arbitrary structure 810 and dielectric 872, and comprising a series of liquid conduits 885 within which a liquid coolant may be pumped, with reservoir, heat exchange, pump etc not shown for clarity.
A second pad 814 on the upper surface of the lower arbitrary structure 810 is electrically connected to an upper electrical conductor formed by elements 852, 854, and 856 respectively in routing to second die pad 824. First and third elements 852 and 854 transitioning away from the viewer with varying thickness and separation from the semiconductor die 820 with second element 854 linking them. Said transition away from the viewer required to implement the upper electrical conductor routing around the coaxial structure 865 that couples perpendicularly away from first die pad 822. The coaxial structure 865 being comparable to coaxial connection 750 of Fig. 7. However, as shown the coaxial structure ends with a cavity 860 within the upper arbitrary structure 830. The cavity 860 being dimensioned to allow the insertion of a coaxial connector, not shown for clarity. Third die pad 826 couples directly through the body of the upper arbitrary structure 830 via power bar 864 that terminates in contact 862. Also shown embedded within the upper arbitrary structure 830 is a coplanar waveguide structure 840. As presented lower arbitrary structure 810 comprises multiple materials deposited simultaneously as the three dimension structure is manufactured, and further includes embedded cavity structures of non-rectangular cross-section. Similarly, upper arbitrary structure 830 contains mechanical fixturing, c.f. cavity 860, as well as electrical structures. Optionally, dependent upon the semiconductor die 820 the upper and lower arbitrary structures 810 and 830 respectively can be manufactured as a single piece part such that the semiconductor die 820 is inserted into a cavity. Referring to Fig. 9 A an alternate approach to the thermal management of a semiconductor die 910 is presented with plan cross-section of package 900. Unlike conventional semiconductor die the semiconductor die 910 has been metallised on all four sidewalls, this metallization being shown as top metal 910A, left metal 910B, right metal 910C, and lower metal 910D. In contact with each of the four metallised walls 910A through 910D are thermal slugs 950, six interfacing on each of the upper and lower metals 910A and 91DC respectively, and two interfacing on each of the left and right metals 910B and 910C respectively. Disposed around the periphery of the package 900, on each sidewall are heat sinks 920A through 920D in thermal contact with the thermal slugs 950. Disposed between thermal slugs 950 are arrayed electrical traces 930 together with secondary trace arrays 940 disposed in two corners of the package 900.
Shown in Fig. 9B is first cross-section Y=Y of package 900 showing the electrical traces 930 down though the package 900 and terminating in solder balls 960, top and bottom heat sinks 920A and 920D respectively and package lid 970. Within the package lid 970 are electrical traces 972 through 976 routing from the top surface contacts on the semiconductor die 910 to the electrical traces 930. As shown in cross-section Y=Y the upper and lower metallizations 910A and 910D respectively are present on the semiconductor die. Within Fig. 9C which is the second cross-section X=X of package 900 these upper and lower metallizations 910A and 910D respectively are connected to thermal slugs 950 which in turn are thermally connected to the top and bottom heat sinks 920A and 920D respectively.
As such the package 900 comprises multiple materials which are deposited simultaneously during manufacture, being the main dielectric of the package 900, metallization for electrical traces 930, which are typically copper, gold or aluminum, metal for thermal slugs, which may be molybdenum, copper, or copper-tungsten for example, and metal heat sinks, typically aluminum. Additionally deposited during the single manufacturing steps of three dimensional printing for example to form the package 900 would be for example tin- silver-copper, SnAgCu, to provide lead free soldering. The thermal slugs may optionally be beryllia, beryllium oxide.
Current packaging solutions identified above as "industry standard" provide electrical interconnections on only one side / surface of the package. However, in many instances it would be beneficial to provide electrical interconnections on multiple sides / surfaces of a package. Such an approach allowing for example packages to be stacked vertically and horizontally such that electrical interconnects were made directly package to package rather than via an intermediate circuit board or flexible interconnect. Such an exemplary distributed interconnect package 1000 is shown in Fig. 10. The distributed interconnect package 1000 comprising 26 surfaces, and having a structure similar to gem cuts in being a rectangular structure with bevel on each corner. As shown an upper surface 1010 comprises a first array of electrical interconnects 1015, a side wall 1030 provides a second array of electrical interconnects 1035, and the bevel surface 1020 between upper surface 1010 and sidewall 1030 provides a third array of electrical interconnects 1035. End wall 1040 has first DC interconnect 1045, such as ground, as well as corner bevel 1050 which provides a second DC interconnect 1055. Optionally, using three dimensional printing the distributed interconnect package 1000 may be provided with pins or sockets respectively for each of the represented electrical interconnections 1015, 1025, 1035, 1045 and 1055. These pins and sockets thereby forming mating halves of electrical connectors. Additionally the three dimensional printing of the distributed interconnect package 1000 may include mechanical features such as mounting holes, threaded inserts, etc allowing the distributed interconnect package 1000 to be physically interconnected to other distributed interconnect packages 1000, standard connectors, or circuit boards, device panels, etc. Numerous other embodiments may be envisaged without departing from the spirit or scope of the invention.

Claims

1. A method comprising:
(a) providing a design file relating to a mechanical structure for interfacing to at least an electrical device, the design file comprising at least two of electrical input and output coordinates of the mechanical structure, electrical path information for paths interconnecting the electrical input and outputs, mechanical attributes of the semiconductor die, mechanical attributes of the mechanical structure, and a list of materials; and
(b) executing the design file with a three dimensional manufacturing system; the three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of any material from the list of materials with a thickness less than the thickness of any element within the mechanical structure.
2. A method according to claim 1 wherein,
(b) executing the design file further comprises mounting the at least an electrical device at a predetermined point within the execution of the design file into the partially completed mechanical structure.
3. A method according to claim 1 wherein, the addition of a material with a thickness less than the thickness of any element within the mechanical structure comprises adding a thickness less than half that of the thinnest electrical element within the structure.
4. A method according to claim 1 wherein, providing electrical path information comprises providing an electrical path that is continuous in at least its first derivative.
5. A method according to claim 1 wherein, providing the mechanical structure comprises providing at least one of electrical interconnection, thermal management, and mechanical mounting to the at least an electrical device.
6. A method according to claim 1 wherein, (b) executing the design file further comprises the simultaneous addition of at least two materials from the list of materials at the same level and different locations within the mechanical structure during at least one of a plurality of sequential manufacturing operations.
7. A method according to claim 1 wherein, executing the design file results in the mechanical structure being manufactured along an axis other than the axis perpendicular to a principle surface of the electrical device when the mechanical structure and electrical device are assembled together.
8. A method according to claim 1 wherein, providing mechanical attributes comprises providing data indicating at least one of the presence, absence, and percentage of each material of the list of materials for each quantized location within the mechanical structure, the quantized locations determined in dependence of at least one of the design file and three dimensional manufacturing system.
9. A method according to claim 1 absent the removal of any material from the mechanical structure during the execution of the design file.
10. A method comprising: providing a design file relating to a mechanical structure for interfacing to at least an electrical device and comprising at least two of electrical input and output coordinates of the mechanical structure, electrical path information for paths interconnecting the electrical input and outputs, mechanical attributes of the semiconductor die, mechanical attributes of the mechanical structure, and a list of materials, the design file relating to controlling a three dimensional manufacturing system capable of generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations involving the addition of any material from the list of materials with a thickness less than the thickness of any element within the mechanical structure.
11. A method according to claim 10 wherein; providing the design file is by at least one of an electronic transmission, a computer readable storage medium, a physical print out of the design file, and translating a computer aided design file to a format compatible with the three dimensional manufacturing system.
12. A method comprising: (a) providing at least an electrical device of a plurality of electrical devices;
(b) providing a mechanical structure, the mechanical structure for interfacing to at least a predetermined portion of at least one electrical device of the plurality of electrical devices, the mechanical structure manufactured with a three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of material with a thickness less than the smallest thickness of any element within the mechanical structure; and
(c) interconnecting the mechanical structure to the at least one electrical device of the plurality of electrical devices.
13. A method according to claim 12 wherein,
(c) interconnecting the mechanical structure comprises providing at least one of a mechanical mounting, an electrical interconnection, and a thermal interconnection to the at least one of the plurality of electrical devices.
14. A method according to claim 12 wherein,
(a) providing at least an electrical device comprises providing the at least an electrical device of a plurality of electrical devices as a first mechanical assembly; and (c) interconnecting the mechanical structure comprises interconnecting the mechanical structure to at least a predetermined portion of the first mechanical assembly.
15. A method according to claim 14 wherein,
(c) interconnecting the mechanical structure comprises providing electrical interconnection from the at least an electrical device of a plurality of electrical devices to a predetermined portion of the first mechanical assembly.
16. A method according to claim 12 wherein,
(c) interconnecting the mechanical structure comprises interconnecting only electrical interconnections of the at least an electrical device of a plurality of electrical devices to at least one of itself and another of the plurality of electrical devices.
17. A method according to claim 12 wherein, providing at least an electrical device comprises providing at least one of a semiconductor die, a semiconductor die mounted to a carrier, a substrate having electrical traces deposited thereon, a package, a predetermined portion of a semiconductor wafer, and a discrete electrical component.
18. A method according to claim 12 wherein, the mechanical structure comprises at least one of metallic materials, dielectric materials, and meta-materials.
19. A method according to claim 12 wherein, the mechanical structure provides at least one of an electrical tab connection, a solder bump, a wire bond pad, a package pin, a socket for an electrical connector, a receptacle for inserting an electrical connector, a threaded region for accepting a matching thread from a fastening, a void, a hole allowing insertion there-through of a fastening, a mounting surface for an integrated circuit, a mounting for an optical fiber, a mounting for an optoelectronic component, a cavity, a tube,
20. A method according to claim 12 wherein, providing the mechanical structure comprises providing at least one of a plurality of electrical paths, each electrical path being at least one of a discrete conductor, a coplanar waveguide, a coaxial waveguide, a coplanar strip, a transmission line segment, a transmission line segment with meta-material elements, an electrical plane, and a series of continuous conductor elements.
21. A method according to claim 20 wherein, each electrical path comprises providing an electrical path that is at least one of continuous in at least its first derivative and contains approximately abrupt transitions in direction.
22. A method comprising:
(a) providing at least an electrical device of a plurality of electrical devices; and
(b) generating a mechanical structure in association with the at least an electrical device of the plurality of electrical devices, the mechanical structure for interfacing to at least a predetermined portion of at least one electrical device of the plurality of electrical devices, the mechanical structure manufactured with a three dimensional manufacturing system generating the mechanical structure as a single piece part from at least one of a plurality of sequential manufacturing operations, each of the plurality of sequential manufacturing operations involving the addition of material with a thickness less than the smallest thickness of any element within the mechanical structure.
23. A method according to claim 22 wherein;
(b) generating a mechanical structure comprises generating a predetermined portion of the mechanical structure directly onto a predetermined region of the at least an electrical device of the plurality of electrical devices.
EP08807647A 2007-09-14 2008-09-12 Method and apparatus for forming arbitrary structures for integrated circuit devices Withdrawn EP2195830A2 (en)

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US9818665B2 (en) 2014-02-28 2017-11-14 Infineon Technologies Ag Method of packaging a semiconductor chip using a 3D printing process and semiconductor package having angled surfaces
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US5278442A (en) * 1991-07-15 1994-01-11 Prinz Fritz B Electronic packages and smart structures formed by thermal spray deposition
US5779833A (en) * 1995-08-04 1998-07-14 Case Western Reserve University Method for constructing three dimensional bodies from laminations

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* Cited by examiner, † Cited by third party
Title
See references of WO2009034557A2 *

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