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EP2033219A1 - Power housing for semiconductor chips and the arrangement thereof for heat dissipation - Google Patents

Power housing for semiconductor chips and the arrangement thereof for heat dissipation

Info

Publication number
EP2033219A1
EP2033219A1 EP06804809A EP06804809A EP2033219A1 EP 2033219 A1 EP2033219 A1 EP 2033219A1 EP 06804809 A EP06804809 A EP 06804809A EP 06804809 A EP06804809 A EP 06804809A EP 2033219 A1 EP2033219 A1 EP 2033219A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor chips
housing
chip carrier
heat dissipation
carrier substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06804809A
Other languages
German (de)
French (fr)
Inventor
Egbert Freiberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Creative Led GmbH
Original Assignee
Creative Led GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Creative Led GmbH filed Critical Creative Led GmbH
Publication of EP2033219A1 publication Critical patent/EP2033219A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink

Definitions

  • the invention relates to an auto-mountable surface-mount power housing for semiconductor chips and their arrangement for heat dissipation in conjunction with a wiring substrate and a cooling medium with optimized high heat dissipation when using one or more semiconductor chips, for example radiation-emitting devices with the same and mixed, arbitrary wavelength in a housing and any internal interconnection, which make a high current load and the removal of the associated heat generation necessary.
  • Another known disadvantage is that all previously known housing, which can derive a higher power dissipation, can not be used for use in conjunction with flexible circuit boards.
  • Another known disadvantage is that no multi-layer wiring levels can be applied, which leads to a reduction in the compactness of the devices and the associated disadvantages of an application.
  • the object of the present invention is to make the design for power housing for semiconductor chips so that on the one hand the number of thermal resistances is reduced and on the other hand, the electrical connection capability of the component independent of any cooling media use of the existing soldering technology for the electrical connection and, if necessary, also for the mechanical and thermal connection with the cooling medium and an unrestricted use in conjunction with flexible Wiring carriers, for example, in flexible printed circuit boards, with full potential freedom is possible.
  • the solution of the problem is achieved according to the invention that is omitted for mounting the formative of the prior art placement of the component housing on the wiring medium, for example, a circuit board, which is connected by heat resistance to the cooling medium constructive.
  • the wiring medium from the chain of thermal transitions is completely removed and the thermal coupling can be done directly with the cooling medium, the electrical connection via the wiring medium, which just not applied in the prior art solid connection with the cooling medium has, for example, metal core board, but continues to be so that the assembly can be done with the power housing for semiconductor chips according to the known rules of soldering and the arrangement for heat dissipation by applying the built in the wiring medium power housing for semiconductor chips is formed on the cooling medium.
  • the power housing for semiconductor chips must be constructed so that on the one hand take place the direct contact with the cooling medium and at the same time the electrical connection can be constructively self-sufficient and executed independently.
  • the invention is explained symbolically and by way of example closer.
  • FIG. 4 shows an example embodiment of the isolated chip metallization of the power housing for semiconductor chips with self-aligning position positioning or different polarity
  • the direct thermal coupling is effected according to the invention in that the wiring carrier (14) contains an opening (21) adapted to the chip carrier substrate (12), whereby only the chip carrier substrate (12) is inserted, which is electrically conductively connected to the housing carrier substrate (13) Connected sides and at the same time realized the mechanical connection.
  • Housing support substrate (13) and chip carrier substrate (12) form the structural unit of the housing, which is part of the overall arrangement according to the invention for heat dissipation with the other components cooling medium (15) and wiring substrate (14).
  • the chip carrier substrate (12) thus allows the direct connection assembly with the cooling medium (15) via a townleititatismaterial (16) without thermally intermediate wiring carrier (14) for electrical connection of the device.
  • the chip carrier substrate (12) consists of conductor tracks structured ceramic material or silicon or a constructive combination of the two. Typically, but not compulsorily, a metallized surface which is electrically insulated from the outside is provided in the center, the chip carrier metallization (23) for mounting the semiconductor chips (10). This Chipisme (23) is designed in such a way that the chips can be mounted by means of conventional conductive adhesive or fins.
  • the back surface of the chip carrier substrate (12) metallized executable and thus allows a soldering by means of lead-free solders on the cooling medium (15).
  • the top of the chip carrier substrate (12) with silicon dioxide applied as insulation and metallization applied thereto.
  • the housing support substrate (13) consists of ceramic or laminate materials with adapted thermal expansion coefficients to the chip carrier substrate (12).
  • the sauceleittellsmaterial (16) consists of any suitable for heat dissipation materials, for example, metallic solders when mounted by soldering or thermally conductive adhesives and pastes.
  • Design tolerances and assembly-related unevenness can be compensated for by means of self-adhesive or single-sided or double-sided self-adhesive halogen-free and lead-free politiciansleitucunsmaterialien (16) by means of conventional tools.
  • the electrical connection between the semiconductor chip (10) and the bonding wires (11) to the wiring level (25) on the wiring substrate (14) is achieved in that the chip carrier substrate (12) metallic over the wiring level of the housing support (20) with the opposite Genzouselect (13) via the wiring level for electrical connection the chip carrier substrate (22) is geometrically larger than the chip carrier substrate (12), in order to achieve that an electrical connection to the wiring carrier (14) for connecting the semiconductor chip (10) takes place to an external circuit.
  • the thickness of the chip carrier substrate is adapted to the thickness of the wiring substrate so that it terminates at least at the same level. Furthermore, the disadvantage in the soldering process is eliminated since the component housing can be connected to the wiring support (14) for connection of the component under existing technologically proven soldering processes including the standardized soldering times (soldering profiles).
  • the method of assembly is carried out by simply applying the fully assembled wiring substrate (14) after the soldering of inventively realized mecanicalden electronic components on the heat sink, optionally using a fixing material (24), which may also be thermally conductive.
  • a fixing material 24
  • the thermal connection can be improved by means of a heat-conducting connection material (16) underneath the chip carrier substrate (12).
  • a thermal connection on the surface of the wiring substrate (14) can be achieved by thermally bonding between the wiring plane of the wiring substrate (25) and the metallic connection plane (27) electrically insulated at the wiring plane of the housing support substrate (20) is, during the soldering process is connected with metallic.
  • the isolation of the individual wirings on the chip carrier substrate (12) and the housing support substrate (13) takes place horizontally via an insulating passivation (26), for example made of glass, according to FIG. 2, which simultaneously realizes a sealing of the overall arrangement.
  • an insulating passivation for example made of glass, according to FIG. 2, which simultaneously realizes a sealing of the overall arrangement.
  • the mechanical connection strength of the housing assembly of the two parts chip carrier substrate (12) and housing support substrate (13) by a combined or simultaneous sintering of the glass passivation (26) and the metallic wiring of conductive pastes on the chip carrier substrate (12) and the housing support substrate (13). be achieved.
  • the chip carrier substrate (12) and the housing support substrate (13) regardless of the materials used by a bonding process or soldering process by means of electrically conductive material, the wiring level of the chip carrier and the wiring level of the housing support are connected.
  • the protection of the semiconductor chips (10) and the bonding wires (11) is carried out by any potting materials based on epoxy or silicones with adapted thermal expansion coefficient. Also, a closure by gluing or soldering a lid is possible.
  • an optical encapsulation (17) is executed with level or curved shape according to the required optical properties in the emission opening (18).
  • the shape of the emission opening (18), which simultaneously allows the passage of the radiation, can be carried out in any manner and is subject exclusively to the technical requirements of the optical characteristics of the application.
  • the function of the wiring level of the housing carrier substrate (20) is reduced to the mechanical connection between chip carrier substrate (12) and housing carrier substrate (13), wherein the electrical connection now directly between the wiring level of the chip carrier substrate (22) and the wiring level (25) of the wiring substrate ( 14) can take place.
  • the chip carrier substrate (12) On the chip carrier substrate (12) is a metallized surface for mounting the half-chips (10) by means of conventional bonding method by using adhesive Leitmaterialien. If a eutectic chip bonding is to be carried out, the metallization of the chip carrier metallization (23) is structured as a function of the chip size in partial areas of the chip carrier metallization (28) in order to reduce or avoid floating effects. This structuring is carried out in such a way that the semiconductor chips (10) are self-aligned using the surface tension of the liquid solder.
  • FIG. 4 shows the detailed structure of an isolated chip carrier metallization (23) of the chip carrier substrate (12) for receiving the semiconductor chips (10) in partial areas of the chip carrier metallization (28).
  • the dimensions of the individual semiconductor chips (10) plus a border gives the size of a partial area of the chip carrier metallization (28), which can be arbitrarily configured in arrangement and number.
  • Connected are the partial surfaces of the Chipangometallmaschine (28) with electrically conductive connecting webs and small bonding surfaces (29), which are necessary for bilaterally to be contacted semiconductor chips (10), in one-sided components to be contacted, this part and the web omitted if the contact of the Upper side takes place.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to a surface-mountable power housing (1) for semiconductor chips (10) and the arrangement thereof for heat dissipation at cooling media (15) in high-power components by reducing the constructionally dictated thermal resistances lying in series. The power housing is formed in such a way that the underside can be connected directly to the heat sink (15) through an opening (21) in the wiring plane (25), and the required wiring plane is not incorporated. The housing is embodied from a chip carrier substrate (12) and a housing carrier substrate (13), which are provided with electrical connections for contact-connecting the semiconductor chips (10) to the wiring plane (25). The power housing preferably comprises ceramic materials or silicon.

Description

Leistungsgehäuse für Halbleiterchips und deren Anordnung zur Power housing for semiconductor chips and their arrangement for
Wärmeabfuhrheat dissipation
Beschreibungdescription
[0001] Die Erfindung betrifft ein automatisch bestückbares oberflächenmontierbares Leistungsgehäuse für Halbleiterchips und deren Anordnung zur Wärmeabfuhr in Verbindung mit einem Verdrahtungsträger und einem Kühlmedium mit optimiert hoher Wärmeabfuhr bei Verwendung von einem oder mehreren Halbleiterchips, zum Beispiel Strahlungsemittierende Bauelemente mit gleicher und auch gemischter, beliebiger Wellenlänge in einem Gehäuse und beliebiger interner Verschaltung, welche eine hohe Strombelastung und die Abführung der damit verbundenen Wärmeerzeugung notwendig machen.The invention relates to an auto-mountable surface-mount power housing for semiconductor chips and their arrangement for heat dissipation in conjunction with a wiring substrate and a cooling medium with optimized high heat dissipation when using one or more semiconductor chips, for example radiation-emitting devices with the same and mixed, arbitrary wavelength in a housing and any internal interconnection, which make a high current load and the removal of the associated heat generation necessary.
[0002] Alle bisher bekannten Gehäuse zur Oberflächenmontage, zum Beispiel das in DE10117889 beschriebene, benutzen das Aufsetzprinzip des Bauteiles auf einen Verdrahtungsträger. Die Konstruktion zeichnet sich dadurch aus, dass die Kontaktflächen zum elektrischen Anschluss des Bauteiles sich entweder auf der Rückseite des Gehäuses oder als separater von diesem herausgeführter metallischer Anschluss so gebogen ist, dass die Lötverbindung auf der Ebene der Bauteilunterseite ist.All previously known housing for surface mounting, for example, described in DE10117889, use the placement principle of the component on a wiring substrate. The construction is characterized in that the contact surfaces for the electrical connection of the component is bent either on the back of the housing or as a separate lead out of this metallic connection so that the solder joint is on the level of the component bottom.
Durch Konstruktionen dieser Gehäuse und deren elektrische Verbindung zum Verdrahtungsträger, insbesondere kostenintensiver Metallkernleiterplatten oder anderer üblicher Verdrahtungsmedien, werden Anordnungen geschaffen, die mehrere thermische Widerstände besitzen. Trotz konstruktiver Ansätze hat die Praxis bisher gezeigt, daß es keine automatisch bestückbaren und lötbaren Leistungsgehäuse für Halbleiterchips für hohe Leistungen mit hoher direkter Wärmeabführungskapazität bis zum Kühlmedium gibt. Die physikalisch bedingte Addition der einzelnen, in Reihe liegenden thermischen Widerstände begrenzt die umsetzbare Verlustleistung der Anordnungen von zu Degradation neigenden Bauelementen und führt zu deren erheblicher Lebensdauereinschränkung.Constructions of these housings and their electrical connection to the wiring substrate, in particular cost-intensive metal core circuit boards or other conventional wiring media, arrangements are created which have a plurality of thermal resistances. Despite constructive approaches, the practice has been shown that there are no automatically populated and solderable power housing for semiconductor chips for high performance with high direct heat dissipation capacity to the cooling medium. The physical addition of the individual series thermal resistors limits the achievable power loss Arrangements of degradation-prone components and leads to their significant lifetime restriction.
[0003] Erheblicher Nachteil der bisher bekannten Anordnungen ist, daß das notwendige Kühlmedium, z.B. ein Kühlkörper oder eine Metallkernleiterplatte beim Lötprozess mit erwärmt werden muß, so daß die Verweildauer der Halbleiterchips über das erforderliche Maß an Zeit einer thermischen Belastung unterliegt, welches ebenfalls zur Vorschädigung oder zum Ausfall führen kann.Significant disadvantage of the previously known arrangements is that the necessary cooling medium, e.g. a heat sink or a metal core board during the soldering process must be heated with, so that the residence time of the semiconductor chips over the required amount of time is subject to thermal stress, which can also lead to pre-damage or failure.
[0004] Weiterer bekannter Nachteil ist, daß Spannungspotentiale zum Beispiel der Anode oder Kathode des Halbleiterchips metallisch nach außen geführt und zwangsläufig auf das Kühlmedium übertragen werden. Dies führt zu erheblichen konstruktiven Einschränkungen, die nur durch Einfügen von potentialtrennenden Medien zwischen Halbleiterbauelemente und Kühlmedium beseitigt werden können, diese aber gleichzeitig eine Erhöhung der Anzahl der unerwünschten thermischen Widerstände bewirken.Another known disadvantage is that voltage potentials, for example, the anode or cathode of the semiconductor chip are led outwardly metallic and inevitably transferred to the cooling medium. This leads to considerable structural limitations that can be eliminated only by inserting potential-separating media between semiconductor devices and cooling medium, but at the same time cause an increase in the number of unwanted thermal resistances.
[[0005] Desweiteren bekannter Nachteil ist, daß alle bisher bekannten Gehäuse, die eine höhere Verlustleistung ableiten können, nicht für den Einsatz in Verbindung mit flexiblen Leiterplatten genutzt werden können.Another known disadvantage is that all previously known housing, which can derive a higher power dissipation, can not be used for use in conjunction with flexible circuit boards.
Ein weiterer bekannter Nachteil ist, daß keine mehrlagigen Verdrahtungsebenen angewandt werden können, was zu einer Verringerung der Kompaktheit der Geräte und den damit verbundenen Nachteilen einer Applikation führt.Another known disadvantage is that no multi-layer wiring levels can be applied, which leads to a reduction in the compactness of the devices and the associated disadvantages of an application.
[0006] Die Aufgabe der vorliegenden Erfindung ist es, die Ausführung für Leistungsgehäuse für Halbleiterchips so zu gestalten, daß einerseits die Anzahl der thermischen Widerstände reduziert wird und andererseits die elektrische Anschlußfähigkeit des Bauteiles eine von jeglichen Kühlmedien unabhängige Nutzung der vorhandenen Löttechnologie für die elektrische Verbindung sowie falls erforderlich auch für die mechanische und thermische Verbindung mit dem Kühlmedium ermöglicht und einen uneingeschränkten Einsatz in Verbindung mit flexiblen Verdrahtungsträgern, zum Beispiel bei flexiblen Leiterplatten, bei voller Potentialfreiheit möglich ist.The object of the present invention is to make the design for power housing for semiconductor chips so that on the one hand the number of thermal resistances is reduced and on the other hand, the electrical connection capability of the component independent of any cooling media use of the existing soldering technology for the electrical connection and, if necessary, also for the mechanical and thermal connection with the cooling medium and an unrestricted use in conjunction with flexible Wiring carriers, for example, in flexible printed circuit boards, with full potential freedom is possible.
[0007] Der Erfinder erkannte, daß der Gesamtthermowiderstand und damit die erforderliche Wärmeabfuhrkapazität nur zu beeinflussen ist und erheblich verkleinert werden kann, wenn die Gehäusekonstruktion des Leistungsgehäuse für Halbleiterchips die Anzahl der sich addierenden einzelnen thermischen Widerstände reduziert und in einer Anordnung von Kühlmedium und Verdrahtungsträger eine Einheit bildet. Trotzdem soll eine automatisierte Bestückung sowie Nutzung vorhandene Löttechnologien erreichbar sein, um die technologischen und ökonomischen Vorteile der Oberflächenmontage bei Verwendung von flexiblen und starren Verdrahtungsträgern effizient zu nutzen.The inventor recognized that the Gesamtthermowiderstand and thus the required heat dissipation capacity can only be influenced and can be significantly reduced if the housing construction of the power housing for semiconductor chips reduces the number of adding individual thermal resistances and in an arrangement of cooling medium and wiring substrate a Unit forms. Nevertheless, automated assembly and use of existing soldering technologies should be achievable to efficiently utilize the technological and economical benefits of surface mounting when using flexible and rigid wiring substrates.
[0008] Die Lösung der Aufgabe wird erfindungsgemäss dadurch erreicht, daß zur Montage dem vom Stand der Technik prägenden Aufsetzen des Bauteilgehäuses auf das Verdrahtungsmedium, zum Beispiel einer Leiterplatte abgegangen wird, welches über Wärmewiderstände mit dem Kühlmedium konstruktiv verbunden ist. Erfindungsgemäß wird erreicht, daß das Verdrahtungsmedium aus der Kette der thermischen Übergänge komplett herausgenommen wird und die thermische Kopplung dadurch direkt mit dem Kühlmedium erfolgen kann, die elektrische Verbindung über das Verdrahtungsmedium, welches eben nicht die gemäß dem Stand der Technik angewandte feste Verbindung mit dem Kühlmedium besitzt zum Beispiel Metallkernleiterplatte, aber weiterhin so erfolgt, daß die Bestückung mit dem Leistungsgehäuse für Halbleiterchips nach den bekannten Regeln der Löttechnik erfolgen kann und die Anordnung zur Wärmeabfuhr durch Aufbringen der im Verdrahtungsmedium eingebauten Leistungsgehäuse für Halbleiterchips auf das Kühlmedium entsteht. Um dies zu erreichen, muß das Leistungsgehäuse für Halbleiterchips so aufgebaut sein, daß einerseits der direkte Kontakt zum Kühlmedium erfolgen und gleichzeitig die elektrische Verbindung konstruktiv autark und unabhängig davon ausgeführt werden kann. [0009] Anhand von Figuren wird die Erfindung symbolisch und beispielhaft näher erläutert.The solution of the problem is achieved according to the invention that is omitted for mounting the formative of the prior art placement of the component housing on the wiring medium, for example, a circuit board, which is connected by heat resistance to the cooling medium constructive. According to the invention it is achieved that the wiring medium from the chain of thermal transitions is completely removed and the thermal coupling can be done directly with the cooling medium, the electrical connection via the wiring medium, which just not applied in the prior art solid connection with the cooling medium has, for example, metal core board, but continues to be so that the assembly can be done with the power housing for semiconductor chips according to the known rules of soldering and the arrangement for heat dissipation by applying the built in the wiring medium power housing for semiconductor chips is formed on the cooling medium. To achieve this, the power housing for semiconductor chips must be constructed so that on the one hand take place the direct contact with the cooling medium and at the same time the electrical connection can be constructively self-sufficient and executed independently. Based on figures, the invention is explained symbolically and by way of example closer.
Es zeigen dabeiIt show here
Fig.1 - X-Darstellung des Leistungsgehäuse für HalbleiterchipsFig.1 - X representation of the power housing for semiconductor chips
Fig.2 - Y-Darstellung des Leistungsgehäuse für HalbleiterchipsFig.2 - Y representation of the power housing for semiconductor chips
Fig.3 - Inverse -Darstellung des Leistungsgehäuse für Halbleiterchips3 shows inverse illustration of the power housing for semiconductor chips
Fig.4 - Darstellung einer Beispielausführung der isolierten Chipmetallisierung des Leistungsgehäuse für Halbleiterchips bei selbstjustierender Lagepositionierung oder unterschiedlicher Polarität4 shows an example embodiment of the isolated chip metallization of the power housing for semiconductor chips with self-aligning position positioning or different polarity
[0010] Die Erfindung wird anhand von Fig.1 näher erläutert .The invention will be explained in more detail with reference to FIG.
Die direkte thermische Kopplung erfolgt erfindungsgemäß dadurch, daß der Verdrahtungsträger (14) eine dem Chipträgersubstrat (12) angepaßte Öffnung (21) enthält, wobei nur das Chipträgersubstrat (12) durchgesteckt wird, welches mit dem Gehäuseträgersubstrat (13) elektrisch leitend an den sich gegenüberliegenden Seiten verbunden ist und gleichzeitig die mechanische Verbindung realisiert. Gehäuseträgersubstrat (13) und Chipträgersubstrat (12) bilden die konstruktive Einheit des Gehäuses, welches Teil der erfindungsgemäßen Gesamtanordnung zur Wärmeabfuhr mit den weiteren Bestandteilen Kühlmedium (15) und Verdrahtungsträger (14) ist.The direct thermal coupling is effected according to the invention in that the wiring carrier (14) contains an opening (21) adapted to the chip carrier substrate (12), whereby only the chip carrier substrate (12) is inserted, which is electrically conductively connected to the housing carrier substrate (13) Connected sides and at the same time realized the mechanical connection. Housing support substrate (13) and chip carrier substrate (12) form the structural unit of the housing, which is part of the overall arrangement according to the invention for heat dissipation with the other components cooling medium (15) and wiring substrate (14).
[0011] Das Chipträgersubstrat (12) gestattet somit die direkte Verbindungsmontage mit dem Kühlmedium (15) auch über ein Wärmeleitverbindungsmaterial (16) ohne thermisch zwischenliegenden Verdrahtungsträger (14) zum elektrischen Anschluß des Bauelementes. [0012] Das Chipträgersubstrat (12) besteht aus mit Leiterbahnen strukturierten Keramikmaterial oder Silizium oder eine konstruktive Kombination aus beiden. Typischerweise, aber nicht zwingend vorgeschrieben, ist mittig eine nach aussen elektrisch isolierte metallisierten Fläche, die Chipträgermetallisierung (23) zur Montage der Halbleiterchips (10) vorhanden. Diese Chipträgermetallisierung (23) ist von der Beschaffenheit so ausgelegt, dass die Chips mittels üblicher Leitkleber oder Schmelzlote montiert werden können.The chip carrier substrate (12) thus allows the direct connection assembly with the cooling medium (15) via a Wärmeleitverbindungsmaterial (16) without thermally intermediate wiring carrier (14) for electrical connection of the device. The chip carrier substrate (12) consists of conductor tracks structured ceramic material or silicon or a constructive combination of the two. Typically, but not compulsorily, a metallized surface which is electrically insulated from the outside is provided in the center, the chip carrier metallization (23) for mounting the semiconductor chips (10). This Chipträgermetallisierung (23) is designed in such a way that the chips can be mounted by means of conventional conductive adhesive or fins.
[0013] Zur weiteren Senkung des verbleibenden Wärmeübergangswiderstandes ist die Rückseitenoberfläche des Chipträgersubstrates (12) metallisiert ausführbar und gestattet somit ein Auflöten mittels bleifreier Lote auf das Kühlmedium (15). Bei Anwendung von Silizium ist die Oberseite des Chipträgersubstrates (12) mit aufgebrachtem Siliziumdioxid als Isolierung und darauf aufgebrachter Metallisierung.To further reduce the remaining heat transfer resistance, the back surface of the chip carrier substrate (12) metallized executable and thus allows a soldering by means of lead-free solders on the cooling medium (15). When silicon is used, the top of the chip carrier substrate (12) with silicon dioxide applied as insulation and metallization applied thereto.
[0014] Das Gehäuseträgersubstrat (13) besteht aus keramischen oder Laminatwerkstoffen mit angepasstem Temperaturausdehnungskoeffizienten zum Chipträgersubstrat (12).The housing support substrate (13) consists of ceramic or laminate materials with adapted thermal expansion coefficients to the chip carrier substrate (12).
[0015] Das Wärmeleitverbindungsmaterial (16) besteht aus jeglichen zur Wärmeableitung geeigneten Materialien, zum Beispiel aus metallischen Loten bei Montage durch Löten oder aus wärmeleitenden Klebern und Pasten.The Wärmeleitverbindungsmaterial (16) consists of any suitable for heat dissipation materials, for example, metallic solders when mounted by soldering or thermally conductive adhesives and pastes.
[0016] Konstruktive Toleranzen und montagebedingte Unebenheiten können mittels Aufpressen von selbsthaftenden oder einseitig oder zweiseitig selbstklebenden halogenfreien und bleifreien Wärmeleitverbindungsmaterialien (16) mittels dafür üblicher Werkzeuge ausgeglichen werden.Design tolerances and assembly-related unevenness can be compensated for by means of self-adhesive or single-sided or double-sided self-adhesive halogen-free and lead-free Wärmeleitverbindungsmaterialien (16) by means of conventional tools.
[0017] Die elektrische Anschlußverbindung zwischen Halbleiterchip (10) sowie deren Bonddrähte (11) bis zur Verdrahtungsebene (25) auf dem Verdrahtungsträger (14) wird dadurch erreicht, daß das Chipträgersubstrat (12) metallisch über die Verdrahtungsebene des Gehäuseträgers (20) , welche mit dem gegenüberliegenden Gehäuseträgersubstrat (13) über die Verdrahtungsebene zur elektrischen Verbindung des Chipträgersubstrates (22) verbunden ist, welches geometrisch größer als das Chipträgersubstrat (12) ist, um zu erreichen, daß eine elektrische Verbindung zum Verdrahtungsträger (14) zum Anschluß des Halbleiterchips (10) an eine externe Beschaltung erfolgt.The electrical connection between the semiconductor chip (10) and the bonding wires (11) to the wiring level (25) on the wiring substrate (14) is achieved in that the chip carrier substrate (12) metallic over the wiring level of the housing support (20) with the opposite Gehäuseträgersubstrat (13) via the wiring level for electrical connection the chip carrier substrate (22) is geometrically larger than the chip carrier substrate (12), in order to achieve that an electrical connection to the wiring carrier (14) for connecting the semiconductor chip (10) takes place to an external circuit.
[0018] Dabei ist es unerheblich, welche Stärke der Verdrahtungsträger (14) zum Anschluß des Halbleiterchips besitzt, da dieser dadurch keinen Einfluß auf das Wärmeableitverhalten hat. Die Stärke des Chipträgersubstrates ist der Stärke des Verdrahtungsträgers so angepaßt , daß dieser mindestens Niveaugleich abschließt. Weiterhin ist der Nachteil beim Lötprozeß beseitigt, da die Bauteilgehäuse mit dem Verdrahtungsträger (14) zum Anschluß des Bauteiles unter vorhandenen technologisch bewährten Lötprozessen einschließlich der standardisierten Lötzeiten (Lötprofile) verbunden werden können.It is irrelevant what strength of the wiring substrate (14) for connecting the semiconductor chip, since this has no effect on the heat dissipation behavior. The thickness of the chip carrier substrate is adapted to the thickness of the wiring substrate so that it terminates at least at the same level. Furthermore, the disadvantage in the soldering process is eliminated since the component housing can be connected to the wiring support (14) for connection of the component under existing technologically proven soldering processes including the standardized soldering times (soldering profiles).
[0019] Das Verfahren der Montage erfolgt durch einfaches Aufbringen der komplett bestückten Verdrahtungsträger (14) nach dem Lötprozess der erfindungsgemäß realisierten aufzumontierenden elektronischen Bauelemente auf dem Kühlkörper, gegebenenfalls unter Verwendung eines Fixiermaterials (24), welches auch wärmeleitfähig sein kann. Bei dieser Montage ist es nur notwendig, daß das Chipträgersubstrat (12) direkt mit dem Kühlmedium (15) verbunden ist. Gegebenfalls kann die thermische Verbindung mittels eines Wärmeleitverbindungsmaterial (16) unterhalb des Chipträgersubstrates (12) verbessert werden. Eine thermische Verbindung auf der Oberfläche des Verdrahtungsträgers (14) kann zusätzlich erreicht werden, indem eine thermische Verbindung zwischen der Verdrahtungsebene des Verdrahtungsträgers (25) und der metallischen Verbindungsebene (27), die elektrisch isoliert auf der Ebene der Verdrahtungsebene des Gehäuseträgersubstrat (20) sich befindet, beim Lötprozess metallisch mit verbunden wird.The method of assembly is carried out by simply applying the fully assembled wiring substrate (14) after the soldering of inventively realized aufzumontierenden electronic components on the heat sink, optionally using a fixing material (24), which may also be thermally conductive. In this assembly, it is only necessary that the chip carrier substrate (12) is connected directly to the cooling medium (15). If appropriate, the thermal connection can be improved by means of a heat-conducting connection material (16) underneath the chip carrier substrate (12). In addition, a thermal connection on the surface of the wiring substrate (14) can be achieved by thermally bonding between the wiring plane of the wiring substrate (25) and the metallic connection plane (27) electrically insulated at the wiring plane of the housing support substrate (20) is, during the soldering process is connected with metallic.
[0020] Die Isolierung der einzelnen Verdrahtungen auf dem Chipträgersubstrat (12) und dem Gehäuseträgersubstrat (13) erfolgt horizontal über eine isolierende Passivierung (26) , zum Beispiel aus Glas, gemäß Fig. 2, die gleichzeitig ein Abdichten der Gesamtanordnung realisiert. [0021] Die mechanische Verbindungsfestigkeit des Gehäuseanordnung der beiden Teile Chipträgersubstrat (12) und Gehäuseträgersubstrat (13) wird durch ein kombiniertes oder gleichzeitiges Sintern der Glaspassivierung (26) und der metallischen Verdrahtungen aus Leitpasten auf dem Chipträgersubstrat (12) und dem Gehäuseträgersubstrat (13) erreicht werden.The isolation of the individual wirings on the chip carrier substrate (12) and the housing support substrate (13) takes place horizontally via an insulating passivation (26), for example made of glass, according to FIG. 2, which simultaneously realizes a sealing of the overall arrangement. The mechanical connection strength of the housing assembly of the two parts chip carrier substrate (12) and housing support substrate (13) by a combined or simultaneous sintering of the glass passivation (26) and the metallic wiring of conductive pastes on the chip carrier substrate (12) and the housing support substrate (13). be achieved.
[0022] Alternativ kann das Chipträgersubstrat (12) und das Gehäuseträgersubstrat (13) unabhängig vom verwendeten Werkstoffen durch ein Klebeprozess oder Lötprozess mittels elektrisch leitendem Material die Verdrahtungsebene des Chipträgers und der Verdrahtungsebene des Gehäuseträgers verbunden werden.Alternatively, the chip carrier substrate (12) and the housing support substrate (13) regardless of the materials used by a bonding process or soldering process by means of electrically conductive material, the wiring level of the chip carrier and the wiring level of the housing support are connected.
[0023] Der Schutz der Halbleiterchips (10) sowie der Bonddrähte (11) erfolgt durch beliebige Vergußmaterialien, basierend auf Epoxy oder Silikonen mit angepasstem thermischen Ausdehnungskoeffizienten. Auch ist ein Verschluß durch Aufkleben oder Auflöten eines Deckels möglich.The protection of the semiconductor chips (10) and the bonding wires (11) is carried out by any potting materials based on epoxy or silicones with adapted thermal expansion coefficient. Also, a closure by gluing or soldering a lid is possible.
[0024] Im Falle von Strahlungsemittierenden und oder empfangenen Halbleiterchips (10) wird ein optischer Verguß (17) mit niveaugleicher oder gewölbter Form gemäß den geforderten optischen Eigenschaften in die Abstrahlöffnung (18) ausgeführt. Die Form der Abstrahlöffnung (18), welche gleichzeitig den Durchgang der Strahlung ermöglicht, ist beliebig ausführbar und unterliegt ausschließlich den technischen Erfordernissen an die optische Charakteristik der Applikation. Eine direkte Montage von Baugruppen mit optischen Eigenschaften erfolgt über die Verbindung mit dem Gehäuseträgersubstrat (13).In the case of radiation-emitting and or received semiconductor chips (10), an optical encapsulation (17) is executed with level or curved shape according to the required optical properties in the emission opening (18). The shape of the emission opening (18), which simultaneously allows the passage of the radiation, can be carried out in any manner and is subject exclusively to the technical requirements of the optical characteristics of the application. A direct assembly of modules with optical properties via the connection with the housing support substrate (13).
[0025] Bei Verwendung von flexibel ausgestalteten Verdrahtungsträgern (14) ist eine Anpassung an runde oder beliebig gebogene Formen des Kühlmedium (15) problemlos möglich. Auch können unabhängig von der Größe und der Anschlußposition des Gehäuseträgersubstrates (13) mehrere Verdrahtungsebenen im Verdrahtungsträger (14) übereinander angewandt werden, z.B. in starren oder flexiblen Mehrlagen-Leiterplatten, ohne eine Verschlechterung oder anderweitige Beeinflussung des Wärmeableitwiderstandes. [0026] Sollte die konstruktiv bedingte Notwendigkeit bestehen, eine inverse Bestückung auf dem Verdrahtungsträger vorsehen zu müssen, so können die Abmessu ngen des Ch ipträgersu bstrates ( 1 2) g rö ßer als d ie des Gehäuseträgersubstrates (13) gemäß Fig. 3 sein. Dabei wird die Funktion der Verdrahtungsebene des Gehäuseträgersubstrates (20) reduziert auf die mechanische Verbindung zwischen Chipträgersubstrat (12) und Gehäuseträgersubstrat (13) , wobei die elektrische Verbindung nunmehr direkt zwischen der Verdrahtungsebene des Chipträgersubstrates (22) und der Verdrahtungsebene (25) des Verdrahtungsträgers (14) erfolgen kann.When using flexibly configured wiring carriers (14) is an adaptation to round or arbitrarily curved shapes of the cooling medium (15) easily possible. Also, regardless of the size and the terminal position of the Gehäuseträgersubstrates (13) a plurality of wiring levels in the wiring substrate (14) are applied to each other, for example, in rigid or flexible multilayer printed circuit boards, without deterioration or otherwise influencing the Wärmeableitwiderstandes. If the design-related need exist to have to provide an inverse assembly on the wiring substrate, so the Abmessu lengths of Ch ipträgersu bstrates (1 2) g rö ßer than d he of the Gehäuseträgersubstrates (13) as shown in FIG. In this case, the function of the wiring level of the housing carrier substrate (20) is reduced to the mechanical connection between chip carrier substrate (12) and housing carrier substrate (13), wherein the electrical connection now directly between the wiring level of the chip carrier substrate (22) and the wiring level (25) of the wiring substrate ( 14) can take place.
[0027] Auf dem Chipträgersubstrat (12) befindet sich eine metallisierte Fläche zur Montage der Halbchips (10) mittels üblicher Bondverfahren mittels Anwendung von adhesiven Leitmaterialien. Soll eine eutektische Chipbondung durchgeführt werden, ist zur Reduzierung bzw. Vermeidung von Schwimmeffekten die Metallisierung der Chipträgermetallisierung (23) in Abhängigkeit der Chipgrösse in Teilflächen der Chipträgermetallisierung (28) strukturiert. Diese Strukturierung wird so vorgenommen, daß die Halbleiterchips (10) unter Nutzung der Oberflächenspannung des flüssigen Lotes selbstjustierend gelötet werden.On the chip carrier substrate (12) is a metallized surface for mounting the half-chips (10) by means of conventional bonding method by using adhesive Leitmaterialien. If a eutectic chip bonding is to be carried out, the metallization of the chip carrier metallization (23) is structured as a function of the chip size in partial areas of the chip carrier metallization (28) in order to reduce or avoid floating effects. This structuring is carried out in such a way that the semiconductor chips (10) are self-aligned using the surface tension of the liquid solder.
[0028] Fig. 4 zeigt den detaillierten Aufbau einer isolierten Chipträgermetallisierung (23) des Chipträgersubstrates (12) zur Aufnahme der Halbleiterchips (10) in Teilflächen der Chipträgermetallisierung (28). Die Abmessungen der einzelnen Halbleiterchips (10) zuzüglich einer Umrandung ergibt die Größe einer Teilfläche der Chipträgermetallisierung (28), die in Anordnung und Anzahl beliebig ausgeführt werden kann. Verbunden sind die Teilflächen der Chipträgermetallisierung (28) mit elektrisch leitenden Verbindungsstegen und kleinen Bondflächen (29), die bei zweiseitig zu kontaktierenden Halbleiterchips (10) notwendig sind, bei einseitig zu kontaktierenden Bauteilen kann diese Teilfläche und der Steg entfallen, wenn die Kontaktierung von der oberen Seite erfolgt.4 shows the detailed structure of an isolated chip carrier metallization (23) of the chip carrier substrate (12) for receiving the semiconductor chips (10) in partial areas of the chip carrier metallization (28). The dimensions of the individual semiconductor chips (10) plus a border gives the size of a partial area of the chip carrier metallization (28), which can be arbitrarily configured in arrangement and number. Connected are the partial surfaces of the Chipträgermetallisierung (28) with electrically conductive connecting webs and small bonding surfaces (29), which are necessary for bilaterally to be contacted semiconductor chips (10), in one-sided components to be contacted, this part and the web omitted if the contact of the Upper side takes place.
[0029] Bei Strahlungsemittierenden Bauelementen mit einer Chipkonstruktion analog dem Flip-Chip-Prinzip erfolgt die Kontaktierung von der Unterseite. Hier ist die Chipträgermetallisierung (23) in der erforderlichen Anzahl von Teilflächen der Chipträgermetallisierung (28) unterteilt und der Polarität des Strahlungsemittierenden Bauelementes zugeordnet. Die elektrische Verbindung erfolgt analog über elektrisch leitende Verbindungsstege oder bei entsprechender geometrischer Auslegung direkt kleine Bondflächen (29). Gleiches gilt für eine isolierte Montage von Halbleiterchips (10) unterschiedlicher Polarität. In radiation-emitting components with a chip construction analogous to the flip-chip principle, the contact is made from the bottom. Here is the Chip carrier metallization (23) in the required number of faces of Chipträgermetallisierung (28) divided and associated with the polarity of the radiation-emitting device. The electrical connection takes place analogously via electrically conductive connecting webs or with a corresponding geometric design directly small bonding surfaces (29). The same applies to an isolated assembly of semiconductor chips (10) of different polarity.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
1 Leistungsgehäuse für Halbleiterchips1 power housing for semiconductor chips
10 Halbleiterchip10 semiconductor chip
11 Bonddraht11 bonding wire
12 Chipträgersubstrat12 chip carrier substrate
13 Gehäuseträgersubstrat13 housing carrier substrate
14 Verdrahtungsträger (zum Anschluß des Bauteiles)14 wiring carrier (for connecting the component)
15 Kühlmedium15 cooling medium
16 Wärmeleitverbindungsmaterial16 thermal interface material
17 optisches Vergußmaterial17 optical potting material
18 Abstrahlöffnung18 emission opening
20 - Verdrahtungsebene des Gehäuseträgersubstrates20 - wiring level of the Gehäuseträgersubstrates
21 - Öffnung im Verdrahtungsträger21 - opening in the wiring carrier
22 - Verdrahtungsebene des Chipträgersubstrates22 - Wiring plane of the chip carrier substrate
23 - Chipträgermetallisierung23 - Chip carrier metallization
24 - Fixiermaterial24 - fixing material
25 - Verdrahtungsebene des Verdrahtungsträgers25 - Wiring level of the wiring substrate
26 - Isolierende Passivierung26 - Insulating passivation
27 - Metallische Verbindungsebene27 - Metallic connection plane
28 - Teilfläche der Chipträgermetallisierung28 - Part surface of Chipträgermetallisierung
29 - Bondfläche 29 - bond area

Claims

Patentansprüche claims
1. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung dadurch gekennzeichnet, dass dieses mindestens aus zwei elektrisch leitend verbundenen hoch wärmeleitfähigen Substraten, dem Chipträgersubstrat (12) und dem Gehäuseträgersubstrat (13) besteht, wobei das Chipträgersubstrat (12), auf das die Halbleiterchips (10) montiert sind, die direkte thermische Verbindung zum Kühlmedium (15) durch eine Öffnung des Verdrahtungsträgers (21) und das Gehäuseträgersubstrat (13), die elektrische Verbindung zum Verdrahtungsträger (14) realisiert.1. power housing for semiconductor chips (1) and their arrangement for heat dissipation, characterized in that this at least two electrically conductive connected highly thermally conductive substrates, the chip carrier substrate (12) and the housing support substrate (13), wherein the chip carrier substrate (12), on the the semiconductor chips (10) are mounted, the direct thermal connection to the cooling medium (15) through an opening of the wiring substrate (21) and the housing support substrate (13), the electrical connection to the wiring support (14) realized.
2. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung nach Anspruch 1, dadurch gekennzeichnet, dass die2. power housing for semiconductor chips (1) and their arrangement for heat dissipation according to claim 1, characterized in that the
Chipträgermetallisierung (23) zur Montage der Halbleiterchips (10) elektrisch nach außen isoliert ist und die elektrische Verbindung zum Gehäuseträgersubstrat (13) vom Halbleiterchip (10) mittels Bonddrähte (11) auf die Verdrahtungsebene des Chipträgersubstrates (22) über gesinterte oder gelötete oder geklebte sich gegenüberliegende elektrisch leitende Kontaktflächen zur Verdrahtungsebene des Gehäuseträgersubstrates (20) realisiert.Chip carrier metallization (23) for mounting the semiconductor chips (10) is electrically insulated to the outside and the electrical connection to the housing carrier substrate (13) from the semiconductor chip (10) by means of bonding wires (11) on the wiring level of the chip carrier substrate (22) via sintered or soldered or glued realized opposite electrically conductive contact surfaces to the wiring level of the Gehäuseträgersubstrates (20).
3. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung nach Anspruch 1 und 2, dadurch gekennzeichnet, dass das3. power housing for semiconductor chips (1) and their arrangement for heat dissipation according to claim 1 and 2, characterized in that the
Chipträgersubstrat (12) und das Gehäuseträgersubstrat (13) aus keramischen Werkstoffen besteht.Chip carrier substrate (12) and the housing support substrate (13) consists of ceramic materials.
4. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung nach Anspruch 1 und 2, dadurch gekennzeichnet, dass das4. power housing for semiconductor chips (1) and their arrangement for heat dissipation according to claim 1 and 2, characterized in that the
Chipträgersubstrat (12) aus Silizium mit rückseitig lötbarer Metallisierung und oberseitig mit aufgebrachtem Siliziumdioxid als Isolierung und darauf aufgebrachter Metallisierung versehen besteht und das Gehäuseträgersubstrat (13) aus keramischen Werkstoffen besteht. Chip carrier substrate (12) made of silicon with back solderable metallization and on the top with applied silicon dioxide as insulation and metallization applied thereto and the housing support substrate (13) consists of ceramic materials.
5. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung nach Anspruch 4, dadurch gekennzeichnet, dass das5. power housing for semiconductor chips (1) and their arrangement for heat dissipation according to claim 4, characterized in that the
Chipträgersubstrat (12) entweder aus Silizium oder keramischen Werkstoffen besteht und das Gehäuseträgersubstrat (13) aus mit Leiterbahnen versehenen Laminatwerkstoffen besteht.Chip carrier substrate (12) consists of either silicon or ceramic materials and the housing support substrate (13) consists of conductor tracks provided with laminate materials.
6. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung nach Anspruch 1 bis 5, dadurch gekennzeichnet, dass die6. power housing for semiconductor chips (1) and their arrangement for heat dissipation according to claim 1 to 5, characterized in that the
Chipträgermetallisierung (23) zur Montage mehrerer Halbleiterchips (10) in eine der Abmessungen der einzelnen Halbleiterchips (10) angepassten Teilflächen der Chipträgermetallisierung (28) unterteilt sein kann.Chip carrier metallization (23) for mounting a plurality of semiconductor chips (10) in one of the dimensions of the individual semiconductor chips (10) adapted partial surfaces of the Chipträgermetallisierung (28) may be divided.
7. Leistungsgehäuse für Halbleiterchips (1) und deren Anordnung zur Wärmeableitung nach Ansprüchen 1 bis 6, dadurch gekennzeichnet, dass das Chipträgersubstrat (12) mit dem Kühlmedium (15) zusätzlich über ein Wärmeleitverbindungsmaterial (16) verbunden sein kann, wobei die Verbindung durch bleifreie Lötung entstanden ist. 7. power housing for semiconductor chips (1) and their arrangement for heat dissipation according to claims 1 to 6, characterized in that the chip carrier substrate (12) may be additionally connected to the cooling medium (15) via a Wärmeleitverbindungsmaterial (16), wherein the compound by lead-free Soldering has arisen.
EP06804809A 2005-10-20 2006-10-17 Power housing for semiconductor chips and the arrangement thereof for heat dissipation Withdrawn EP2033219A1 (en)

Applications Claiming Priority (2)

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CH16852005 2005-10-20
PCT/CH2006/000574 WO2007045112A1 (en) 2005-10-20 2006-10-17 Power housing for semiconductor chips and the arrangement thereof for heat dissipation

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EP2033219A1 true EP2033219A1 (en) 2009-03-11

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WO (1) WO2007045112A1 (en)

Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
US8354684B2 (en) * 2011-01-09 2013-01-15 Bridgelux, Inc. Packaging photon building blocks having only top side connections in an interconnect structure
US8652860B2 (en) 2011-01-09 2014-02-18 Bridgelux, Inc. Packaging photon building blocks having only top side connections in a molded interconnect structure
EP3340293A1 (en) * 2016-12-20 2018-06-27 Siemens Aktiengesellschaft Semiconductor module with support structure on the bottom
DE102018208256A1 (en) * 2018-05-25 2019-11-28 Volkswagen Aktiengesellschaft Power component and method of manufacturing the same
CN109671812A (en) * 2018-12-25 2019-04-23 江苏罗化新材料有限公司 A kind of heat sinking type chip grade LED encapsulation method and its encapsulating structure

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Publication number Priority date Publication date Assignee Title
JPH0378247A (en) * 1989-08-22 1991-04-03 Oki Electric Ind Co Ltd Semiconductor chip heat radiation mounting structure
JP2541494B2 (en) * 1993-12-15 1996-10-09 日本電気株式会社 Semiconductor device
WO2001073843A1 (en) * 2000-03-29 2001-10-04 Rohm Co., Ltd. Semiconductor device
DE10117889A1 (en) 2001-04-10 2002-10-24 Osram Opto Semiconductors Gmbh Leadframe used for a light emitting diode component comprises a chip assembly region, a wire connecting region, external electrical connecting strips, and a support part coupled with a thermal connecting part
US20040226688A1 (en) * 2003-04-30 2004-11-18 Arthur Fong Application specific apparatus for dissipating heat from multiple electronic components

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WO2007045112A1 (en) 2007-04-26

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