Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
  • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around

Definitions

• the invention relates to a transistor comprising at least one channel embedded by a gate electrode, and source and drain electrodes each consisting of alternating first layers based on silicon and second layers made of germanium and silicon compound.
• DG double gate
• GAA gate-all-around
• the "5nm-Gate Nanowire FinFET” article by F. L. Yang and Al. (2004 Symposium on VLSI Technology) describes a transistor having a cylindrical channel completely surrounded by the gate. This transistor has a very good electrostatic control of the channel by the gate, which makes it possible to produce a transistor having a gate length as small as 5 nm.
• germanium transistors As for the materials used, pure germanium has a mobility twice as high for electrons and four times higher for holes than silicon.
• the disadvantage of germanium transistors is the cost of the substrate which is about 10 times higher than that of a solid silicon substrate.
• it is very difficult to stack several germanium channels by epitaxial germanium of good quality on a silicon substrate.
• the manufacture of these transistors requires many developments due to the instability of the germanium oxide.
• US2003 / 0215989 discloses a transistor having a channel embedded by a gate electrode.
• the channel is constituted by the central part of a silicon layer.
• An SiGe layer is removed in the area below the channel to free the space for the gate electrode.
• the source and drain electrodes correspond to the zones disposed on either side of the channel.
• the source and the drain are formed by ion implantation in active layers.
• the source and drain electrodes each consist of alternating first and second layers.
• the first layers are silicon.
• the second layers have a germanium concentration of between 20% and 30%.
• the channel connects two first silicon layers of the stack constituting the source and drain electrodes.
• the object of the invention is to propose a transistor that makes it possible to obtain a very high integration density and a large amount of current, while using standard methods, in particular methods for integrating transistors onto silicon.
• the channel is based on germanium, the first layers being composed of germanium and silicon with a germanium concentration of between 0% and 10% and second layers having a germanium concentration between 10% and 50%, the channel connecting two second layers respectively source and drain electrodes.
• the invention also aims at a method of manufacturing a transistor, comprising successively: the production, on a substrate, of an alternation of first and second layers of germanium and silicon compound, the first layers having a concentration of germanium between 0% and 10% and the second layers having a germanium concentration of between 10% and 50%, the etching, in said stack, of source and drain zones intended to constitute the source and drain electrodes and a narrow zone connecting the source and drain zones, the surface thermal oxidation of said stack, so as to oxidize, in the narrow zone, the silicon of the germanium and silicon compound having a germanium concentration of between 10% and
• Figures 1 to 3 show, respectively in top view, in section along the axis B-B, and in section along the axis AA, a particular embodiment of a transistor according to the invention.
• FIGS. 4 to 6, 7 to 9, 10 to 12 and 13 to 15 respectively represent four steps of a particular embodiment of a method of manufacturing a transistor according to the invention, respectively in plan view, in section along the BB axis and in section along the axis AA.
• a transistor comprises two channels 1 coated with a gate electrode 2.
• the channels 1 are based on germanium.
• the transistor has electrodes source 3 and drain 4 which are each constituted by an alternation of first (5) and second (6) layers composed of germanium and silicon.
• the first layers 5 have a germanium concentration of between 0% and 10% and the second layers 6 have a germanium concentration between 10% and 50%.
• the first layers 5 are, for example, silicon. All second layers 6 may have the same concentration of germanium.
• the first layers 5 are in Si and the second layers 6 in SiGe x , so as to obtain a SiGe type stack x / Si / SiGe x / Si.
• Second layers 6 may also have different germanium concentrations.
• the second layers 6 are respectively SiGe x , SiGe y and SiGe 2 and the first layers 5 are Si, so as to obtain a SiGe type stack x / Si / SiGe y / Si / SiGe z / Si.
• the first layers 5 are not necessarily silicon.
• the first layers 5 also comprise germanium, so as to obtain a stack of type
• the first layers having a germanium concentration of less than 10% and the second layers having a germanium concentration between 10% and 50%.
• the upper layer of the stack of layers 5 and 6 is preferably a first silicon layer.
• the first and / or second layers (5, 6) can be doped during their growth by injection of precursors such as diborane, phosphine, arsine.
• Each channel connects two second layers 6 of SiGe respectively source 3 and drain 4 electrodes.
• the channels 1 are separated from the gate electrode 2 by a dielectric 7 of wire rack.
• the sources 3 and drain 4 are preferably separated from the gate electrode 2 by spacers 15 and by the gate dielectric.
• a portion of the first layers 5 disposed opposite the channel 1 is oxidized, before deposition of the gate dielectric 7, so as to make the spacers 15 between the first layers 5 of the source 3 and drain 4 and the gate electrode 2.
• the upper channel 1 connects the second upper layer 6a of the source electrode 3 to the second upper layer 6b of the drain electrode 4.
• the layers 5 and 6 are formed in parallel on a substrate 8.
• second upper layer 6a is disposed at a predetermined level of alternating layers of the source electrode 3 and also at a predetermined level with respect to the substrate 8.
• the corresponding second upper layer 6b of the drain 4 is disposed at a predetermined level of the alternating layers of the drain electrode 4 and also at a predetermined level with respect to the substrate 8.
• the second upper layers 6a and 6b corresponding to the same channel 1 are thus at the same level.
• the two second layers 6 connected by a channel 1 and the channel 1 are arranged in the same plane parallel to the substrate 8, as represented by the axis C-C.
• the gate electrode 2 completely surrounds the channel 1.
• a method of manufacturing a transistor according to the invention comprises producing, on the substrate 8, a stack of alternating layers 5 and 6 respectively in Si and SiGe 1 as shown in FIGS. 4 to 6.
• the stack is carried out, for example, by SiGe / Si heteroepitaxy on a silicon-on-insulator ("SOI: silicon on insulator") substrate.
• SOI silicon on insulator
• the thickness of the second SiGe layers 6 is preferably between 5 nanometers and 30 nanometers.
• the thicknesses of the first and second layers 5 and 6 are, for example, each of the order of ten nanometers.
• the germanium concentration of the second layers is preferably 30%.
• the number of second SiGe layers 6 determines the number of germanium-based channels 1 formed by the method.
• the stack of alternate layers 5 and 6 may be protected by a protective layer (not shown), for example a silicon nitride layer, to protect the outer faces of the stack against subsequent oxidation.
• a protective layer for example a silicon nitride layer, to protect the outer faces of the stack against subsequent oxidation.
• etching in said stack, a source zone 9 and a drain zone 10, designed respectively to constitute the source 3 and drain 4 electrodes, and a narrow zone 11 connecting the zone from source 9 to the drain zone 10.
• Said zones (9, 10 and 11) are delimited, for example, by deposition of a resin, lithography (for example photo-lithography or electronic lithography) of the resin, anisotropic plasma etching stacking layers 5 and 6 and removing the resin.
• the alternations of layers 5 and 6 constituting the source 3 and drain 4 electrodes are formed in the same stack of layers 5 and 6.
• the narrow zone 11 corresponds to the location of the channels 1 which are formed later.
• the narrow zone 11 has lateral dimensions of between 3 and 50 nanometers and longitudinal dimensions greater than 5 nanometers and can reach micrometric dimensions.
• FIGS. 10 to 12 a superficial thermal oxidation of said stack, shown in FIGS. 10 to 12, is carried out.
• the oxygen enters the stack of layers to a predetermined depth represented by a dotted line 12 in FIG. 10.
• the interior of the electrodes source 3 and drain 4 is not oxidized during thermal oxidation.
• the silicon of the narrow zone 11 is completely oxidized during thermal oxidation.
• all of the silicon of the part of the layers 5 and 6 corresponding to the narrow zone 11, that is to say the silicon of the Si layers 5 and the silicon of the SiGe layers 6, are oxidized.
• the germanium of the SiGe is thus condensed inside the portions of the layers 6 corresponding to the narrow zone 11 and concentrated, on a central axis of the layers 6 connecting the source 3 and the drain 4, so as to forming the channels 1 based on germanium, while the silicon forms an oxide 13 on the surface of the channel 1 based on germanium.
• the dimensions of the germanium-based channels are determined by the lateral and longitudinal dimensions of the narrow zone 11 and by the thicknesses of the second SiGe layers 6 as well as by the initial germanium concentration of the SiGe.
• the portions of the first silicon layers 5 corresponding to the narrow zone 11 are completely converted to silicon oxide 13.
• a surface oxide layer 14 is disposed on the walls of the source 3 and drain 4 electrodes.
• germanium condensation that is to say the increase in germanium concentration of a SiGe silicon and germanium compound when it is subjected to an oxidizing treatment, is usually used for the production of substrates of the type germanium on insulator.
• the narrow zone 11 is oxidized laterally, by its two sides, the condensation of the germanium automatically results in substantially cylindrical channels, as shown in FIGS. 12, 15 and 3.
• the cylindrical shape of the channels makes it possible in particular to later obtain a very good electrostatic control of the channel through the grid.
• the silicon oxide 13 of the narrow zone 11 is eliminated, so as to release the channels 1.
• the elimination of the silicon oxide 13 may be accompanied by a selective etching of residual silicon of the narrow zone 11 arranged between the channels 1, when the previous thermal oxidation is carried out so as to only partially oxidize the silicon of the first layers 5 of the narrow zone 11.
• the silicon of the first layers 5 may oxidize less rapidly than SiGe.
• the channels 1 are thus released completely via the selective etching of the residual silicon (not shown).
• a layer of doped silicon is deposited during epitaxial steps.
• additional thermal oxidation is performed to reduce the parasitic capacitances of the transistor.
• all the materials discovered undergo oxidation, in particular silicon and germanium-based channels.
• a step of producing the spacers 15 is carried out by oxidation (for example thermal or plasma) followed by a selective dissolution of the oxide of germanium in the water.
• the gate dielectric 7 (for example a material based on Hf 1 Si, O or N, for example HfO 2, HfSiON or a material such as LaAlO 3) is deposited on the condensed germanium constituting the channels 1, in order to coat the channels 1.
• the gate dielectric 7 is also deposited on the source 3 and the drain 4, as represented in FIG. 2.
• a gate material for example a metal (for example TiN, WSi, TaN) or a semiconductor (for example polycrystalline silicon, polycrystalline germanium, SiGe), is deposited on the gate dielectric 7, so as to coat the together the channels 1 and the dielectric 7 and, thus, form a coating grid 2, as shown in Figures 2 and 3.
• the grid 2 is made, for example, by depositing a metal layer on the entire stack of layers 5 and 6 and channels 1, followed by a resin deposit, the photolithography of the resin, the anisotropic etching of the metal layer and the removal of the resin.
• the grid 2 is delimited so as to fill the space between the channels 1 and so as to completely cover the narrow zone 11 as well as the adjacent part of the source 3 and drain 4 electrodes, as represented in FIG. 2.
• the dimensions of the grid 2 correspond in particular to the lateral and longitudinal dimensions of the channels 1, to which is added the alignment tolerance of the lithography tool used, typically 20nm for the electron jet apparatus and 60nm for the apparatus of the type photolithography, for example UV, deep UV or extreme UV.
• the gate dielectric 7 on the germanium constituting the channels 1 Before the deposition of the gate dielectric 7 on the germanium constituting the channels 1, it is possible, in known manner, to selectively doping the two zones 9 and 10 intended to constitute the source 3 and drain 4 electrodes.
• the selective doping can for example, be performed via ion implantation.
• the energies of the ions can be chosen so as to dope the source 3 and the drain 4 whereas the channels 1 are simply crossed by the ions without being doped.
• the number of channels may be greater than or less than two.
• Several channels arranged one above the other in particular allow to obtain a better integration density.
• Various standard steps can be added to the production methods, for example the production of spacers, doping steps of the source and drain zones or siliciding of the source and drain zones.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Thin Film Transistor (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 2005
  • 2005-06-06 FR FR0505700A patent/FR2886761B1/fr active Active
• 2006
  • 2006-05-23 JP JP2008515240A patent/JP2008543103A/ja active Pending
  • 2006-05-23 EP EP06764670A patent/EP1889296A1/de not_active Withdrawn
  • 2006-05-23 US US11/920,835 patent/US7829916B2/en active Active
  • 2006-05-23 WO PCT/FR2006/001177 patent/WO2006131615A1/fr not_active Application Discontinuation

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