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EP1864275B1 - Image display device and method of controlling same - Google Patents

Image display device and method of controlling same Download PDF

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Publication number
EP1864275B1
EP1864275B1 EP06709267A EP06709267A EP1864275B1 EP 1864275 B1 EP1864275 B1 EP 1864275B1 EP 06709267 A EP06709267 A EP 06709267A EP 06709267 A EP06709267 A EP 06709267A EP 1864275 B1 EP1864275 B1 EP 1864275B1
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EP
European Patent Office
Prior art keywords
emitters
selection
voltage
electrode
modulator
Prior art date
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Active
Application number
EP06709267A
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German (de)
French (fr)
Other versions
EP1864275A1 (en
Inventor
Arnaud Trochet
Sylvain Thiebaud
Philippe Leroy
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THOMSON LICENSING
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Thomson Licensing SAS
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Publication of EP1864275A1 publication Critical patent/EP1864275A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • An OLED (Organic Light Emitting Diode) active matrix display device comprises light emitters formed from organic electroluminescent cells.
  • such a device For the control of these emitters, such a device comprises thin film transistors, called TFT (Thin Film Transistor) transistors. These transistors are able to control the current flowing through the emitters. They are made of polycrystalline silicon, for example using low temperature amorphous silicon (LTPS) crystallization technology, or directly in amorphous silicon.
  • TFT Thin Film Transistor
  • the TFT manufacturing technology introduces local spatial variations in the trigger threshold voltage of these transistors.
  • TFT transistors fed by the same supply voltage and controlled by identical voltages generate currents of different intensities which result in a non-uniform brightness of the display device comprising such transistors.
  • spatial variations in the luminance of the pixels of the display device and a visible visual discomfort for the user.
  • the instability of the amorphous silicon results in a variation of the characteristics of the TFT when a voltage is applied between the gate and the source of the TFT. More particularly, the triggering threshold voltage of the TFT transistors increases when a positive polarity voltage is applied. is applied their gate and their source and decreases when a negative polarity voltage is applied between their gate and their source. Since the voltage applied between the gate and the source of the transistors generally differs from one transistor to the other according to the luminance deviations of the pixels of an image to be displayed, the degree of fluctuation of the trigger threshold voltage differs from one transistor to another. As a result, the resulting luminance variation is unevenly distributed on the display device, resulting in changes over time in the luminance of the display pixels and obvious visual discomfort for the display. 'user.
  • the document US 2003/0052614 discloses an image display device of the aforementioned type.
  • This device comprises in particular, for each transmitter column, a control switch controlled by an electrode control to move this switch between a connection position to a reverse bias generator and a connection position to a column driving unit.
  • the inverse polarization generator is able to apply between the gate and the source of the modulators associated with the emitters of a column, a reverse bias voltage during so-called modulator regeneration phases, adapted to compensate for the drifts of their threshold voltage. trigger.
  • This reverse bias voltage has a polarity inverse to the polarity of the addressing voltages applied between the gate and the source of these same modulators during illumination phases of the transmitters.
  • the device described in the document US2003 / 0112205 does not allow to apply a reverse bias voltage between the gate and the source of the modulators associated with the transmitters of the same line: indeed, in this document, when a reverse bias is applied (see paragraph 44), is at the terminals of the transmitters (see for example the last sentence of paragraph 44) and not between the gate and the source of the modulators; indeed, during the phases of inverse polarization in question here, the gate and the source of the modulators are brought to the same potential by the simultaneous closing of the referenced switches Tr3 and Tr4, and there is no polarization, inverse or no, between the gate and the source.
  • An object of the invention is in particular to provide an alternative display device adapted to compensate for the variations over time of the trigger threshold voltages.
  • this device divides by two the number of line electrodes contained in the device.
  • the emitters 2, 4, 6, 8 are organic light emitting diodes. They include an anode and a cathode. They emit a luminous intensity directly proportional to the current passing through them. Each transmitter constitutes an elementary pixel of the display device.
  • the display device further comprises addressing circuits 18, 20, 22, 24 distributed along a network.
  • Each addressing circuit is connected to a transmitter 2, 4, 6, 8 to drive it.
  • Addressing circuits 18, 22; 20, 24 of each column of emitters 14, 16 are addressed via an addressing electrode 26, 28 of this column of emitters.
  • Each addressing electrode 26, 28 is connected to a column driver unit 30 (in English: column driver).
  • the control unit 30 is able to receive an image display signal and to transmit simultaneously to each addressing electrode 26, 28 of a column, an address voltage V data representative of a data item. display of a transmitter to be addressed in this column.
  • Addressing circuits 18, 20; 22, 24 of each emitter line 10, 12 are selected via a selection electrode 32, 34, each connected to a selection control unit 33, 35.
  • the selection control unit 33, 35 of a line of transmitters 10, 12 is adapted to generate at a preset frequency, a selection signal V 32 , V 34 at the selection electrode 32, 34 of this line 10, 12 to select all transmitters 2, 4 and 6, 8 of this line 10, 12.
  • This selection signal comprises a series of pulses each generated at each new image frame. These pulses are logical data for selecting a transmitter of a line of transmitters.
  • This circuit 18 comprises a current modulator 36, a selection switch 38, a storage capacitor 40 (referenced 41 in the addressing circuit 28 of the second emitter line 12) and two power supply electrodes 42, 44.
  • the current modulator 36 and the switch 38 are thin film transistors (in English: Thin Film Transistor), based on a technology using polycrystalline silicon (Poly-Si), amorphous silicon (a-Si) or silicon microcrystalline (micro-Si) deposited in thin layers on a glass substrate.
  • Such components comprise three electrodes: a drain electrode and a source electrode between which circulates a modulated current called drain current, and a gate electrode.
  • the modulator 36 shown on the Fig.1 is of type N, so that, in operation, its drain current flows from its drain to its source. It will be noted that the device according to the invention can also be used to drive P-type TFT transistors.
  • the capacitor 40 is able to store electrical charges to maintain a voltage at the gate of the modulator 36 after the transmission of an addressing voltage.
  • the capacitor 40 comprises a first terminal 40a connected to the gate of the modulator 36 and a second terminal 40b connected to a reverse bias electrode 52.
  • the display device 1 further comprises, for each line of emitters 10, 12, a reverse bias generator 46, 48 connected to a reverse bias electrode 52, 54 and a reverse bias control generator 53, 55 connected to a reverse bias control electrode 56, 58.
  • the inverse polarization generators 46 and 48 are able to generate, each between the gate and the source of the modulators 36, a bias voltage V p of values possibly different from each other and of polarity opposite to the polarity of the addressing voltages V. data applied between the gate and the source of the modulators 36 during the transmission phases of the transmitters 2, 4, 6, 8.
  • the reverse bias control generators 53, 55 are adapted to produce a reverse bias control signal V 56 , V 58 , similar to the selection signal V 32 , V 34 , of the same frequency and shifted by half a period or variable period with respect to this selection signal.
  • the device 1 further comprises a reverse bias switch 59 in each addressing circuit 18, 20, 22, 24.
  • a current-passing electrode (source or drain) of the switch 59 of each addressing circuit of an emitter line 10, 12 is connected to the inverse bias electrode 52, 54 of this emitter line. 10, 12, and therefore also to the second terminal 40b of the capacitor 40, 41.
  • the other current-passing electrode (source or drain) of the switch 59 is connected to the gate of the modulator 36, and consequently, also at the first terminal 40a of the capacitor 40, 41.
  • the gate of the switch 59 of each addressing circuit of an emitter line 10, 12 is connected to the reverse bias control electrode 56, 58 of this same emitter line 10, 12.
  • a pulse of the selection signal V 32 represented on the Fig.2 is generated at the selection electrode 32 of the first line of transmitters 10.
  • the control unit 30 addresses an address voltage V data2 to the addressing electrode 26.
  • the value of this voltage d The addressing is referenced to the constant potential of the supply electrode 44.
  • the switches 38 of the first line of emitters 10 close and the voltage V data2 is applied to the first terminal 40a of the capacitor 40 and between the gate and the source of the modulator 36 of the addressing circuit 18, as visible on the Fig.6 .
  • the switches 38 of the first line of emitters 10 open and the voltage V data2 is maintained, thanks to the capacitor 40, between the gate and the source of the modulator 36 of the addressing circuit 18, as visible on the Fig.6 .
  • a pulse of the selection signal V 34 represented on the Fig.4 is applied to the selection electrode 34.
  • the control unit 30 addresses an address voltage V data6 to the addressing electrode 26.
  • the value of this addressing voltage is also referenced to the constant potential. of the supply electrode 44.
  • This pulse closes the switches 59 of the first emitter line 10, so that the reverse bias voltage V p generated by the generator 46 is applied between the gate and the source of the modulator 36 of the addressing circuit 18; as the switch 59 then bypasses the two terminals of the capacitor 40, this capacitor is discharged.
  • the switches 59 of the first line of emitters 10 open and the voltage V P is maintained between the gate and the source of the modulator 36 of the addressing circuit 18 , as visible on the Fig.6 because the capacitor 40 keeps a zero charge.
  • a pulse of the selection signal V 32 represented on the Fig.2 is applied to the selection electrode 32.
  • the control unit 30 addresses a new address voltage to the addressing electrode 26.
  • the duration of T0 to T4 corresponds to the duration of an image frame.
  • the duration of an image frame is divided into two phases, here T0 to T2 and T2 to T4, for example of a duration each equal to the duration of half a frame of image.
  • the ratio of the durations between the first phase and the second phase is 50/50.
  • the ratio of the durations between the first phase and the second phase is 60/40 or 70/30.
  • the V data addressing voltages of display data applied between the gate and the source of the modulators 36 connected to these transmitters are adapted to vary the tripping threshold voltages of the modulators. 36 in a first sense.
  • the inverse bias voltages V p are applied between the gate and the source of the modulators 36 connected to these emitters in order to vary their trigger threshold voltage in the opposite direction so as to compensate for the possible drift of this threshold voltage.
  • V p As the reverse bias voltages V p represented on the Fig. 6 and 7 , have a polarity inverse to the polarity of the addressing voltages V data2 , V data6 previously applied to the modulators 36, they are suitable for reducing the triggering threshold voltage of the modulators 36 in order to bring it back to their threshold voltage. initial trip (before application of the addressing voltage).
  • Part of a display device 60 according to a second embodiment of the invention is schematically illustrated on the Fig.8 .
  • the circuit 66 is identical to the circuits 18, 20, 22, 24. It comprises a referenced capacitor 76 having a first 76a and a second 76b terminals, and a reverse bias electrode referenced 69 similar to the electrodes 52 and 54 and connected to the second terminal 76b of the capacitor 76 and a current-pass electrode of the switch 59.
  • the generators 80, 82, 84, 86 are able to produce a control signal V 70 , V 71 , V 72 , V 74 of the same frequency. As visible on Figures 9 to 12 the control signals V 70 , V 71 applied to the electrodes of two adjacent lines 10, 12 are shifted by half a picture period.
  • the addressing voltage V data2 as represented on the Fig.13 is applied to the gate of the modulator 36 and the terminals of the capacitor 40 of the first emitter line 10 and the emitter 2 is illuminated.
  • a pulse of the control signal V 72 shown in FIG. Fig.11 it is applied to the control electrode 72. This causes the closing of the reverse bias switches 59 of the second line of emitters 12 and the closing of the selector switches 38 of the third line of emitters 61. switch 59 then bypasses the two terminals of the capacitor 41, this capacitor is discharged.
  • the switches 59 of the second line of emitters 12 open and the voltage V p is maintained between the gate and the source of the modulator 36 of the addressing circuit 22, as visible on the Fig.14 because the capacitor 41 maintains a zero charge.
  • an address voltage V data-62 is transmitted by the electrode 26, and applied to the gate of the modulator 36 and a terminal of the capacitor 76 of the third emitter line 61. Accordingly, the emitter 62 is illuminated.
  • the emitters of a group comprising the odd lines 10, 61 of the device are extinguished during a first frame T0-T2; T1-T3, then illuminated during a second T2-T4 frame; T3-T5.
  • the transmitters of another group comprising the even lines 12, 68 of the device are illuminated during a first frame T0-T2; T1-T3 then extinguished during a second T2-T4 frame; T3-T5.
  • the transmitters of a line are addressed on all the columns simultaneously, for all the even lines in a first frame, and then for the set odd lines in a second frame.
  • this second embodiment of the invention makes it possible to reduce the number of line electrodes because the control electrodes 70, 71, 72, 74 make it possible to control both the addressing of the addressing voltages and the addressing reverse bias voltages.
  • the reverse biasing electrodes 52, 54, 69 of the entire display device are connected to a single reverse bias voltage generator.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Description

La présente invention concerne un dispositif d'affichage d'images à matrice active comprenant ;

  1. a) plusieurs émetteurs de lumière formant un réseau, répartis en lignes et en colonnes ;
  2. b) des moyens d'alimentation en puissance des émetteurs ;
  3. c) des moyens de commande des émetteurs comportant :
    • un modulateur de courant pour chaque émetteur, le modulateur comportant une électrode source, une électrode de drain, une électrode de grille, le modulateur étant apte à être traversé par un courant de drain, pour alimenter ledit émetteur pour une tension entre l'électrode de source et l'électrode de grille, supérieure ou égale à une tension de seuil de déclenchement de ce modulateur ;
    • un condensateur de stockage pour chaque émetteur, ledit condensateur comportant une première et une seconde bornes et étant apte à stocker des charges électriques à l'électrode de grille de chaque modulateur ;
    • des moyens d'adressage aptes à adresser des données d'affichage aux émetteurs de chaque colonne ;
    • des moyens de sélection aptes à sélectionner les émetteurs de chaque ligne, les moyens de sélection comprenant un interrupteur de sélection pour chaque émetteur, l'interrupteur de sélection étant propre à permettre d'appliquer entre l'électrode de grille et l'électrode de source de chaque modulateur une donnée d'adressage fournie par les moyens d'adressage ; et
  4. d) au moins un générateur de tension de polarisation inverse propre à appliquer une tension de polarisation inverse de la polarisation desdites donnée d'adressage entre l'électrode de grille et l'électrode de source de chaque modulateur pour compenser la variation de la tension de seuil de déclenchement de chaque modulateur.
The present invention relates to an active matrix image display device comprising;
  1. a) several light emitters forming a network, divided into rows and columns;
  2. b) power supply means for the emitters;
  3. c) transmitter control means comprising:
    • a current modulator for each emitter, the modulator comprising a source electrode, a drain electrode, a gate electrode, the modulator being able to be traversed by a drain current, for supplying said emitter for a voltage between the electrode of source and gate electrode, greater than or equal to a trigger threshold voltage of this modulator;
    • a storage capacitor for each transmitter, said capacitor having first and second terminals and being adapted to store electrical charges at the gate electrode of each modulator;
    • addressing means adapted to address display data to the transmitters of each column;
    • selection means adapted to select the transmitters of each line, the selection means comprising a selection switch for each transmitter, the selection switch being adapted to allow to apply between the gate electrode and the source electrode of each modulator an addressing data provided by the addressing means; and
  4. d) at least one reverse bias voltage generator adapted to apply a polarization reverse bias voltage of said address data between the gate electrode and the source electrode of each modulator to compensate for the variation of the voltage of the tripping threshold of each modulator.

Un dispositif d'affichage à matrice active de type OLED (Organic Light Emitting Diode) comprend des émetteurs de lumière formés à partir de cellules organiques électroluminescentes.An OLED (Organic Light Emitting Diode) active matrix display device comprises light emitters formed from organic electroluminescent cells.

Pour la commande de ces émetteurs, un tel dispositif comporte des transistors à couches minces, appelés transistors TFT (Thin Film Transistor). Ces transistors sont aptes à piloter le courant traversant les émetteurs. Ils sont fabriqués en silicium poly-cristallin, par exemple selon la technologie de cristallisation de silicium amorphe à basse température (LTPS), ou directement en silicium amorphe.For the control of these emitters, such a device comprises thin film transistors, called TFT (Thin Film Transistor) transistors. These transistors are able to control the current flowing through the emitters. They are made of polycrystalline silicon, for example using low temperature amorphous silicon (LTPS) crystallization technology, or directly in amorphous silicon.

Cependant, la technologie de fabrication des TFT introduit des variations spatiales locales de la tension de seuil de déclenchement de ces transistors.However, the TFT manufacturing technology introduces local spatial variations in the trigger threshold voltage of these transistors.

En conséquence, les transistors TFT alimentés par la même tension d'alimentation et commandés par des tensions identiques génèrent des courants d'intensités différentes qui entraînent une non uniformité de la brillance du dispositif d'affichage comprenant de tels transistors. Il en résulte, pour un objet donné de luminance homogène d'une image à afficher, des variations spatiales de la luminance des pixels du dispositif d'affichage et un inconfort visuel manifeste pour l'utilisateur.As a result, TFT transistors fed by the same supply voltage and controlled by identical voltages generate currents of different intensities which result in a non-uniform brightness of the display device comprising such transistors. As a result, for a given object of homogeneous luminance of an image to be displayed, spatial variations in the luminance of the pixels of the display device and a visible visual discomfort for the user.

L'instabilité du silicium amorphe se traduit par une variation des caractéristiques du TFT lorsque qu'une tension est appliquée entre la grille et la source du TFT plus particulièrement, la tension de seuil de déclenchement des transistors TFT augmente lorsqu'une tension de polarité positive est appliquée leur grille et leur source et diminue lorsqu'une tension de polarité négative est appliquée entre leur grille et leur source. Comme la tension appliquée entre la grille et la source des transistors diffère généralement d'un transistor à l'autre selon les écarts de luminance des pixels d'une image à afficher, le degré de fluctuation de la tension de seuil de déclenchement diffère d'un transistor à l'autre. En conséquence, la variation de luminance qui en découle, est répartie de façon inhomogène sur le dispositif d'affichage, et il en résulte des variations au cours du temps de la luminance des pixels du dispositif d'affichage et un inconfort visuel manifeste pour l'utilisateur.The instability of the amorphous silicon results in a variation of the characteristics of the TFT when a voltage is applied between the gate and the source of the TFT. More particularly, the triggering threshold voltage of the TFT transistors increases when a positive polarity voltage is applied. is applied their gate and their source and decreases when a negative polarity voltage is applied between their gate and their source. Since the voltage applied between the gate and the source of the transistors generally differs from one transistor to the other according to the luminance deviations of the pixels of an image to be displayed, the degree of fluctuation of the trigger threshold voltage differs from one transistor to another. As a result, the resulting luminance variation is unevenly distributed on the display device, resulting in changes over time in the luminance of the display pixels and obvious visual discomfort for the display. 'user.

Afin de limiter ces inconvénients, divers circuits de compensation de la dérive de tension de seuil de déclenchement, ont été proposés.In order to limit these disadvantages, various compensation circuits for the trigger threshold voltage drift have been proposed.

Par exemple le document US 2003/0052614 décrit un dispositif d'affichage d'images du type précité. Ce dispositif comprend notamment, pour chaque colonne d'émetteur, un interrupteur de commande piloté par une électrode de commande pour déplacer cet interrupteur entre une position de raccordement à un générateur de polarisation inverse et une position de raccordement à une unité de pilotage de colonne.For example the document US 2003/0052614 discloses an image display device of the aforementioned type. This device comprises in particular, for each transmitter column, a control switch controlled by an electrode control to move this switch between a connection position to a reverse bias generator and a connection position to a column driving unit.

Le générateur de polarisation inverse est propre à appliquer entre la grille et la source des modulateurs associés aux émetteurs d'une colonne, une tension de polarisation inverse pendant des phases dites de régénération des modulateurs, adaptée pour compenser les dérives de leur tension de seuil de déclenchement. Cette tension de polarisation inverse présente une polarité inverse à la polarité des tensions d'adressage appliquées entre la grille et la source de ces mêmes modulateurs pendant des phases d'illumination des émetteurs.The inverse polarization generator is able to apply between the gate and the source of the modulators associated with the emitters of a column, a reverse bias voltage during so-called modulator regeneration phases, adapted to compensate for the drifts of their threshold voltage. trigger. This reverse bias voltage has a polarity inverse to the polarity of the addressing voltages applied between the gate and the source of these same modulators during illumination phases of the transmitters.

A noter que le dispositif décrit dans le document US2003/0112205 ne permet pas d'appliquer une tension de polarisation inverse entre la grille et la source des modulateurs associés aux émetteurs d'une même ligne : en effet, dans ce document, lorsqu'une polarisation inverse est appliquée (voir paragraphe 44), c'est aux bornes des émetteurs (voir par exemple dernière phrase du paragraphe 44) et non pas entre la grille et la source des modulateurs ; en effet, pendant les phases de polarisation inverse dont il s'agit ici, la grille et la source des modulateurs sont portées au même potentiel par la fermeture simultanée des interrupteurs référencés Tr3 et Tr4, et il n'y a aucune polarisation, inverse ou non, entre la grille et la source.Note that the device described in the document US2003 / 0112205 does not allow to apply a reverse bias voltage between the gate and the source of the modulators associated with the transmitters of the same line: indeed, in this document, when a reverse bias is applied (see paragraph 44), is at the terminals of the transmitters (see for example the last sentence of paragraph 44) and not between the gate and the source of the modulators; indeed, during the phases of inverse polarization in question here, the gate and the source of the modulators are brought to the same potential by the simultaneous closing of the referenced switches Tr3 and Tr4, and there is no polarization, inverse or no, between the gate and the source.

Le document US2004/0061671 décrit un dispositif d'affichage piloté par un courant continu.The document US2004 / 0061671 describes a display device controlled by a direct current.

Un but de l'invention est notamment de proposer un dispositif d'affichage alternatif propre à compenser les variations au cours du temps des tensions de seuil de déclenchement.An object of the invention is in particular to provide an alternative display device adapted to compensate for the variations over time of the trigger threshold voltages.

L'invention a pour objet un dispositif d'affichage du type précité, caractérisé en ce qu'il comporte en outre :

  • un interrupteur de polarisation inverse pour chaque émetteur, ledit interrupteur de polarisation inverse étant raccordé entre d'une part l'électrode de grille de chaque modulateur et la première borne du condensateur de stockage de cet émetteur, et d'autre part le ou chaque générateur de tension de polarisation inverse et la seconde borne du condensateur de stockage de cet émetteur ; et
  • des électrodes de commande, chaque électrode de commande étant apte à piloter l'ensemble des interrupteurs de polarisation inverse d'une ligne d'émetteurs.
The invention relates to a display device of the aforementioned type, characterized in that it further comprises:
  • a reverse bias switch for each emitter, said inverse bias switch being connected between firstly the gate electrode of each modulator and the first terminal of the storage capacitor of this emitter, and secondly the or each generator reverse bias voltage and the second terminal of the storage capacitor of this transmitter; and
  • control electrodes, each control electrode being able to control the set of reverse bias switches of a line of emitters.

Suivant des modes particuliers de réalisation, le dispositif d'affichage comporte une ou plusieurs des caractéristiques suivantes :

  • les moyens de sélection comprennent des électrodes de sélection propres à piloter les interrupteurs de sélection, lesdits électrodes de sélection étant distinctes et indépendantes des électrodes de commande ;
  • le réseau formé par les émetteurs comprend un premier groupe de lignes d'émetteurs et un deuxième groupe de lignes d'émetteurs, les lignes des deux groupes étant intercalées, et chaque électrode de commande est raccordée à la grille des interrupteurs de polarisation inverse d'une ligne d'émetteurs du premier groupe et à la grille des interrupteurs de sélection d'une ligne d'émetteurs du deuxième groupe pour commander la fermeture simultanée des interrupteurs de sélection et des interrupteurs de commande appartenant à ces lignes d'émetteurs ;
  • il comprend un unique générateur de tension de polarisation inverse raccordé à l'ensemble des interrupteurs de polarisation inverse du dispositif ;
  • il comprend plusieurs générateurs de tension de polarisation inverse propres à produire chacun une tension de polarisation inverse propre et différente des tensions de polarisation inverse produites par les autres générateurs, chaque générateur étant raccordé uniquement à l'ensemble des interrupteurs de polarisation inverse d'une ligne d'émetteurs.
According to particular embodiments, the display device comprises one or more of the following characteristics:
  • the selection means comprise selection electrodes suitable for driving the selection switches, said selection electrodes being distinct and independent of the control electrodes;
  • the network formed by the emitters comprises a first group of emitter lines and a second group of emitter lines, the lines of the two groups being intercalated, and each control electrode is connected to the gate of the inverse polarization switches of a line of emitters of the first group and the gate of the selector switches of a line of emitters of the second group for controlling the simultaneous closing of the selector switches and the control switches belonging to these lines of emitters;
  • it comprises a single reverse bias voltage generator connected to the set of inverse polarization switches of the device;
  • it comprises a plurality of reverse bias voltage generators each capable of producing a clean reverse bias voltage and different from the reverse bias voltages produced by the other generators, each generator being connected only to the set of reverse-bias switches of a line of issuers.

Avantageusement, ce dispositif divise par deux le nombre d'électrodes de ligne contenu dans le dispositif.Advantageously, this device divides by two the number of line electrodes contained in the device.

L'invention a également pour objet un procédé de pilotage du dispositif d'affichage d'images selon la revendication 3, ledit dispositif comprenant successivement une première et une deuxième lignes d'émetteurs, caractérisé en ce que le procédé comporte les étapes suivantes :

  • application d'une première tension de sélection à l'électrode de commande raccordée aux interrupteurs de sélection de la première ligne d'émetteurs, à une fréquence prédéfinie,
  • application d'une seconde tension de sélection à l'électrode de commande raccordée aux interrupteurs de sélection de la deuxième ligne d'émetteurs, à la même fréquence prédéfinie,
et en ce que les applications des première et seconde tensions de sélection sont décalées d'une demi-période, la durée de cette demi-période étant égale à la durée d'une demi-trame d'image.The subject of the invention is also a method for controlling the image display device according to claim 3, said device comprising successively first and second transmitter lines, characterized in that the method comprises the following steps:
  • applying a first selection voltage to the control electrode connected to the selection switches of the first line of transmitters at a predetermined frequency,
  • applying a second selection voltage to the control electrode connected to the selection switches of the second line of transmitters at the same preset frequency,
and in that the applications of the first and second selection voltages are shifted by half a period, the duration of this half-period being equal to the duration of one half-frame of image.

Suivant des modes particuliers de réalisation, le procédé de pilotage du dispositif d'affichage, comporte une ou plusieurs des caractéristiques suivantes :

  • application d'une tension de sélection à l'électrode de sélection, à une fréquence prédéfinie,
  • application d'une tension de commande à l'électrode de commande, à la même fréquence prédéfinie, l'application de ladite tension de commande étant décalée dans le temps d'une fraction de période par rapport à l'application de ladite tension de sélection ;
  • la fraction de période est égale à une demi-période ;
  • la fraction de période est égale à un tiers de période ; et
  • la durée d'une période est égale à la durée d'une trame d'image.
According to particular embodiments, the control method of the display device comprises one or more of the following characteristics:
  • applying a selection voltage to the selection electrode at a predefined frequency,
  • applying a control voltage to the control electrode at the same predefined frequency, the application of said control voltage being shifted in time by a fraction of a period with respect to the application of said selection voltage ;
  • the fraction of period is equal to half a period;
  • the fraction of the period is equal to one third of the period; and
  • the duration of a period is equal to the duration of an image frame.

L'invention sera mieux comprise à la lecture de la description qui va suivre, donnée uniquement à titre d'exemple et faite en se référant aux dessins annexés, sur lesquels :

  • la Fig.1 est une vue schématique d'une partie d'un dispositif d'affichage selon un premier mode de réalisation de l'invention ;
  • les Fig.2 et 4 sont des graphes représentant l'évolution temporelle d'un signal de sélection propre à sélectionner un premier et respectivement un second émetteurs du dispositif représenté sur la Fig.1 ;
  • les Fig.3 et 5 sont des graphes représentant l'évolution temporelle d'un signal de commande propre à commander le premier et respectivement le second émetteurs du dispositif représenté sur la Fig.1 ;
  • les Fig.6 et 7 sont des graphes représentant l'évolution temporelle d'une tension associé au premier émetteur et respectivement au second émetteur du dispositif représenté sur la Fig.1 ;
  • la Fig.8 est une vue schématique d'une partie d'un dispositif d'affichage selon un second mode de réalisation de l'invention ;
  • les Fig.9, 10, 11 et 12 sont des graphes représentant l'évolution temporelle d'un signal de commande propre à commander un émetteur d'une première ligne d'émetteurs, un émetteur d'une deuxième ligne d'émetteurs ainsi qu'un émetteur d'une troisième ligne d'émetteurs, et respectivement l'émetteur de la troisième ligne d'émetteurs ainsi qu'un émetteur d'une quatrième ligne d'émetteurs, du dispositif représenté sur la Fig.8 ; et
  • les Fig.13, 14 et 15 sont des graphes représentant l'évolution temporelle d'une tension stockée par un condensateur associé à l'émetteur de la première ligne d'émetteurs, à l'émetteur de la deuxième ligne d'émetteurs et respectivement associé à l'émetteur de la troisième ligne d'émetteurs, du dispositif représenté sur la Fig.8.
The invention will be better understood on reading the description which follows, given solely by way of example and with reference to the appended drawings, in which:
  • the Fig.1 is a schematic view of a portion of a display device according to a first embodiment of the invention;
  • the Fig.2 and 4 are graphs representing the temporal evolution of a selection signal suitable for selecting a first and a second transmitter of the device shown in FIG. Fig.1 ;
  • the Fig.3 and 5 are graphs representing the time evolution of a control signal suitable for controlling the first and second emitters of the device shown in FIG. Fig.1 ;
  • the Fig.6 and 7 are graphs representing the temporal evolution of a voltage associated with the first transmitter and the second transmitter of the device represented on the Fig.1 ;
  • the Fig.8 is a schematic view of a portion of a display device according to a second embodiment of the invention;
  • the Fig.9, 10, 11 and 12 are graphs representing the time evolution of a control signal suitable for controlling a transmitter of a first line of transmitters, a transmitter of a second line of transmitters as well as a transmitter of a third line of transmitters, and respectively the transmitter of the third line of transmitters and a transmitter of a fourth line of transmitters, of the device represented on the Fig.8 ; and
  • the Fig.13, 14 and 15 are graphs representing the temporal evolution of a voltage stored by a capacitor associated with the transmitter of the first line of transmitters, the transmitter of the second line of transmitters and respectively associated with the transmitter of the third line of transmitters, the device shown on the Fig.8 .

Une partie du dispositif d'affichage 1 selon un premier mode de réalisation de l'invention, est illustrée schématiquement sur la Fig.1. Celle-ci comporte des émetteurs de lumière 2, 4, 6, 8, répartis selon un réseau comprenant des lignes et des colonnes d'émetteurs.Part of the display device 1 according to a first embodiment of the invention is schematically illustrated on the Fig.1 . It comprises light emitters 2, 4, 6, 8, distributed in a network comprising rows and columns of emitters.

Sur la Fig.1, seules une première 10 et une deuxième 12 lignes d'émetteurs et une première 14 et deuxième 16 colonnes d'émetteurs ont été représentées.On the Fig.1 only a first 10 and a second 12 emitter lines and a first 14 and second 16 emitter columns have been shown.

Les émetteurs 2, 4, 6, 8 sont des diodes électroluminescentes organiques. Ils comprennent une anode et une cathode. Ils émettent une intensité lumineuse directement proportionnelle au courant qui les traverse. Chaque émetteur constitue un pixel élémentaire du dispositif d'affichage.The emitters 2, 4, 6, 8 are organic light emitting diodes. They include an anode and a cathode. They emit a luminous intensity directly proportional to the current passing through them. Each transmitter constitutes an elementary pixel of the display device.

Le dispositif d'affichage comporte en outre des circuits d'adressage 18, 20, 22, 24 répartis selon un réseau.The display device further comprises addressing circuits 18, 20, 22, 24 distributed along a network.

Chaque circuit d'adressage est raccordé à un émetteur 2, 4, 6, 8 pour le piloter.Each addressing circuit is connected to a transmitter 2, 4, 6, 8 to drive it.

Les circuits d'adressage 18, 22 ; 20, 24 de chaque colonne d'émetteurs 14, 16 sont adressés par l'intermédiaire d'une électrode d'adressage 26, 28 de cette colonne d'émetteurs. Chaque électrode d'adressage 26, 28 est raccordée à une unité de pilotage de colonne 30 (en anglais : column driver).Addressing circuits 18, 22; 20, 24 of each column of emitters 14, 16 are addressed via an addressing electrode 26, 28 of this column of emitters. Each addressing electrode 26, 28 is connected to a column driver unit 30 (in English: column driver).

L'unité de pilotage 30 est propre à recevoir un signal d'affichage d'images et à transmettre simultanément à chaque électrode d'adressage 26, 28 d'une colonne, une tension d'adressage Vdata représentative d'une donnée d'affichage d'un émetteur à adresser dans cette colonne.The control unit 30 is able to receive an image display signal and to transmit simultaneously to each addressing electrode 26, 28 of a column, an address voltage V data representative of a data item. display of a transmitter to be addressed in this column.

Les circuits d'adressage 18, 20 ; 22, 24 de chaque ligne d'émetteurs 10, 12 sont sélectionnés par l'intermédiaire d'une électrode de sélection 32, 34, raccordée chacune à une unité de pilotage de sélection 33, 35.Addressing circuits 18, 20; 22, 24 of each emitter line 10, 12 are selected via a selection electrode 32, 34, each connected to a selection control unit 33, 35.

L'unité de pilotage de sélection 33, 35 d'une ligne d'émetteurs 10, 12 est adaptée pour générer à une fréquence prédéfinie, un signal de sélection V32, V34 à l'électrode de sélection 32, 34 de cette ligne 10, 12 pour sélectionner l'ensemble des émetteurs 2, 4 et 6, 8 de cette ligne 10, 12.The selection control unit 33, 35 of a line of transmitters 10, 12 is adapted to generate at a preset frequency, a selection signal V 32 , V 34 at the selection electrode 32, 34 of this line 10, 12 to select all transmitters 2, 4 and 6, 8 of this line 10, 12.

Ce signal de sélection comprend une série d'impulsions générées chacune à chaque nouvelle trame d'image. Ces impulsions sont des données logiques de sélection d'un émetteur d'une ligne d'émetteurs.This selection signal comprises a series of pulses each generated at each new image frame. These pulses are logical data for selecting a transmitter of a line of transmitters.

Comme les circuits d'adressage 18, 20, 22 et 24 sont identiques, seul le circuit 18 sera décrit de manière détaillée.Since the addressing circuits 18, 20, 22 and 24 are identical, only the circuit 18 will be described in detail.

Ce circuit 18 comprend un modulateur de courant 36, un interrupteur de sélection 38, un condensateur de stockage 40 (référencé 41 dans le circuit d'adressage 28 de la deuxième ligne d'émetteurs 12) et deux électrodes d'alimentation en puissance 42, 44.This circuit 18 comprises a current modulator 36, a selection switch 38, a storage capacitor 40 (referenced 41 in the addressing circuit 28 of the second emitter line 12) and two power supply electrodes 42, 44.

Le modulateur de courant 36 et l'interrupteur 38 sont des transistors en couches minces (en anglais : Thin Film Transistor), basés sur une technologie utilisant du silicium polycristallin (Poly-Si), du silicium amorphe (a-Si) ou du silicium microcristallin (micro-Si) déposé en couches minces sur un substrat de verre. De tels composants comprennent trois électrodes : une électrode de drain et une électrode de source entre lesquelles circule un courant modulé appelé courant de drain, et une électrode de grille.The current modulator 36 and the switch 38 are thin film transistors (in English: Thin Film Transistor), based on a technology using polycrystalline silicon (Poly-Si), amorphous silicon (a-Si) or silicon microcrystalline (micro-Si) deposited in thin layers on a glass substrate. Such components comprise three electrodes: a drain electrode and a source electrode between which circulates a modulated current called drain current, and a gate electrode.

Le modulateur 36 représenté sur la Fig.1, est de type N, de sorte que, en fonctionnement, son courant de drain circule de son drain à sa source. On notera que le dispositif selon l'invention peut aussi être utilisé pour piloter des transistors TFT de type P.The modulator 36 shown on the Fig.1 , is of type N, so that, in operation, its drain current flows from its drain to its source. It will be noted that the device according to the invention can also be used to drive P-type TFT transistors.

Le condensateur 40 est apte à stocker des charges électriques pour maintenir une tension à la grille du modulateur 36 après la transmission d'une tension d'adressage.The capacitor 40 is able to store electrical charges to maintain a voltage at the gate of the modulator 36 after the transmission of an addressing voltage.

Le condensateur 40 comprend une première borne 40a connectée à la grille du modulateur 36 et une seconde borne 40b connectée à une électrode de polarisation inverse 52.The capacitor 40 comprises a first terminal 40a connected to the gate of the modulator 36 and a second terminal 40b connected to a reverse bias electrode 52.

Le drain du modulateur 36 est raccordé à la cathode de l'émetteur 2. La source du modulateur 36 est raccordée à l'électrode d'alimentation 44 qui est maintenue à un potentiel constant. La grille du modulateur 36 est raccordée d'une part, à une première borne du condensateur 40 et d'autre part, à une électrode de passage de courant (drain ou source) de l'interrupteur 38. L'autre électrode de passage de courant (drain ou source) de l'interrupteur 38 est raccordée à l'électrode d'adressage 26. La grille de l'interrupteur 38 est raccordée à l'électrode de sélection 32. L'anode de l'émetteur 2 est raccordée à l'électrode d'alimentation 42.The drain of the modulator 36 is connected to the cathode of the transmitter 2. The source of the modulator 36 is connected to the supply electrode 44 which is maintained at a constant potential. The gate of the modulator 36 is connected on the one hand to a first terminal of the capacitor 40 and on the other hand to an electrode current passage (drain or source) of the switch 38. The other current passage electrode (drain or source) of the switch 38 is connected to the addressing electrode 26. The gate of the switch 38 is connected to the selection electrode 32. The anode of the transmitter 2 is connected to the supply electrode 42.

Le dispositif d'affichage 1 comporte de plus pour chaque ligne d'émetteurs 10, 12, un générateur de polarisation inverse 46, 48 raccordé à une électrode de polarisation inverse 52, 54 et un générateur de commande de polarisation inverse 53, 55 raccordé à une électrode de commande de polarisation inverse 56, 58.The display device 1 further comprises, for each line of emitters 10, 12, a reverse bias generator 46, 48 connected to a reverse bias electrode 52, 54 and a reverse bias control generator 53, 55 connected to a reverse bias control electrode 56, 58.

Les générateurs de polarisation inverse 46 et 48 sont aptes à générer chacun, entre la grille et la source des modulateurs 36, une tension de polarisation Vp, de valeurs éventuellement différentes entre elles et de polarité inverse à la polarité des tensions d'adressage Vdata appliquées entre la grille et la source des modulateurs 36 lors des phases d'émission des émetteurs 2, 4, 6, 8.The inverse polarization generators 46 and 48 are able to generate, each between the gate and the source of the modulators 36, a bias voltage V p of values possibly different from each other and of polarity opposite to the polarity of the addressing voltages V. data applied between the gate and the source of the modulators 36 during the transmission phases of the transmitters 2, 4, 6, 8.

L'électrode de polarisation inverse 52, 54 est raccordée à la seconde borne du condensateur 40, 41 de chaque circuit d'adressage d'une ligne d'émetteurs 10, 12.The inverse bias electrode 52, 54 is connected to the second terminal of the capacitor 40, 41 of each addressing circuit of a transmitter line 10, 12.

Les générateurs de commande de polarisation inverse 53, 55, sont adaptés pour produire un signal de commande de polarisation inverse V56, V58, similaire au signal de sélection V32, V34, de même fréquence et décalé d'une demi période ou période variable par rapport à ce signal de sélection.The reverse bias control generators 53, 55, are adapted to produce a reverse bias control signal V 56 , V 58 , similar to the selection signal V 32 , V 34 , of the same frequency and shifted by half a period or variable period with respect to this selection signal.

Le dispositif 1 comprend en outre un interrupteur de polarisation inverse 59 dans chaque circuit d'adressage 18, 20, 22, 24.The device 1 further comprises a reverse bias switch 59 in each addressing circuit 18, 20, 22, 24.

Cet interrupteur 59 est un transistor en couches minces de même type que l'interrupteur 38 et le modulateur 36.This switch 59 is a thin-film transistor of the same type as the switch 38 and the modulator 36.

Une électrode de passage de courant (source ou drain) de l'interrupteur 59 de chaque circuit d'adressage d'une ligne d'émetteurs 10, 12 est raccordée à l'électrode de polarisation inverse 52, 54 de cette ligne d'émetteurs 10, 12, et, par conséquent, également à la seconde borne 40b du condensateur 40, 41. L'autre électrode de passage de courant (source ou drain) de l'interrupteur 59 est raccordée à la grille du modulateur 36, et, par conséquent, également à la première borne 40a du condensateur 40, 41. La grille de l'interrupteur 59 de chaque circuit d'adressage d'une ligne d'émetteurs 10, 12 est raccordée à l'électrode de commande de polarisation inverse 56, 58 de cette même ligne d'émetteurs 10, 12.A current-passing electrode (source or drain) of the switch 59 of each addressing circuit of an emitter line 10, 12 is connected to the inverse bias electrode 52, 54 of this emitter line. 10, 12, and therefore also to the second terminal 40b of the capacitor 40, 41. The other current-passing electrode (source or drain) of the switch 59 is connected to the gate of the modulator 36, and consequently, also at the first terminal 40a of the capacitor 40, 41. The gate of the switch 59 of each addressing circuit of an emitter line 10, 12 is connected to the reverse bias control electrode 56, 58 of this same emitter line 10, 12.

Seul le fonctionnement des émetteurs 2, 6 de la première colonne 14, et de la première 10 et de la deuxième 12 lignes d'émetteurs, est décrit de manière détaillée.Only the operation of the emitters 2, 6 of the first column 14, and the first 10 and second 12 lines of transmitters, is described in detail.

Au temps T = T0, une impulsion du signal de sélection V32 représenté sur la Fig.2, est générée à l'électrode de sélection 32 de la première ligne d'émetteurs 10. Simultanément, l'unité de pilotage 30 adresse une tension d'adressage Vdata2 à l'électrode d'adressage 26. La valeur de cette tension d'adressage est référencée au potentiel constant de l'électrode d'alimentation 44.At time T = T0, a pulse of the selection signal V 32 represented on the Fig.2 is generated at the selection electrode 32 of the first line of transmitters 10. Simultaneously, the control unit 30 addresses an address voltage V data2 to the addressing electrode 26. The value of this voltage d The addressing is referenced to the constant potential of the supply electrode 44.

En conséquence, les interrupteurs 38 de la première ligne d'émetteurs 10 se ferment et la tension Vdata2 est appliquée à la première borne 40a du condensateur 40 et entre la grille et la source du modulateur 36 du circuit d'adressage 18, comme visible sur la Fig.6. Après la fin de l'impulsion du signal de sélection V32, les interrupteurs 38 de la première ligne d'émetteurs 10 s'ouvrent et la tension Vdata2 est maintenue, grâce au condensateur 40, entre la grille et la source du modulateur 36 du circuit d'adressage 18, comme visible sur la Fig.6.Consequently, the switches 38 of the first line of emitters 10 close and the voltage V data2 is applied to the first terminal 40a of the capacitor 40 and between the gate and the source of the modulator 36 of the addressing circuit 18, as visible on the Fig.6 . After the end of the pulse of the selection signal V 32 , the switches 38 of the first line of emitters 10 open and the voltage V data2 is maintained, thanks to the capacitor 40, between the gate and the source of the modulator 36 of the addressing circuit 18, as visible on the Fig.6 .

Comme la tension Vdata2 est supérieure à la tension de seuil de déclenchement du modulateur 36, un courant de drain traverse l'émetteur 2 qui s'illumine.Since the voltage V data2 is greater than the trigger threshold voltage of the modulator 36, a drain current passes through the emitter 2 which lights up.

Au temps T=T1, une impulsion du signal de sélection V34 représenté sur la Fig.4, est appliquée à l'électrode de sélection 34. Simultanément, l'unité de pilotage 30 adresse une tension d'adressage Vdata6 à l'électrode d'adressage 26. La valeur de cette tension d'adressage est également référencée au potentiel constant de l'électrode d'alimentation 44.At the time T = T1, a pulse of the selection signal V 34 represented on the Fig.4 is applied to the selection electrode 34. Simultaneously, the control unit 30 addresses an address voltage V data6 to the addressing electrode 26. The value of this addressing voltage is also referenced to the constant potential. of the supply electrode 44.

En conséquence, les interrupteurs 38 de la deuxième ligne d'émetteurs 12 se ferment et la tension Vdata6 est appliquée au condensateur 41 et entre la grille et la source du modulateur 36 du circuit d'adressage 22 de la deuxième ligne d'émetteurs 12. Comme la tension Vdata6 est supérieure à la tension de seuil de déclenchement du modulateur 36, un courant de drain traverse l'émetteur 6 qui s'illumine. Après la fin de l'impulsion du signal de sélection V34, les interrupteurs 38 de la deuxième ligne d'émetteurs 12 s'ouvrent et la tension Vdata6 est maintenue, grâce au condensateur 41, entre la grille et la source du modulateur 36 du circuit d'adressage 22, comme visible sur la Fig.7.Consequently, the switches 38 of the second line of emitters 12 close and the voltage V data6 is applied to the capacitor 41 and between the gate and the source of the modulator 36 of the addressing circuit 22 of the second emitter line 12 Since the voltage V data6 is greater than the trigger threshold voltage of the modulator 36, a drain current passes through the emitter 6 which lights up. After the end of the pulse of the selection signal V 34 , the switches 38 of the second line of emitters 12 open and the voltage V data6 is maintained, thanks to the capacitor 41, between the gate and the source of the modulator 36 of the addressing circuit 22, as visible on the Fig.7 .

Cette étape est répétée successivement pour chaque émetteur d'une ligne, ligne après ligne pour l'ensemble des lignes du dispositif d'affichage pendant une période allant de T=T1 jusqu'à T=T4.This step is repeated successively for each transmitter of a line, line by line for all the lines of the display device for a period ranging from T = T1 to T = T4.

Parallèlement, au temps T=T2, une impulsion du signal de commande V56 représenté sur la Fig.3, est appliquée à l'électrode de commande 56.Meanwhile, at the time T = T2, a pulse of the control signal V 56 represented on the Fig.3 , is applied to the control electrode 56.

Cette impulsion ferme les interrupteurs 59 de la première ligne d'émetteurs 10, de sorte que la tension de polarisation inverse Vp générée par le générateur 46 est appliquée entre la grille et la source du modulateur 36 du circuit d'adressage 18 ; comme l'interrupteur 59 court-circuite alors les deux bornes du condensateur 40, ce condensateur est déchargé. Après la fin de l'impulsion du signal de commande V56, les interrupteurs 59 de la première ligne d'émetteurs 10 s'ouvrent et la tension VP est maintenue entre la grille et la source du modulateur 36 du circuit d'adressage 18, comme visible sur la Fig.6, car le condensateur 40 conserve une charge nulle.This pulse closes the switches 59 of the first emitter line 10, so that the reverse bias voltage V p generated by the generator 46 is applied between the gate and the source of the modulator 36 of the addressing circuit 18; as the switch 59 then bypasses the two terminals of the capacitor 40, this capacitor is discharged. After the end of the pulse of the control signal V 56 , the switches 59 of the first line of emitters 10 open and the voltage V P is maintained between the gate and the source of the modulator 36 of the addressing circuit 18 , as visible on the Fig.6 because the capacitor 40 keeps a zero charge.

Ensuite, au temps T = T3, une impulsion du signal de commande V58 représenté sur la Fig.5, est appliquée à l'électrode de commande 58 de la deuxième ligne d'émetteurs 12 pour fermer les interrupteurs 59 de cette deuxième ligne 12. En conséquence, la tension de polarisation inverse Vp générée par le générateur 48 est appliquée à la seconde borne du condensateur 41 ainsi qu'à la grille du modulateur 36 du circuit d'adressage 22 de la deuxième ligne d'émetteurs 12 ; comme l'interrupteur 59 court-circuite alors les deux bornes du condensateur 41, ce condensateur est déchargé. Après la fin de l'impulsion du signal de commande V58, les interrupteurs 59 de la deuxième ligne d'émetteurs 12 s'ouvrent et la tension VP est maintenue entre la grille et la source du modulateur 36 du circuit d'adressage 22, comme visible sur la Fig.7, car le condensateur 41 conserve une charge nulle.Then, at the time T = T3, a pulse of the control signal V 58 represented on the Fig.5 , is applied to the control electrode 58 of the second emitter line 12 to close the switches 59 of this second line 12. Accordingly, the reverse bias voltage V p generated by the generator 48 is applied to the second terminal capacitor 41 as well as to the gate of the modulator 36 of the addressing circuit 22 of the second emitter line 12; as the switch 59 bypasses both terminals of the capacitor 41, this capacitor is discharged. After the end of the pulse of the control signal V 58 , the switches 59 of the second line of emitters 12 open and the voltage V P is maintained between the gate and the source of the modulator 36 of the addressing circuit 22 , as visible on the Fig.7 because the capacitor 41 maintains a zero charge.

Au temps T=T4, l'étape réalisée au temps T=T0 est répétée. Ainsi, une impulsion du signal de sélection V32 représenté sur la Fig.2, est appliquée à l'électrode de sélection 32. Simultanément, l'unité de pilotage 30 adresse une nouvelle tension d'adressage à l'électrode d'adressage 26.At time T = T4, the step performed at time T = T0 is repeated. Thus, a pulse of the selection signal V 32 represented on the Fig.2 , is applied to the selection electrode 32. Simultaneously, the control unit 30 addresses a new address voltage to the addressing electrode 26.

Au temps T=T5, l'étape réalisée au temps T=T1 est répétée.At time T = T5, the step performed at time T = T1 is repeated.

Ensuite, le procédé de fonctionnement du dispositif selon l'invention se poursuit par répétition des étapes décrites ci-dessus.Next, the operating method of the device according to the invention is continued by repeating the steps described above.

La durée de T0 à T4 correspond à la durée d'une trame d'image. La durée d'une trame d'image est divisée en deux phases, ici T0 à T2 et T2 à T4, par exemple d'une durée chacune égale à la durée d'une demi trame d'image.The duration of T0 to T4 corresponds to the duration of an image frame. The duration of an image frame is divided into two phases, here T0 to T2 and T2 to T4, for example of a duration each equal to the duration of half a frame of image.

Au cours d'une première phase (correspondant aux durées de T=T0 à T=T2 et de T=T1 à T=T3), les émetteurs de l'écran sont illuminés, et au cours d'une seconde phase (correspondant aux durées de T=T2 à T=T4 et de T=T3 à T=T5), les émetteurs sont éteints. Le rapport des durées entre la première phase et la seconde phase est de 50/50.During a first phase (corresponding to the durations of T = T0 to T = T2 and T = T1 to T = T3), the emitters of the screen are illuminated, and during a second phase (corresponding to durations of T = T2 at T = T4 and T = T3 at T = T5), the emitters are extinguished. The ratio of the durations between the first phase and the second phase is 50/50.

En variante, le rapport des durées entre la première phase et la seconde phase est de 60/40 ou de 70/30.Alternatively, the ratio of the durations between the first phase and the second phase is 60/40 or 70/30.

Au cours des phases d'émission des émetteurs, les tensions d'adressage Vdata de données d'affichage appliquées entre la grille et la source des modulateurs 36 raccordés à ces émetteurs, sont propres à faire varier les tensions de seuil de déclenchement des modulateurs 36 dans un premier sens.During the transmission phases of the transmitters, the V data addressing voltages of display data applied between the gate and the source of the modulators 36 connected to these transmitters, are adapted to vary the tripping threshold voltages of the modulators. 36 in a first sense.

Au cours des phases éteintes des émetteurs, les tensions de polarisation inverse Vp sont appliquées entre la grille et la source des modulateurs 36 raccordés à ces émetteurs pour faire varier leur tension de seuil de déclenchement en sens inverse de manière à compenser la dérive éventuelle de cette tension de seuil.During the extinct phases of the emitters, the inverse bias voltages V p are applied between the gate and the source of the modulators 36 connected to these emitters in order to vary their trigger threshold voltage in the opposite direction so as to compensate for the possible drift of this threshold voltage.

Comme les tensions de polarisation inverse Vp représentées sur les Fig. 6 et 7, présentent une polarité inverse à la polarité des tensions d'adressage Vdata2, Vdata6 précédemment appliquées aux modulateurs 36, elles sont propres à diminuer la tension de seuil de déclenchement des modulateurs 36 afin de ramener celle-ci à leur tension de seuil de déclenchement initiale (avant application de la tension d'adressage).As the reverse bias voltages V p represented on the Fig. 6 and 7 , have a polarity inverse to the polarity of the addressing voltages V data2 , V data6 previously applied to the modulators 36, they are suitable for reducing the triggering threshold voltage of the modulators 36 in order to bring it back to their threshold voltage. initial trip (before application of the addressing voltage).

Une partie d'un dispositif d'affichage 60 selon un second mode de réalisation de l'invention est illustrée schématiquement sur la Fig.8.Part of a display device 60 according to a second embodiment of the invention is schematically illustrated on the Fig.8 .

Les éléments du second mode de réalisation illustrés sur la Fig.8 identiques ou similaires aux éléments du premier mode de réalisation illustrés sur la Fig.1, sont désignés par les mêmes chiffres de référence que dans la Fig.1, et ne sont pas décrits une seconde fois.The elements of the second embodiment illustrated on the Fig.8 identical or similar to the elements of the first embodiment illustrated on the Fig.1 , are designated by the same reference numbers as in the Fig.1 , and are not described a second time.

La Fig.8 représentant le dispositif 60, comprend en sus de la partie du dispositif 1 représentée sur la Fig.1, une troisième ligne d'émetteurs 61, comportant des émetteurs 62 et 64, pilotés chacun par un circuit d'adressage 66, 67, ainsi qu'une quatrième ligne d'émetteurs 68 non représentée dans le détail.The Fig.8 representing the device 60, comprises in addition to the part of the device 1 represented on the Fig.1 , a third line of emitters 61, comprising emitters 62 and 64, each controlled by an addressing circuit 66, 67, and a fourth emitter line 68 not shown in detail.

Le circuit 66 est identique aux circuits 18, 20, 22, 24. Il comprend un condensateur référencé 76 ayant une première 76a et une seconde 76b bornes, ainsi qu'une électrode de polarisation inverse référencée 69 similaire aux électrodes 52 et 54 et raccordée à la seconde borne 76b du condensateur 76 et à une électrode de passage de courant de l'interrupteur 59.The circuit 66 is identical to the circuits 18, 20, 22, 24. It comprises a referenced capacitor 76 having a first 76a and a second 76b terminals, and a reverse bias electrode referenced 69 similar to the electrodes 52 and 54 and connected to the second terminal 76b of the capacitor 76 and a current-pass electrode of the switch 59.

Les générateurs de polarisation inverse 46, 48 connectés aux électrodes 52, 54 et 69 n'ont pas été représentés pour simplifier la Fig.8.The reverse bias generators 46, 48 connected to the electrodes 52, 54 and 69 have not been shown to simplify the Fig.8 .

Le dispositif 60 comprend des électrodes de commande pour la sélection et pour la polarisation inverse 70, 71 et 72 en remplacement des électrodes de sélection 32, 34 et des électrodes de commande de polarisation inverse 56 et 58 du dispositif 1 et une électrode de commande supplémentaire référencée 74.The device 60 comprises control electrodes for selection and for the reverse bias 70, 71 and 72 in place of the selection electrodes 32, 34 and the reverse bias control electrodes 56 and 58 of the device 1 and an additional control electrode referenced 74.

L'électrode de commande 70 est raccordée à l'ensemble des interrupteurs de commande de polarisation inverse 59 d'une ligne d'émetteurs non représentée, positionnée juste au-dessus de la première ligne 10, ainsi qu'à l'ensemble des interrupteurs de sélection 38 de la première ligne d'émetteurs 10.The control electrode 70 is connected to all of the reverse bias control switches 59 of a transmitter line, not shown, positioned just above the first line 10, as well as to all the switches. 38 of the first line of transmitters 10.

L'électrode de commande 71 est raccordée à l'ensemble des interrupteurs de commande de polarisation inverse 59 de la première ligne d'émetteurs 10, ainsi qu'à l'ensemble des interrupteurs de sélection 38 de la seconde ligne d'émetteurs 12.The control electrode 71 is connected to all of the reverse bias control switches 59 of the first emitter line 10, as well as to all of the selection switches 38 of the second emitter line 12.

De même, l'électrode de commande 72, respectivement l'électrode de commande 74, est raccordée à l'ensemble des interrupteurs de commande de polarisation inverse 59 de la seconde ligne d'émetteurs 12, respectivement de la troisième ligne d'émetteurs 61, ainsi qu'à l'ensemble des interrupteurs de sélection 38 de la troisième ligne d'émetteurs 61, respectivement de la quatrième ligne d'émetteurs 68.Similarly, the control electrode 72, respectively the control electrode 74, is connected to all the reverse bias control switches 59 of the second line of emitters 12, respectively of the third line of emitters 61. , as well as to all the selection switches 38 of the third line of emitters 61, respectively of the fourth emitter line 68.

Ainsi, les interrupteurs de commande de polarisation inverse 59 d'une ligne sont raccordés à la même électrode de commande que les interrupteurs de sélection 38 de la ligne suivante.Thus, the reverse bias control switches 59 of a line are connected to the same control electrode as the selection switches 38 of the next line.

Le dispositif 60 comprend en outre des générateurs de commande 80, 82, 84, 86 chacun raccordé à une électrode de commande 70, 71, 72, 74.The device 60 further comprises control generators 80, 82, 84, 86 each connected to a control electrode 70, 71, 72, 74.

Les générateurs 80, 82, 84, 86 sont propres à produire un signal de commande V70, V71, V72, V74 de même fréquence. Comme visible sur les figures 9 à 12, les signaux de commande V70, V71 appliqués aux électrodes de deux lignes adjacentes 10, 12 sont décalées d'une demi période d'image.The generators 80, 82, 84, 86 are able to produce a control signal V 70 , V 71 , V 72 , V 74 of the same frequency. As visible on Figures 9 to 12 the control signals V 70 , V 71 applied to the electrodes of two adjacent lines 10, 12 are shifted by half a picture period.

Seul le fonctionnement des émetteurs 6 et 62 de la première colonne 14 et de la première 10, de la deuxième 12 et de la troisième 61 lignes d'émetteurs, est décrit de manière détaillée.Only the operation of the emitters 6 and 62 of the first column 14 and the first 10, second 12 and third 61 lines of transmitters, is described in detail.

Au temps T=T0, une impulsion du signal de commande V71 représenté sur la Fig.10, est transmise à l'électrode de commande 71. Cette impulsion provoque la fermeture des interrupteurs de polarisation inverse 59 de la première ligne d'émetteurs 10 et des interrupteurs de sélection 38 de la deuxième ligne d'émetteurs 12.At time T = T0, a pulse of the control signal V 71 represented on the Fig.10 is transmitted to the control electrode 71. This pulse causes the closing of the reverse bias switches 59 of the first line of transmitters 10 and selection switches 38 of the second line of transmitters 12.

Simultanément, une tension d'adressage Vdata6 représentative d'une donnée d'affichage est appliquée à l'électrode d'adressage 26 par l'unité de pilotage 30. La valeur de cette tension d'adressage est référencée au potentiel constant de l'électrode d'alimentation 44.At the same time, a data signaling voltage V representative of a display datum is applied to the addressing electrode 26 by the control unit 30. The value of this addressing voltage is referenced to the constant potential of the signal. supply electrode 44.

Comme les interrupteurs 59 de la première ligne d'émetteurs 10 sont fermés, la tension de polarisation inverse Vp issue de l'électrode de polarisation inverse 52 est appliquée entre la grille et le source des modulateurs 36 et aux bornes des condensateurs 40 de la première ligne d'émetteurs 10. Comme l'interrupteur 59 court-circuite alors les deux bornes du condensateur 40, ce condensateur est déchargé. Après la fin de l'impulsion du signal de commande V71, les interrupteurs 59 de la première ligne d'émetteurs 10 s'ouvrent et la tension Vp est maintenue entre la grille et la source du modulateur 36 du circuit d'adressage 18, comme visible sur la Fig.13, car le condensateur 40 conserve une charge nulle.Since the switches 59 of the first line of emitters 10 are closed, the reverse bias voltage V p resulting from the inverse bias electrode 52 is applied between the gate and the source of the modulators 36 and across the capacitors 40 of the first line of emitters 10. As the switch 59 then bypasses the two terminals of the capacitor 40, this capacitor is discharged. After the end of the pulse of the control signal V 71 , the switches 59 of the first line of emitters 10 open and the voltage V p is maintained between the gate and the source of the modulator 36 of the addressing circuit 18 , as visible on the Fig.13 because the capacitor 40 keeps a zero charge.

Parallèlement, comme les interrupteurs 38 de la deuxième ligne d'émetteurs 12 sont simultanément fermés, la tension d'adressage Vdata6 issue de l'électrode 26, est appliquée à la première borne 41 a du condensateur 41 et à la grille du modulateur 36 de la deuxième ligne d'émetteurs 12, comme visible sur la Fig.14.At the same time, since the switches 38 of the second line of emitters 12 are simultaneously closed, the addressing voltage V data6 originating from the electrode 26 is applied to the first terminal 41a of the capacitor 41 and to the gate of the modulator 36 of the second line of emitters 12, as visible on the Fig.14 .

En conséquence, l'émetteur 2 est éteint et l'émetteur 6 est illuminé. Après la fin de l'impulsion du signal de commande V71, les interrupteurs 38 de la deuxième ligne d'émetteurs 12 s'ouvrent et la tension Vdata6 est maintenue, grâce au condensateur 41, entre la grille et la source du modulateur 36 du circuit d'adressage 22, comme visible sur la Fig.14.As a result, the transmitter 2 is off and the transmitter 6 is illuminated. After the end of the pulse of the control signal V 71 , the switches 38 of the second line of emitters 12 open and the voltage V data6 is maintained, thanks to to the capacitor 41, between the gate and the source of the modulator 36 of the addressing circuit 22, as visible on the Fig.14 .

Au temps T=T1, une impulsion du signal de commande V74 représenté sur la Fig.12, est appliquée à l'électrode de commande 74. L'application de cette impulsion provoque la fermeture des interrupteurs 59 de la troisième ligne d'émetteurs 61. Par suite de cette fermeture, la tension de polarisation inverse Vp de l'électrode de polarisation inverse 69 est appliquée entre la grille et la source du modulateur 36 et aux bornes du condensateur 76 de la troisième ligne d'émetteurs 61, comme visible sur la Fig.15.At time T = T1, a pulse of control signal V 74 represented on the Fig.12 is applied to the control electrode 74. The application of this pulse causes the switches 59 of the third emitter line 61 to close. As a result of this closure, the reverse bias voltage V p of the reverse bias 69 is applied between the gate and the source of the modulator 36 and across the capacitor 76 of the third emitter line 61, as visible on the fig.15 .

En conséquence, l'émetteur 62 s'éteint.As a result, the transmitter 62 turns off.

Comme l'interrupteur 59 court-circuite alors les deux bornes du condensateur 76, ce condensateur est déchargé. Après la fin de l'impulsion du signal de commande V74, les interrupteurs 59 de la troisième ligne d'émetteurs 66 s'ouvrent et la tension Vp est maintenue entre la grille et la source du modulateur 36 du circuit d'adressage 66, comme visible sur la Fig.15, car le condensateur 76 conserve une charge nulle.
Au temps T=T2, une impulsion du signal de commande V70 représenté sur la Fig.9 est appliquée à l'électrode de commande 70 par le générateur 80 et une tension d'adressage Vdata2 est appliquée à l'électrode d'adressage 26 par l'unité de pilotage d'adressage 30. La valeur de cette tension d'adressage est également référencée au potentiel constant de l'électrode d'alimentation 44...As the switch 59 then bypasses the two terminals of the capacitor 76, this capacitor is discharged. After the end of the pulse of the control signal V 74 , the switches 59 of the third line of emitters 66 open and the voltage V p is maintained between the gate and the source of the modulator 36 of the addressing circuit 66 , as visible on the fig.15 because the capacitor 76 keeps a zero charge.
At the time T = T2, a pulse of the control signal V 70 represented on the Fig.9 is applied to the control electrode 70 by the generator 80 and an addressing voltage V data2 is applied to the addressing electrode 26 by the addressing control unit 30. The value of this addressing voltage is also referenced to the constant potential of the supply electrode 44 ...

En conséquence, la tension d'adressage Vdata2, telle que représentée sur la Fig.13 est appliquée à la grille du modulateur 36 et aux bornes du condensateur 40 de la première ligne d'émetteurs 10 et l'émetteur 2 est illuminé.As a result, the addressing voltage V data2 , as represented on the Fig.13 is applied to the gate of the modulator 36 and the terminals of the capacitor 40 of the first emitter line 10 and the emitter 2 is illuminated.

Après la fin de l'impulsion du signal de commande V70, les interrupteurs 38 de la première ligne d'émetteurs 10 s'ouvrent et la tension Vdata2 est maintenue, grâce au condensateur 40, entre la grille et la source du modulateur 36 du circuit d'adressage 18, comme visible sur la Fig.13.After the end of the pulse of the control signal V 70 , the switches 38 of the first line of emitters 10 open and the voltage V data2 is maintained, thanks to the capacitor 40, between the gate and the source of the modulator 36 of the addressing circuit 18, as visible on the Fig.13 .

Au temps T=T3, une impulsion du signal de commande V72 représenté sur la Fig.11, est appliquée à l'électrode de commande 72. Celle-ci provoque la fermeture des interrupteurs de polarisation inverse 59 de la deuxième ligne d'émetteurs 12 et la fermeture des interrupteurs de sélection 38 de la troisième ligne d'émetteurs 61.Comme l'interrupteur 59 court-circuite alors les deux bornes du condensateur 41, ce condensateur est déchargé. Après la fin de l'impulsion du signal de commande V72, les interrupteurs 59 de la deuxième ligne d'émetteurs 12 s'ouvrent et la tension Vp est maintenue entre la grille et la source du modulateur 36 du circuit d'adressage 22, comme visible sur la Fig.14, car le condensateur 41 conserve une charge nulle.At time T = T3, a pulse of the control signal V 72 shown in FIG. Fig.11 , it is applied to the control electrode 72. This causes the closing of the reverse bias switches 59 of the second line of emitters 12 and the closing of the selector switches 38 of the third line of emitters 61. switch 59 then bypasses the two terminals of the capacitor 41, this capacitor is discharged. After the end of the pulse of control signal V 72 , the switches 59 of the second line of emitters 12 open and the voltage V p is maintained between the gate and the source of the modulator 36 of the addressing circuit 22, as visible on the Fig.14 because the capacitor 41 maintains a zero charge.

En conséquence, la tension de polarisation inverse Vp de l'électrode de polarisation inverse 54 est appliquée entre la grille et la source du modulateur 36 et aux bornes du condensateur 41 de la deuxième ligne d'émetteurs 12, comme visible sur la Fig.14.As a result, the reverse bias voltage V p of the inverse bias electrode 54 is applied between the gate and the source of the modulator 36 and across the capacitor 41 of the second emitter line 12, as visible on FIG. Fig.14 .

Par suite, l'émetteur 6 s'éteint.As a result, the transmitter 6 goes off.

Parallèlement, une tension d'adressage Vdata-62, telle que représentée sur la Fig.15, est transmise par l'électrode 26, et appliquée à la grille du modulateur 36 et à une borne du condensateur 76 de la troisième ligne d'émetteurs 61. En conséquence, l'émetteur 62 est illuminé.In parallel, an address voltage V data-62 , as represented on the fig.15 , is transmitted by the electrode 26, and applied to the gate of the modulator 36 and a terminal of the capacitor 76 of the third emitter line 61. Accordingly, the emitter 62 is illuminated.

Au temps T=T4 et T=T5, les étapes réalisées au temps T=0 et T=1 sont répétées, respectivement.At time T = T4 and T = T5, the steps performed at time T = 0 and T = 1 are repeated, respectively.

Les périodes de temps allant de T = T0 à T = T4 et de T = T1 à T = T5 correspondent chacun à la durée d'une image, constituée ici de deux trames entrelacées.The time periods from T = T0 to T = T4 and from T = T1 to T = T5 each correspond to the duration of an image, here constituted by two interlaced fields.

Selon ce mode de réalisation de l'invention, les émetteurs d'un groupe comprenant les lignes impaires 10, 61 du dispositif, sont éteints au cours d'une première trame T0-T2 ; T1-T3, puis illuminés au cours d'une deuxième trame T2-T4 ; T3-T5.According to this embodiment of the invention, the emitters of a group comprising the odd lines 10, 61 of the device are extinguished during a first frame T0-T2; T1-T3, then illuminated during a second T2-T4 frame; T3-T5.

A l'inverse, les émetteurs d'un autre groupe comprenant les lignes paires 12, 68 du dispositif, sont illuminés au cours d'une première trame T0-T2 ; T1-T3 puis éteints au cours d'une deuxième trame T2-T4 ; T3-T5.Conversely, the transmitters of another group comprising the even lines 12, 68 of the device are illuminated during a first frame T0-T2; T1-T3 then extinguished during a second T2-T4 frame; T3-T5.

Sans se départir de l'invention, on peut inverser l'ordre entre les trames paires et les trames impaires.Without departing from the invention, it is possible to reverse the order between the even fields and the odd fields.

Lorsque les émetteurs 2, 4 de la première ligne 12 sont éteints, les émetteurs 6, 8 de la deuxième ligne 12 sont illuminés et inversement.When the emitters 2, 4 of the first line 12 are off, the emitters 6, 8 of the second line 12 are illuminated and vice versa.

Avantageusement, ce second mode de réalisation de l'invention facilite l'adressage des données d'affichage lorsque le mode d'affichage est entrelacé car l'unité de pilotage 30 n'a pas besoin de recalculer l'échelonnement des données à adresser du signal d'affichage qu'elle réceptionne, pour repasser en mode dit « progressif ».Advantageously, this second embodiment of the invention facilitates the addressing of the display data when the display mode is interlaced because the control unit 30 does not need to recalculate the staggering of the data to be addressed. display signal it receives, to return to so-called "progressive" mode.

En effet, lors de l'utilisation d'un mode d'affichage entrelacé, les émetteurs d'une ligne sont adressés sur toutes les colonnes simultanément, pour l'ensemble des lignes paires lors d'une première trame, puis pour l'ensemble des lignes impaires lors d'une seconde trame.Indeed, when using an interlaced display mode, the transmitters of a line are addressed on all the columns simultaneously, for all the even lines in a first frame, and then for the set odd lines in a second frame.

Avantageusement, ce second mode de réalisation de l'invention permet de réduire le nombre d'électrodes de ligne car les électrodes de commande 70, 71, 72, 74 permettent de commander à la fois l'adressage des tensions d'adressage et l'adressage des tensions de polarisation inverse.Advantageously, this second embodiment of the invention makes it possible to reduce the number of line electrodes because the control electrodes 70, 71, 72, 74 make it possible to control both the addressing of the addressing voltages and the addressing reverse bias voltages.

Avantageusement, ce dispositif permet de ne pas utiliser une unité de pilotage propre à adresser des tensions de polarité positive et négative. Ce type d'unité de pilotage est en effet onéreux.Advantageously, this device makes it possible not to use a control unit capable of addressing positive and negative polarity voltages. This type of control unit is indeed expensive.

En variante, les électrodes de polarisation inverse 52, 54, 69 de l'ensemble du dispositif d'affichage sont reliées à un unique générateur de tension de polarisation inverse.In a variant, the reverse biasing electrodes 52, 54, 69 of the entire display device are connected to a single reverse bias voltage generator.

Claims (10)

  1. An image display device (1; 60) with active matrix comprising:
    a) a number of light emitters (2, 4, 6, 8; 62, 64) forming a network, divided into rows (10, 12; 61, 68) and columns (14, 16);
    b) means (42, 44) for supplying power to the emitters;
    c) means of controlling the emitters comprising:
    - a current modulator (36) for each emitter (2, 4, 6, 8; 62, 64), the modulator (36) comprising a source electrode, a drain electrode, a gate electrode, the modulator (36) being able to be passed through by a drain current, to supply said emitter (2, 4, 6, 8; 62, 64) for a voltage between the source electrode and the gate electrode, greater than or equal to a trigger threshold voltage of this modulator;
    - a storage capacitor (40, 41; 76) for each emitter (2, 4, 6, 8; 62, 64), said capacitor (40, 41; 76) comprising a first (40a, 41a; 76a) and a second (40b, 41b; 76b) terminals and being able to store electrical charges at the gate electrode of each modulator (36);
    - addressing means (26, 28, 30) able to address display data to the emitters (2, 4, 6, 8; 62, 64) of each column (14, 16);
    - selection means (32, 34, 38) able to select the emitters (2, 4, 6, 8; 62, 64) of each row (10, 12; 61, 68), the selection means (32, 34, 38) comprising a selection switch (38) for each emitter (2, 4, 6, 8; 62, 64), the selection switch (38) being specifically for enabling addressing data supplied by the addressing means (26, 28, 30) to be applied between the gate electrode and the source electrode of each modulator (36); and
    d) at least one inverse bias voltage generator (46, 48, 52, 54; 69) specifically for applying an inverse bias voltage (Vp) of the bias of said addressing data between the gate electrode and the source electrode of each modulator (36) to compensate for the variation in the trigger threshold voltage of each modulator (36);
    characterized in that it also comprises:
    - an inverse bias switch (59) for each emitter (2, 4, 6, 8; 62, 64), said inverse bias switch (59) being connected between, on the one hand, the gate electrode of each modulator (36) and the first terminal (40a, 41 a; 76a) of the storage capacitor (40, 41; 76) of this emitter, and, on the other hand, the or each inverse bias voltage generator (46, 48, 52, 54; 69) and the second terminal (40b, 41b; 76b) of the storage capacitor (40, 41; 76) of this emitter; and
    - control electrodes (56, 58; 70, 71, 72, 74), each control electrode (56, 58; 70, 71, 72, 74) being able to drive all of the inverse bias switches (59) of a row of emitters (10, 12; 61,68).
  2. The device (1) as claimed in claim 1, characterized in that the selection means (32, 34, 38) comprise selection electrodes (32, 34) specifically for driving the selection switches (38), said selection electrodes (32, 34) being separate and independent of the control electrodes (56, 58).
  3. The device (60) as claimed in claim 1, characterized in that the network formed by the emitters (2, 4, 6, 8, 62, 64) comprises a first group of rows of emitters (10, 61) and a second group of rows of emitters (12, 68), the rows of the two groups being interposed, and in that each control electrode (71, 74) is connected to the gate of the inverse bias switches (59) of a row of emitters (10, 61) of the first group and to the gate of the selection switches (38) of a row of emitters (12, 69) of the second group to control the simultaneous closure of the selection switches (38) and of the control switches (59) belonging to these rows of emitters (10, 12, 61, 69).
  4. The device (1; 60) as claimed in any one of claims 1 to 3, characterized in that it comprises a single inverse bias voltage generator (46, 48, 52, 54; 69) connected to all the inverse bias switches (59) of the device.
  5. The device (1; 60) as claimed in any one of claims 1 to 3, characterized in that it comprises a number of inverse bias voltage generators (46, 48, 52, 54; 69) specifically for each to produce an inverse bias voltage (Vp) that is specific and different from the inverse bias voltages (Vp) produced by the other generators, each generator (46, 48, 52, 54; 69) being connected only to all the inverse bias switches (59) of a row of emitters (10, 12; 61, 68).
  6. A method of driving an image display device (60) as claimed in claim 3, said device comprising, in turn, a first (10) and a second (12) rows of emitters, characterized in that the method comprises the following steps:
    - application of a first selection voltage (V70) to the control electrode (70) connected to the selection switches (38) of the first row of emitters (10), at a predefined frequency,
    - application of a second selection voltage (V71) to the control electrode (71) connected to the selection switches (38) of the second row of emitters (12), at the same predefined frequency,
    and in that the applications of the first (V70) and second (V71) selection voltages are offset by a half-period, the duration of this half-period being equal to the duration of an image half-frame.
  7. The method of driving an image display device (1) as claimed in claim 2, said device comprising, in turn, a first (10) and a second (12) rows of emitters, characterized in that the method comprises the following steps:
    - application of a selection voltage (V32) to the selection electrode (32), at a predefined frequency,
    - application of a control voltage (V56) to the control electrode (56), at the same predefined frequency, the application of said control voltage (V56) being offset in time by a fraction of a period relative to the application of said selection voltage (V32).
  8. The drive method as claimed in claim 7, characterized in that the fraction of a period is equal to a half-period.
  9. The drive method as claimed in claim 7, characterized in that the fraction of a period is equal to a third of a period.
  10. The drive method as claimed in any one of claims 7 to 9, characterized in that the duration of a period is equal to the duration of an image frame.
EP06709267A 2005-02-10 2006-02-07 Image display device and method of controlling same Active EP1864275B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0501357 2005-02-10
PCT/FR2006/000279 WO2006084989A1 (en) 2005-02-10 2006-02-07 Image display device and method of controlling same

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EP1864275B1 true EP1864275B1 (en) 2009-09-09

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JP5186950B2 (en) * 2008-02-28 2013-04-24 ソニー株式会社 EL display panel, electronic device, and driving method of EL display panel
JP4760840B2 (en) * 2008-02-28 2011-08-31 ソニー株式会社 EL display panel, electronic device, and driving method of EL display panel
CN101251982B (en) * 2008-04-07 2010-06-09 上海广电光电子有限公司 Pixel circuit for improving active matrix organic light-emitting device life period
JP2010039436A (en) * 2008-08-08 2010-02-18 Sony Corp Display panel module and electronic apparatus

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JP2001042822A (en) * 1999-08-03 2001-02-16 Pioneer Electronic Corp Active matrix type display device
US6858989B2 (en) 2001-09-20 2005-02-22 Emagin Corporation Method and system for stabilizing thin film transistors in AMOLED displays
JP2003186437A (en) * 2001-12-18 2003-07-04 Sanyo Electric Co Ltd Display device
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JP2004118132A (en) * 2002-09-30 2004-04-15 Hitachi Ltd Direct-current driven display device
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JP4988603B2 (en) 2012-08-01
US7924250B2 (en) 2011-04-12
KR20070102524A (en) 2007-10-18
JP2008530604A (en) 2008-08-07
DE602006009087D1 (en) 2009-10-22
CN101116131B (en) 2011-01-12
US20080062073A1 (en) 2008-03-13
CN101116131A (en) 2008-01-30
KR101321951B1 (en) 2013-10-25
WO2006084989A1 (en) 2006-08-17

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