EP1597767A2

EP1597767A2 - Integrated semiconductor circuit comprising a transistor with laterally staggered source and drain electrodes

Info

Publication number: EP1597767A2
Application number: EP04715877A
Authority: EP
Inventors: Jörg Vollrath
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2003-02-28
Filing date: 2004-03-01
Publication date: 2005-11-23
Also published as: KR20050105261A; JP2006519474A; DE10308927A1; CN100442522C; US7372095B2; CN1757113A; WO2004077569A3; US20060049469A1; KR100798435B1; WO2004077569A2

Abstract

The invention relates to an integrated semiconductor circuit comprising a transistor and a strip conductor (11). Said transistor comprises a first source/drain electrode (1), a second source/drain electrode (2), and a gate electrode. Said strip conductor (11) is electrically insulated from a semiconductor substrate at least by means of a gate dielectric, and forms the gate electrode in the region of the transistor. The strip conductor (11) extends in the region of the transistor along a first direction (x). According to the invention, the second source/drain electrode (2) is arranged in such a way that it is offset in the first direction (x) in relation to the first source/drain electrode (1). The transistor thus formed has an inversion channel (K1) which extends only between two facing corner regions (1a, 2a) of the first and second source/drain electrodes, i.e. is considerably narrower than the inversion channel of a conventional transistor. The invention thus enables semiconductor circuits to be produced which are more compact.

Description

description

Integrated semiconductor circuit with a transistor and with a conductor track

The invention relates to a semiconductor integrated circuit with a transistor and with a conductor track.

Semiconductor circuits are implemented, for example, as CMOS circuits (complementary metal oxide semiconductor) and have transistors produced in MOS technology which form inversion channels from electrons or holes below a conductor track. In this case, two source / drain electrodes are formed opposite one another on both sides of a conductor track as implantation areas in a semiconductor substrate. The conductor track serves as a gate electrode in the region of the transistor and controls the formation or prevention of an inversion channel through its electrical potential. The inversion channel runs in the semiconductor substrate just below the semiconductor surface, specifically below a gate oxide layer between the mutually facing sides of both source / drain electrodes of the transistor. The width of the channel extends over the width of both source / drain regions along the direction of the course of the conductor track. Usually both the channel length and the channel width each correspond to the optical resolution limit F that can be achieved with the lithographic exposure device used in each case.

The transistor described above can be used in particular as a memory transistor in non-volatile semiconductor memories. In this case, it has a charge-storing between the conductor track and the semiconductor substrate Layer which spatially binds electrical charges which are interspersed in this layer when an inversion channel is formed and can thereby store digital information. In such memory circuits, there is a need for techniques which reduce the storage density, ie the number of storable information per substrate area. The task of miniaturizing electrical circuits also arises with logic circuits.

It is the object of the present invention to provide a semiconductor circuit which has a larger number of electrical components per substrate base area without reducing the optical resolution limit. In particular, the number of inversion channels that can be formed in a semiconductor substrate is to be increased by a factor of up to two while the substrate base area remains the same.

This object is achieved according to the invention by an integrated semiconductor circuit according to claim 1 with a transistor (10) and with a conductor track (11),

- The transistor (10) has a first (1) and a second source / drain electrode (2), which are arranged in a semiconductor substrate (20), and a gate electrode (7),

- wherein the conductor track (11) is at least electrically insulated from the semiconductor substrate (20) by a gate dielectric (14) and forms the gate electrode (7) in the region of the transistor (10),

- The conductor track (11) in the region of the transistor (10) runs along a first direction (x),

- The second source / drain electrode (2) in the first direction (x) is arranged offset to the first source / drain electrode (1) and - The transistor (10) between the gate electrode (7) and the semiconductor substrate (20) has a charge-storing layer (13) in which electrical charges (Ql, Q2) are locally bound.

According to the invention, a semiconductor circuit is proposed which has a transistor, preferably in a MOS design, with two source / drain electrodes offset with respect to one another in the direction of the course of the conductor track, the conductor track forming its gate electrode in the region of the transistor. Conventional semiconductor transistors have two source / drain electrodes, both of which adjoin the same or largely identical conductor track section, so that the inversion channel extends between them essentially over the entire width of the two source / drain electrodes. The inversion channel therefore has a width which corresponds to the optical resolution limit.

According to the invention, however, the first and the second source / drain electrodes are offset from one another in the direction of the conductor path, so that the inversion channel no longer occupies the entire width of the two source / drain electrodes measured in the direction of the conductor path, but only adjoins next to one another Corner regions of the first and the second source / drain electrode extends. Due to the lateral offset of the second source / drain electrode with respect to the first, the shortest possible connection between the two electrodes is, for example, the connecting line between a right corner area of the first electrode that faces the second electrode and a left corner area of the second electrode the first electrode is facing; an inversion channel becomes the edge regions of the source / drain adjacent to these corner regions No longer reach electrodes along the entire length of these edge areas, but essentially only short-circuit the facing corner areas. Since such an inversion channel takes up a much smaller substrate base area between the electrodes offset with respect to one another according to the invention, the potential for area savings on the semiconductor substrate increases.

The inversion channel is formed essentially along the connecting line of the two adjacent corner regions of the source / drain electrodes. The other two corner areas, which adjoin the surface of the conductor track, can be used for the formation of further inversion channels to other electrodes. Since the rectangular or square base area of a source / drain electrode has four corners, the density of transistors can be increased by a factor of up to two.

According to the invention, the transistor has a charge-storing layer between the gate electrode and the semiconductor substrate, in which electrical charges are locally bound. Such a transistor is suitable as a memory transistor for non-volatile semiconductor memories; by scattering high-energy charge carriers from an inversion channel, locally bound charge states are generated in the charge-storing layer above the first and / or to the second source / drain electrode. This storage mechanism is used in irror bit technology. The storage density that can be generated in this way can be doubled with the aid of the present invention, since charges are only stored in the charge-storing layer at corner areas instead of at edge areas of the source / drain electrodes. It is preferably provided that the second source / drain electrode is arranged offset from the first source / drain electrode by a distance which corresponds to the width of the first source / drain electrode along the first direction. The first and the second source / drain electrode thus adjoin two different, successive sections of the conductor track; the second source / drain electrode begins on the first side of the interconnect where the first source / drain electrode ends on the second side of the interconnect. This offset allows multiple source / drain electrodes to be lined up alternately on both sides of the conductor track. There is a distance between different inversion channels under the conductor path in the direction of the conductor path, which corresponds approximately to the optical resolution limit.

It is preferably provided that the first and second source / drain electrodes have a rectangular base area in the semiconductor substrate and that the transistor forms an inversion channel in the switched-on state, which is only between a single corner region of the first source / drain electrode, that of the second Source / drain electrode is facing, and a single corner region of the second source / drain electrode, which faces the first source / drain electrode, runs. Thus, two corner regions of the second source / drain electrode, which adjoin the conductor path in the direction and in the opposite direction of the conductor path, can each be used to form an inversion channel. In particular, the transistor forms an inversion channel that is narrower than half the width of the first or second source / drain electrode measured in the direction of the course of the conductor track. Accordingly, it is provided that the transistor electrical charges in the charge storage layer only at the corner region of the first source / drain electrode, which faces the second source / drain electrode, and / or at the corner region of the second source / drain electrode, which faces the first source / drain electrode, stores. The storage of electrical charges exclusively at corner regions of source / drain electrodes is achieved in that an electrical insulation layer between the semiconductor substrate and the charge-storing layer has a layer thickness which is so large that the electrical insulation layer only at corner regions of the source / drain -Electrodes can be tunneled through by electrical charges of an inversion channel.

A further development provides that the first and the second source / drain electrodes can be electrically biased against one another either positively or negatively. An inversion channel can then flow in both directions between the electrodes and, if the source-drain voltage is sufficiently high, can store digital information at the corner region of the first or second electrode.

It is preferably provided that a third source / drain electrode is provided, which is arranged on the same side of the conductor track as the first source / drain electrode and which is arranged offset in the first direction to the second source / drain electrode. As a result, an inversion channel can be formed between a corner region of the second source / drain electrode, which faces the third source / drain electrode, and a corner region of the third source / drain electrode, which faces the second source / drain electrode. The first and third source / drain electrodes are on the opposite side of the second source / drain electrode Arranged side of the conductor track and offset relative to the second source / drain electrode in mutually opposite directions, ie in the direction and in the opposite direction of the conductor track in the region of the second source / drain electrode. Thus, an inversion channel extending to the second source / drain electrode and thus a separate transistor can be formed between each of the first and third source / drain electrodes. The inversion channels of both transistors each reach different corner regions of the second source / drain electrode that are adjacent to the conductor track. The first and the third source / drain electrode preferably have a distance from one another which corresponds to the width of the second source / drain electrode in the direction of the course of the conductor track, ie along the first direction.

A fourth source / drain electrode is preferably provided, which is arranged on the same side of the conductor track as the second source / drain electrode and is arranged offset in the first direction to the third source / drain electrode. As a result, a further inversion channel can be formed between a corner region of the third source / drain electrode, which faces the fourth source / drain electrode, and a corner region of the fourth source / drain electrode, which faces the third source / drain electrode , In this way, as in the aforementioned embodiment, both corner regions of the third source / drain electrode adjacent to the conductor track can be used for the formation of one transistor each. Analogously, further source / drain electrodes can be lined up alternately on both sides of the conductor track, which results in a particularly dense arrangement of transistors, in particular memory transistors. It is preferably provided that the charge-storing layer is a nitride layer which is surrounded on both sides by electrical insulation layers. In particular, one oxide layer each can be provided on and below the nitride layer, the lower oxide layer simultaneously serving as a gate dielectric.

A further development of the invention provides that the semiconductor circuit adjacent to the second source / drain electrode has a further conductor track running parallel to the conductor track and a fifth source / drain electrode, the fifth source / drain electrode on that of the second source / drain -Electrode opposite side of the further conductor track is arranged and is arranged offset in the first direction to the second source / drain electrode. As a result, there is yet another inversion channel between a corner region of the second source / drain electrode, which faces the fifth source / drain electrode, and a corner region of the fifth source / drain electrode, which faces the second source / drain electrode formable. Thus, those corner regions of the second source / drain electrode that face away from the first conductor track and are adjacent to a further, second conductor track are also used to form transistors. With the help of additional conductor tracks and transistors formed on them, dense two-dimensional logic or memory circuits can be implemented.

It is preferably provided that a sixth source / drain electrode is provided, which faces a corner region of the second source / drain electrode. With the aid of the first, the third, the fifth and the sixth source / drain electrode, up to four inversion channels can be formed, each of which is connected to different corner regions of the second source / drain. Reach the electrode. While in conventional semiconductor circuits a maximum of two inversion channels can reach one and the same source / drain electrode, according to the invention up to 50% of the substrate surface previously required is saved.

The semiconductor circuit is preferably a non-volatile memory circuit in which digital information can be stored at each corner region of the second source / drain electrode. When using mirror bit technology, each of the inversion channels reaching the second source / drain electrode can additionally store further digital information at a corner region of a source / drain electrode adjacent to the second source / drain electrode.

Alternatively, the semiconductor circuit can be a logic subcircuit in which the first, the second and the fifth source / drain electrode and the two conductor tracks form two logic transistors connected in series. Even more complex logic circuits can be implemented with the help of a two-dimensional network of transistors formed on conductor tracks.

The invention is described below with reference to FIGS. 1 to 10. Show it:

FIG. 1 shows a cross-sectional view of a semiconductor circuit according to the invention with a transistor,

FIG. 2 shows a top view of the semiconductor circuit from FIG. 1, FIGS. 3 and 4 different alternatives for electrical contacting of the semiconductor circuit from FIG. 1,

FIGS. 5 and 6 further embodiments of the present invention with a plurality of source / drain electrodes,

Figures 7 and 8 are schematic plan views of a conventional and a semiconductor circuit according to the invention and

FIGS. 9 and 10 are circuit diagrams of special logic circuits, each of which can be implemented by a conventional or an inventive semiconductor circuit.

FIG. 1 shows a transistor 10 with a first 1 and a second source / drain electrode 2, which are formed in a semiconductor substrate 20. Between the two electrodes 1, 2 there is a conductor track 11 above the semiconductor substrate 20 which forms the gate electrode 7 in the region of the transistor 10. A lower oxide layer 14, which also forms the gate dielectric of the transistor, a charge-storing layer 13 and an upper oxide layer 15 are arranged between the conductor track 11 and the semiconductor substrate 20. The charge-storing layer 13 spatially binds charges Ql, Q2 which are scattered through the gate oxide layer 14 into the charge-storing layer, as a result of which digital information can be stored as locally bound amounts of charges Ql, Q2.

The first and second source / drain electrodes 1, 2 are, as shown in FIG. 2 in plan view, offset from one another in the direction of the course of the conductor track 11, ie the first direction x. In the direction x, the base area G of the first electrode 1 has a ^π width d. With a conventional one The second electrode 2 would also be arranged along the conductor track section d of the conductor track 11 in the transistor. In contrast, according to the invention, the second electrode 2 is offset in the direction x relative to the first, and preferably exactly by the distance d. As a result, the transistor channel Kl is not completely formed between the mutually facing edge regions of the electrodes 1, 2, but only between a corner region la of the first electrode and a corner region 2a of the second electrode 2. The channel Kl formed between these mutually facing corner regions la, 2a thus narrower than a conventional transistor channel and takes up less substrate area.

FIG. 3 shows a possible connection of a transistor according to the invention in nMOS construction (metal oxide semiconductor), in which the inversion channel K1 consisting of electrons flows from the first source / drain electrode 1 to the second source / drain electrode 2, which flows with a positive one electrical potential + V is biased with respect to the first electrode 1, which is, for example, at ground 0. As a result, the electrons of the inversion channel Kl are accelerated in the direction of the arrow shown and reach the charge-storing layer by scattering through the gate oxide layer, where they are spatially bound and form the amount of charge Q2. As shown in FIG. 3, the amount of charge Q2 is located in the charge-storing layer adjacent to the corner region 2a of the second source / drain electrode 2.

In the embodiment illustrated in Figure 4 of the nMOS transistor circuit of Figure 3, the first source / drain electrode 1 relative to the second 2 with a positive potential + V is biased so that the Elek ^t Ronen toward the first E- Electrode 1 accelerated and scattered into the charge-storing layer in the area of the corner region la of the first electrode 1 as the amount of charge Ql. Depending on the current direction of the transistor channel, a charge can thus be stored at a corner region 1a, 2a of the first or second source / drain electrode 1, 2. Only two corner areas la, 2a are involved in the inversion channel.

With a third 3 and a fourth source / drain electrode 4, as shown in FIG. 5, further inversion channels K2, K3 can be formed on the conductor track 11. The electrodes are alternately arranged offset on both sides of the conductor track 11. According to FIG. 5, an inversion channel K2 is formed between a corner region 2b of the second electrode, which faces the third source / drain electrode 3, and the corner region 3a thereof. A further inversion channel K3 runs analogously between corner regions 3b, 4a of the third and fourth source / drain electrodes 3, 4. Further source / drain electrodes can be arranged on the conductor track 11, with a further transistor channel per source / drain electrode is trainable.

It is also possible to use further corner regions of this source / drain electrode which face away from the conductor track 11 in order to form further transistors. 6 shows, in addition to the conductor 11, a further conductor 16, between which the second source / drain electrode 2 is located. The further conductor track 16 is designed in the same way as the conductor track 11 and adjoins the second 2, the fourth 4 and a fifth 5 and a sixth source / drain electrode 6, these four source / drain electrodes also being offset from one another and in alternating sequence to the left and right of d <= r further conductor track 16 are arranged. As a result, two further inversion channels K5, K6 proceeding from the second source / drain electrode can be formed, which between a corner region 2σ of the second electrode 2 and a corner region 5a of the fifth source / drain electrode 5 and between a corner region 2d of the second electrode and a corner region 6a of the sixth source / drain electrode. They can be used to store two further digital pieces of information by means of charge quantities Q5, Q6 scattered in a corresponding charge-storing layer under the further line 16 at the corner regions 2c, 2d. All of the transistors of the semiconductor circuit according to the invention shown or indicated in the figures can also be formed without a charge-storing layer, for example only with a gate dielectric 14 between the gate electrode 7 and the semiconductor substrate 20, in which case they are logic transistors or transistors can be used for any other circuits. In this case, the indicated amounts of charge Q1 to Q6 are omitted.

FIG. 7 shows a schematic top view of a conventional semiconductor circuit, which can be a logic subcircuit, for example. Three conductor tracks G 1, G 2, G 3 are shown, which serve as gate electrodes. Source / drain regions 1, 2, 5, 7 are shown between the conductor tracks and are arranged in two rows between the conductor tracks G1, G2, G3. In the conventional semiconductor circuit from FIG. 7, these source / drain electrodes are not offset from one another. Q denotes circular amounts of charge which are arranged in the charge storage layer along the entire edges of the source / drain regions. Accordingly, an inversion channel takes up the entire width of a source / drain region along the course of, for example, the conductor track G2. Di ^{Ω shown} in Figure 7 terschaltung represents a subcircuit of a NAND grid, in which three transistors are connected in series in the direction of the vertical arrow. A current through this series connection of three transistors can only flow if a gate voltage is applied in each of the transistors, as shown for example for the middle transistor with the gate electrode G2 by means of the horizontal arrow.

FIG. 8 shows a semiconductor circuit according to the invention, with which the subcircuit from FIG. 7 can be implemented with source / drain electrodes offset from one another in the direction of conductor tracks. Also shown are three conductor tracks G1, G2, G3 and several source / drain electrodes 1, 2, 3, 4, 5, 6, 7, of which, for example, the first, second, fifth and seventh source / drain electrodes are three in Series connected transistors can be connected, as shown by the diagonal arrow. In particular, the first and the second source / drain electrodes 1, 2 together with the conductor track G1 form a first transistor T and the second and fifth source / drain electrodes 2, 5 together with the second conductor track G2 form a second transistor T ' , The circuit functions in the same way as in FIG. 7, but can be arranged much closer together with other switching elements. In particular, FIG. 8 shows possible start and end points of further inversion channels, which are indicated by circles on the corner regions of the source / drain electrodes. As the comparison with FIG. 7 shows, these start and end areas of the inversion channels are packed much more densely.

The circuits shown in FIGS. 7 and 8 represent subcircuits of a NAND grid. FIGS. 9 and 10 show the complete circuit diagram of such a circuit. Three n-channel transistors N and further p-channel transistors P connected to common gate electrodes G1, G2 and G3 are shown, the subcircuit S corresponding to that of the three transistors in FIGS. 7, 8. The three n-channel transistors N are connected in series and connected to a signal output A. If even one of these three transistors is not conductive, the corresponding p-channel transistor, which is connected to the same gate line, is transparent and applies the potential of the signal output A to the operating voltage Vdd. When all three n-channel transistors are conductive, signal output A is grounded. The circuit shown in FIG. 10 has the same switching behavior, in which the signal output A is first connected to the operating voltage via a p-channel transistor P and only then, when the transistor P is switched off, possible gate voltages to the gate lines G1, G2 and G3 can be applied to earth the signal output A afterwards.

Any other logic subcircuit can be made with the present invention. The advantage of tightly packed inversion channels can be exploited in particular in the case of memory circuits in which information is stored in a charge-storing layer of the transistor or in another structure. LIST OF REFERENCE NUMBERS

1, 2, 3, 4, 5, 6 source / drain electrodes la, lb, 2a, ..., 6a corner areas

7 gate electrode

10 transistor

11 conductor track

13 charge-storing layer

14 lower oxide layer

15 upper oxide layer

16 further conductor tracks 20 semiconductor substrate A signal output

Gl, G2, G3 gate lines (conductor tracks)

Kl, ..., K6 inversion channels

N-channel transistors

P p-channel transistors

Ql, Q2, ..., Q6 charge quantities

T, T 'transistors

S subcircuit

Vdd operating voltage

Claims

claims

1. Integrated semiconductor circuit with a transistor (10) and with a conductor track (11),

- The second source / drain electrode (2) in the first direction (x) is arranged offset to the first source / drain electrode (1) and

- The transistor (10) between the gate electrode (7) and the semiconductor substrate (20) has a charge-storing layer (13) in which electrical charges (Ql, Q2) are locally bound.

2. Semiconductor circuit according to claim 1, characterized in that the second source / drain electrode (2) by a distance (d) which corresponds to the width of the first source / drain electrode (1) along the first direction (x) first source / drain electrode (1) is arranged offset.

3. Semiconductor circuit according to claim 1 or 2, characterized in that the first (1) and the second source / drain electrode (2) have a rectangular base area (G) in the semiconductor substrate (20) and that the transistor (10) has an inversion channel (Kl), which only between a corner area (la) of the first source / drain electrode (1) facing the second source / drain electrode (2) and a corner area (2a) of the second source / drain Electrode (2), which faces the first source / drain electrode (1), runs.

4. Semiconductor circuit according to one of claims 1 to 3, characterized in that the transistor (10) electrical charges (Ql; Q2) in the charge storage layer (13) exclusively at the corner region (la) of the first source / drain electrode (1) which faces the second source / drain electrode (2) and / or at the corner region (2a) of the second source / drain electrode (2) which faces the first source / drain electrode (1) ,

5. Semiconductor circuit according to one of claims 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the first (1) and the second source / drain electrode (2) are optionally positively or negatively biased electrically.

6. Semiconductor circuit according to one of claims 3 to 5, characterized in that a third source / drain electrode (3) is provided, which is arranged on the same side of the conductor track (11) as the first source / drain electrode (1) and which is offset in the first direction (x) to the second source / drain electrode (2).

7. Semiconductor circuit according to claim 6, characterized in that a fourth source / drain electrode (4) is provided, which is arranged on the same side of the conductor track (11) as the second source / drain electrode (2) and is offset in the first direction (x) to the third source / drain Electrode (3) is arranged.

8. Semiconductor circuit according to one of claims 4 to 7, that the charge-storing layer (13) is a nitride layer which is surrounded on both sides by electrical insulation layers (14, 15).

9. Semiconductor circuit according to one of claims 1 to 8, characterized in that the semiconductor circuit adjacent to the second source / drain electrode (2) a parallel to the conductor track (11) extending further conductor track (16) and a fifth source / drain electrode (5th ), the fifth source / drain electrode (5) being arranged on the side of the further conductor track (16) opposite the second source / drain electrode (2) and offset in the first direction (x) to the second source / drain -Electrode (2) is arranged.

10. A semiconductor circuit according to claim 9, characterized in that a sixth source / drain electrode (6) is provided, which a corner region (2d) of the second source / drain electrode (2) faces, so that with the aid of the first (1 ), the third (3), the fifth (5) and the sixth source / drain electrode (6) up to four inversion channels (K1, K2, K5, Kβ) can be formed, each of which has different corner areas (2a, 2b, 2c, 2d) of the second source / drain electrode (2).

11. Semiconductor circuit according to one of claims 1 to 10, characterized in that the semiconductor circuit is a non-volatile memory circuit in which at each corner region (2a, 2b, 2c, 2d) of the second source / drain electrode (2) each have digital information ( Q2, Q3, Q5, Q6) can be stored.

12. Semiconductor circuit according to claim 9 or 10, characterized in that the semiconductor circuit is a logic subcircuit in which the first (1), the second (2) and the fifth source / drain electrode (5) and the two conductor tracks (11, 16) form two logic transistors (T, T ') connected in series.