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EP1438740A2 - Method for packing electronic modules and multiple chip packaging - Google Patents

Method for packing electronic modules and multiple chip packaging

Info

Publication number
EP1438740A2
EP1438740A2 EP02776729A EP02776729A EP1438740A2 EP 1438740 A2 EP1438740 A2 EP 1438740A2 EP 02776729 A EP02776729 A EP 02776729A EP 02776729 A EP02776729 A EP 02776729A EP 1438740 A2 EP1438740 A2 EP 1438740A2
Authority
EP
European Patent Office
Prior art keywords
base plate
chip
power semiconductor
logic chip
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02776729A
Other languages
German (de)
French (fr)
Inventor
Kuno Wolf
Stephan Ernst
Robert Plikat
Wolfgang Feiler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1438740A2 publication Critical patent/EP1438740A2/en
Withdrawn legal-status Critical Current

Links

Classifications

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a packaging of electronic components, and in particular relates to a multi-chip packaging for packaging electronic assemblies, which consist of at least one power semiconductor chip and at least one logic chip.
  • At least one logic chip and at least one power semiconductor chip are commonly combined with electronic assemblies to perform a specific circuit function.
  • both types of chips that is, power semiconductor chips and logic chips
  • a compact housing or can be integrated into a compact package in order to reduce an overall sa tbaugroße and effort in Einset ⁇ wetting the from electronic chips and power semiconductor chips existing electronic assemblies to reduce.
  • the compact housing or the compact packaging serves to protect the electronic components contained therein from the ambient conditions in an application, on the other hand electrical and thermal contacts of the power semiconductor chips and / or the logic chips are realized with each other and with a base plate.
  • connection units of the power semiconductor chip and the connection units of the base plate are freely accessible, i. the corresponding connection units are not covered with plastic.
  • the metallic base plate carries at least one electrical potential of at least one power semiconductor chip, whereby potential differences or voltages of several hundred volts may occur, which may impair the functionality of logic chips or even destroy the logic chip completely. Furthermore, it is disadvantageous that these voltages can fluctuate transiently strongly, which leads to the fact that the logic chips must withstand transient voltages. This disadvantageously requires complex shielding measures on the logic chip.
  • the semiconductor process used to produce the logic chip must additionally be designed for high blocking voltages.
  • a method which attempts to circumvent this problem is described in DE 197 16 674 A1.
  • the circuit modules packaged in a housing (logic chips and power semiconductor chips) are distributed over a plurality of base plates which are electrically insulated from one another, thereby making it possible to keep high voltages or potential differences away from the sensitive logic chips.
  • a disadvantage of o.a. A method according to the prior art is that a plurality of baseplates electrically insulated from one another must be arranged side by side in a housing, so that only a smaller overall component area can be packaged for a given base area than if only one (electrically conductive, metallic ) Base plate, since the circuit modules must have a sufficient insulation distance from each other or from the edge of a base plate.
  • a disadvantage of this method and this device is that a ceramic reduces the thermal conductivity of the packaging, whereby a heat dissipation from the circuit modules is difficult.
  • Another disadvantage of the above-mentioned method consists in a complicated manufacture of the ceramic, whereby the module package is associated with higher costs, as a module package, which is based on a single metallic base plate.
  • An essential idea of the invention is that different circuit modules, such as logic chips and power semiconductor chips are combined in a common packaging, wherein the at least one logic chip and the at least one power semiconductor chip are arranged on a common, generally metallic base plate.
  • a particular advantage of the present invention is that with a given housing size a larger Total chip surface is packable, as d in packaging according to the state of Tecnnik with separate base plates for each module is feasible.
  • the method of the invention for packaging electronic assemblies essentially comprises the following steps:
  • first and second terminals for connecting power semiconductor chips and logic chips and at least one base plate terminal unit for the electrical connection of the base plate are left free.
  • electrical isolation of the logic chip from the baseplate is provided by a dielectric layer applied to the logic chip.
  • the dielectric layer isolates portions or the entirety of the logic chip from the baseplate, providing on the dielectric layer a metallization layer for soldering the logic chip layer assembly to the metal baseplate.
  • electrical isolation of the logic chip from the base plate is provided by bonding the logic chip to the base plate by means of an electrically insulating adhesive. Conveniently, portions or the entirety of the logic chip are isolated by the adhesive layer between the logic chip and the metal baseplate.
  • electrically insulating spacers are inserted into an adhesive layer consisting of the adhesive in order to provide a uniform spacing between the logic chip and the baseplate.
  • the at least one logic chip is soldered onto the baseplate by means of a metallization layer applied to the dielectric layer of the logic chip and by means of a second solder.
  • the dielectric layer and the metallization layer are successively applied to one side (for example, the bottom side) of the logic chip in a coating process.
  • a high thermal conductivity between the power semiconductor chip and the base plate is provided by the first solder, advantageously a thermal energy is dissipated by the power semiconductor chip to the base plate, whereby a Enticar- achieved power semiconductor chip becomes.
  • a high electrical conductivity between the power semiconductor chip and the base plate is provided by the first solder.
  • current transport between the power semiconductor chip and the baseplate is provided by the first solder without a significant voltage drop since the first solder has low electrical resistance.
  • electrical insulation of the logic chip from the baseplate is provided by an SOI substrate, wherein SOI is a silicon deposition on an insulator (silicon on insulator).
  • a power semiconductor chip in the multiple chip package according to the invention is combined with at least two different logic chips in order to provide a multiple chip package.
  • combinations of adhesive bonds of the at least one logic chip to the baseplate and solder connections between the baseplate and a metallization layer applied to the dielectric layer of at least one further logic chip are provided.
  • the erf Dungsgepurposee multiple chip packaging further has:
  • a base plate which is preferably formed as a unit of a preferably metallic material such as copper, for example;
  • the inventive Menrfachchipverpackung in place of the above feature b) at least e arranged on the base plate logic chip, said at least e ne logic chip with a dielectric layer for electrical Insulation of at least parts of the logic chip of the base plate is coated, the dielectric layer is coated with a metallization layer and the metallization layer is soldered by means of a second solder on the base plate.
  • the multiple chip package according to the invention further has:
  • At least one logic chip arranged on the base plate, wherein the at least one logic chip is coated with a dielectric layer for dielectric isolation of at least parts of the logic chip from the base plate, the dielectric layer is coated with a metallization layer and the metallization layer is applied to the metallization layer by means of a second solder Base plate is soldered;
  • Figure 1 shows a multi-chip package without molding compound or without Kunststoffverguss with a logic chip and a power semiconductor chip, which are connected by signal transmission lines and on a
  • Base plate arranged as a side sectional view taken along a line A-A 'of Figure 3 according to a preferred embodiment of the present invention
  • FIG. 2 shows a multiple chip package of a side
  • Figure 3 is a plan view of a multiple chip package according to a preferred embodiment of the present invention.
  • FIG. 4 a shows a plan view of a multiple-chip package with an applied Moidmasse or a bracenen Kunststoffverguss according to a preferred embodiment of the present invention.
  • FIG. 4b shows a side view of a multi-chip package with applied molding compound or applied plastic Substance casting of Figure 4a according to a preferred embodiment of the present invention.
  • the molding compound or plastic encapsulation 120 (explained below with reference to FIGS. 4 a and 4 b) has been omitted for reasons of clarity.
  • the illustrated multiple chip package consists of two circuit modules, i. a logic chip 102 and a power semiconductor chip 103, which according to the invention are arranged on a common base plate 101.
  • the power semiconductor chip 103 must have the highest possible thermal and highest possible electrical conductivity with the base plate 101, which is generally formed as a metallic base plate is to be connected.
  • the power semiconductor chip 103 is soldered onto the base plate 101 by means of a first solder 105 (hatched in FIG. 1).
  • the base plate has a base plate connection unit 112 which is left free after encapsulation of the overall arrangement with a molding compound and which provides one of several possible electrical connections to the power semiconductor chip 103.
  • FIG. 1 shows a logic chip 102 which, as mentioned above, must be decoupled from the electrical potential of the power semiconductor chip 103 carried by the baseplate 101.
  • this is achieved by gluing the logic chip 102 onto the base plate 101 by means of an adhesive 106, which is electrically insulating.
  • an adhesive 106 which is electrically insulating.
  • One of a plurality of signal transmission lines is shown as a signal transmission line 104a for electrically connecting the power semiconductor chip 103 to the logic chip 102. Further signal transmission lines serve to connect respectively the logic chip 102 and the power semiconductor chip 103 with first and second connection units 111 and 113 (shown in FIG. 3). In this way, a multi-chip package 100 is achieved by way of example with two circuit modules, the logic chip 102 and the power semiconductor chip 103 in an advantageous compact design or housing form.
  • FIG. 2 illustrates a further preferred embodiment of the present invention, FIG. 2 again showing, by way of example, two circuit modules, ie a logic chip 102 and a power semiconductor chip 103, which are electrically connected to one another by a signal transmission line 104a.
  • the application of the power semiconductor chip 103 on the base plate 101 is realized as shown with reference to Figure 1, while the logic chip 102 is applied in other ways electrically insulating on the uniform, metallic base plate 101.
  • a dielectric layer 109 is applied to its underside, which is electrically insulating.
  • a metallization layer 201 is applied, which serves as a solderable connection element to the metallic base plate 101.
  • a uniform, flat dielectric layer 109 may be provided, for example, by a thermal oxidation process or a deposition process in chip-sharing.
  • SOI substrate silicon on insulator
  • a semiconductor material is located above and below the dielectric layer 109, and the metal layer 201 is deposited on the underside of the semiconductor material disposed below the dielectric layer 109.
  • FIG. 3 shows a multiple-chip package 100, in which a logic chip 102 and a power semiconductor chip 103 are enclosed, in a plan view, wherein a molding compound 120 has been omitted for reasons of clarity. How m
  • a signal transmission line 104d serves to connect the power semiconductor chip 103 to the second connection unit 113.
  • Another connection of the power semiconductor chip 103 is realized via the base plate to the base plate terminal 112 by soldering the power semiconductor chip 103 onto the base plate 101 by means of an electrically conductive adhesive 105, as described above with reference to FIG.
  • the signal transmission lines 104a-104e only by way of example s nd, that is, fewer or more than five signal transmission lines 104a-104e may be present.
  • the power semiconductor cluster 103 may be configured, for example, as an IGBT (Insulated Gate Bipolar Transistor) for ignition applications, wherein the logic chip 102 includes the associated logic circuitry, an ESD (Electrostatic Discharge) protection circuit, and a current control circuit.
  • the base plate terminal 112 provides a terminal tag connected to a collector of the IGBT to which an ignition coil can be connected, the second terminal 113 being on a reference potential, and the first terminal unit 111 serving as a control terminal.
  • the control signal applied to the first terminal unit 111 is forwarded via the signal transmission line 104c, the logic chip 102 and the signal transmission line 104a to the gate of the IGBT (the power semiconductor chip 103).
  • a signal proportional to the coil current of the ignition coil is returned by the IGBT 103 to the current control circuit implemented on the logic chip 102. This can prevent exceeding of a limit value of the Spuienstro flowing through the ignition coil by reducing the gate voltage supplied to the IGBT via the signal transmission line 104a.
  • FIGS. 4a and 4b show a multi-chip package 100 with an applied molding compound 120 or an applied plastic encapsulation, so that complete packaging of the circuit modules shown with reference to FIGS. 1 to 3, ie the logic chip 102 and the power semiconductor chip 103 is provided.
  • FIG. 4b a side view of FIG. 4a is shown.
  • the molding compound 120 for packaging the electronic assembly consisting of the at least one power semiconductor chip 103 and the at least one logic chip 102 has at least one base plate terminal unit 112 of the base plate 101 and the ends of the first and of the modules facing away from the modules 102 and 103, respectively second connection units 111 and 113 leaves free.
  • the base plate 101 itself has a high electrical and a high thermal conductivity, wherein the base plate is preferably made of a metallic material such as a copper material or a copper alloy.
  • External circuit units are preferably connected to the base plate connection unit 112 and to the first connection unit 111 and the second connection unit 113.
  • the method according to the invention for packaging electronic assemblies, in which power semiconductor chips and logic chips can be combined, as well as the multiple chip package according to the invention makes an arrangement of individual components

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention relates to a method for packing electronic modules, and to a multiple chip packaging (100). According to the invention, at least one power semiconductor chip (103) is applied to a base plate (101) using a first solder (105), at least one logical chip (102) is applied to the base plate (101), the logical chip and the base plate being arranged in such a way that they are electrically isolated from each other, at least one logical chip (102) is connected to the at least one power semiconductor chip (103) by means of signal transmission lines (104a-104e), and the electronic module consisting of the at least one power semiconductor chip (103) and the at least one logical chip (102) is packed by means of a moulding material (120) in order to provide a multiple chip packaging (100).

Description

Verfahren zum Verpacken von elektronischen Baugruppen und MenrfachchipVerpackungMethod for packaging electronic assemblies and multi-chip packaging
STAND DER TECHNIKSTATE OF THE ART
Die vorliegende Erfindung betrifft eine Verpackung von elek- tronischen Bauelementen, und betrifft insbesondere eine Mehr- fachchipverpackung zum Verpacken von elektronischen Baugruppen, die aus mindestens einem Leistungshalbleiterchip und mindestens einem Logikchip bestehen.The present invention relates to a packaging of electronic components, and in particular relates to a multi-chip packaging for packaging electronic assemblies, which consist of at least one power semiconductor chip and at least one logic chip.
Bei einer Auslegung von elektronischen Bauelementen, insbesondere von Halbleiterbauelementen, ist es vorteilhaft, Lei- stungshalbleiterchips und Logikchips als voneinander getrennte Chips auszufuhren, da die entsprechenden Halbleiterprozes- se individuell für beide Funktionalitäten (Leistungshalblei- terchipoπentierte Funktionalitäten bzw. Logikchiporientierte Funktionalitäten) optimiert werden können.In the case of a design of electronic components, in particular of semiconductor components, it is advantageous to design power semiconductor chips and logic chips as separate chips, since the corresponding semiconductor processes can be optimized individually for both functionalities (power semiconductor-functionalities or logic chip-oriented functionalities).
Auf der anderen Seite ist m elektronischen Baugruppen gewohnlich mindestens einen Logikchip und mindestens einen Leistungshalbleiterchip kombiniert, um eine spezifische Schaltungsfunktion auszufuhren.On the other hand, at least one logic chip and at least one power semiconductor chip are commonly combined with electronic assemblies to perform a specific circuit function.
Es ist somit wirtschaftlich vorteilhaft, dass beide Chiparten, d.h. Leistungshalbleiterchips und Logikchips, als eine funktionale Einheit m einem kompakten Gehäuse bzw. in einer kompakten Verpackung integriert werden können, um eine Ge- sa tbaugroße zu reduzieren und einen Aufwand bei der Einset¬ zung der aus Logikchips und Leistungshalbleiterchips bestehenden elektronischen Baugruppen zu verringern. Das kompakte Gehäuse bzw. die kompakte Verpackung dient dabei einem Schutz der m ihr enthaltenen elektronischen Baugruppen vor den Umgebungsbedingungen bei einer Anwendung, andererseits müssen elektrische und thermische Kontaktierungen der Leistungshalbleiterchips und/oder der Logikchips untereinander und mit einer Grundplatte realisiert werden.Thus, it is economically advantageous that both types of chips, that is, power semiconductor chips and logic chips, as a functional unit m a compact housing or can be integrated into a compact package, in order to reduce an overall sa tbaugroße and effort in Einset ¬ wetting the from electronic chips and power semiconductor chips existing electronic assemblies to reduce. The compact housing or the compact packaging serves to protect the electronic components contained therein from the ambient conditions in an application, on the other hand electrical and thermal contacts of the power semiconductor chips and / or the logic chips are realized with each other and with a base plate.
Hierbei treten insbesondere bei Leistungshalbleiterchips hohe Verlustleistungen auf, die beispielsweise über die Ruckseite des Leistungshalbleiterchips an die Umgebung bzw. an eine thermisch leitfahige Grundplatte abgegeben werden müssen, so dass eine überhitzung des Leistungshalbleiterchips vermieden wird.In this case, in particular in the case of power semiconductor chips, high power losses occur which, for example, have to be released to the environment or to a thermally conductive baseplate via the reverse side of the power semiconductor chip, so that overheating of the power semiconductor chip is avoided.
In herkömmlicher Weise werden Leistungshalbleiterchips auf eine Seite einer üblicherweise aus Metall bestehenden Grundplatte aufgelotet, wobei die Grundplatte mit einer oder meh- reren Anschlussεinheiten ausgebildet ist, um das Leistungshalbleiterchip über seine Ruckseite elektrisch an externe Schaltungsemheiten anzukoppeln. Weitere Verbindungs- anschlüssse des Leistungshalbleiterchips werden über weitere Anschlusseinheiten mit metallischen Kontaktfahnen versehen und nach außen geführt. Nach einem Vergießen der elektronischen Baugruppe mit einer Moldmasse (z.B. Kunststoff erguss bzw. Kunststoffvergussmasse) sind die Anschlusseinhεiten des Leistungshalbleiterchips sowie die Anschlusseinheiten der Grundplatte frei zuganglich, d.h. die entsprechenden An- Schlusseinheiten sind nicht mit Kunststoff überzogen.In a conventional manner, power semiconductor chips are soldered onto one side of a base plate, which is usually made of metal, wherein the base plate is formed with one or more connection units in order to electrically connect the power semiconductor chip to external circuit units via its rear side. Further connection terminals of the power semiconductor chip are provided with metal contact lugs via further connection units and led outwards. After casting the electronic assembly with a molding compound (for example plastic or plastic casting compound), the connection units of the power semiconductor chip and the connection units of the base plate are freely accessible, i. the corresponding connection units are not covered with plastic.
Sollen Logikchips zusammen mit Leistungshalbleiterchips in einer einzigen Verpackung angeordnet werden, tritt nach dem Stand der Technik das Problem auf, dass die metallische Grundplatte mindestens ein elektrisches Potential mindestens eines Leistungshalbleiterchips fuhrt, wobei Potentialdifferenzen bzw. Spannungen von mehreren hundert Volt auftreten können, welche die Funktionsfahigkeit von Logikchips beeinträchtigen können bzw. den Logikchip sogar vollständig zer- stören können. Weiterhin ist es nachteilig, dass diese Spannungen transient stark schwanken können, was dazu fuhrt, dass die Logilchips honen transienten Spannungen widerstehen müssen. Dies erfordert in nachteiliger Weise aufwendige Abschirmmaßnahmen auf dem Logikchip.If logic chips are to be arranged together with power semiconductor chips in a single package, the problem arises in the prior art that the metallic base plate carries at least one electrical potential of at least one power semiconductor chip, whereby potential differences or voltages of several hundred volts may occur, which may impair the functionality of logic chips or even destroy the logic chip completely. Furthermore, it is disadvantageous that these voltages can fluctuate transiently strongly, which leads to the fact that the logic chips must withstand transient voltages. This disadvantageously requires complex shielding measures on the logic chip.
Unzweckmaßigerweise muss der zur Erzeugung des Logikchips verwendete Halbleiterprozess zusätzlich für hohe Sperrspannungen ausgelegt werden.Inexpediently, the semiconductor process used to produce the logic chip must additionally be designed for high blocking voltages.
Ein Verfahren, mit welchem versucht wird, dieses Problem zu umgehen, ist m der DE 197 16 674 AI beschrieben. Hierbei werden die m einem Gehäuse verpackten Schaltungsmodule (Logikchips und Leistungshalbleiterchips) auf mehrere elektrisch voneinander isolierte Grundplatten verteilt, wodurch es ermöglicht wird, αass hohe Spannungen bzw. Potentialdifferenzen von den empfindlichen Logikchips ferngehalten werden. Ein Nachteil des o.a. Verfahrens nach dem Stand der Technik besteht darin, dass mehrere, elektrisch voneinander isolierte Grundplatten in einem Gehäuse nebeneinander angeordnet werden m ssen, so dass bei einer vorgegebenen Grundflache nur eine kleinere Gesamtbauelementflache verpackt werden kann, als bei einem Vorhandensein nur einer (elektrisch leitenden, metallischen) Grundplatte, da die Schaltungsmodule untereinander bzw. vom Rand einer Grundplatte einen ausreichenden Isola- tionsabstand aufweisen müssen.A method which attempts to circumvent this problem is described in DE 197 16 674 A1. In this case, the circuit modules packaged in a housing (logic chips and power semiconductor chips) are distributed over a plurality of base plates which are electrically insulated from one another, thereby making it possible to keep high voltages or potential differences away from the sensitive logic chips. A disadvantage of o.a. A method according to the prior art is that a plurality of baseplates electrically insulated from one another must be arranged side by side in a housing, so that only a smaller overall component area can be packaged for a given base area than if only one (electrically conductive, metallic ) Base plate, since the circuit modules must have a sufficient insulation distance from each other or from the edge of a base plate.
Ein weiteres Verfahren und eine Vorrichtung zum Verpacken von Schaltungsmodulen nach dem Stand der Technik ist in der Lite- raturstelle PCIM 2000, Conference Proceedmgs, PC7.2 unter dem Titel "Power Semiconductor Packaging - Problem or res- source ?, From the State of the art to future trends" besenrieben, wobei hier an Stelle einer metallischen Grundplatte eine metallisierte Keramikgrundplatte eingesetzt wird.Another prior art method and apparatus for packaging circuit modules is disclosed in the paper PCIM 2000, Conference Proceeds, PC7.2 entitled "Power Semiconductor Packaging - Problem or Resource ?, From the State of the Art art to future trends ", in which case a metallized ceramic base plate is used instead of a metallic base plate.
Durch em gezieltes Strukturieren der Metallisierung auf der Grundplatte lasst sich eine elektrische Entkopplung der Ruck- seiten von Leistungs- bzw. Logikchips erreichen. Ein Nachteil dieses Verfahrens und dieser Vorrichtung besteht darin, dass eine Keramik die thermische Leitfähigkeit der Verpackung verringert, wodurch eine Warmeabfuhr von den Schaltungsmodulen erschwert wird. Ein weiterer Nachteil des o.a. Verfahrens besteht in einer aufwendigen Herstellung der Keramik, wodurch die Modulverpackung mit höheren Kosten verbunden ist, als eine Modulverpackung, welche auf einer einzigen metallischen Grundplatte beruht.By em targeted structuring of the metallization on the base plate can be an electrical decoupling of the jerk pages of power or logic chips. A disadvantage of this method and this device is that a ceramic reduces the thermal conductivity of the packaging, whereby a heat dissipation from the circuit modules is difficult. Another disadvantage of the above-mentioned method consists in a complicated manufacture of the ceramic, whereby the module package is associated with higher costs, as a module package, which is based on a single metallic base plate.
Es ist somit ein Problem der vorliegenden Erfindung, ein Verfahren zum Verpacken von Schaltungsmodulen und eine Mehrfachchipverpackung bereitzustellen, wobei mindestens ein Logikchip und mindestens ein Leistungshalbleiterchip auf einer einheitlichen metallischen Grundplatte in einer Mehrfachchipverpackung kombiniert werden.It is thus a problem of the present invention to provide a method of packaging circuit modules and a multi-chip package wherein at least one logic chip and at least one power semiconductor chip are combined on a unitary metallic base plate in a multi-chip package.
VORTEILE DER ERFINDUNGADVANTAGES OF THE INVENTION
Die Erfindung schafft das im Patentanspruch 1 angegebeneThe invention provides that specified in claim 1
Verfahren zum Verpacken von elektronischen Baugruppen sowie Mehrfachchipverpackungen mit den Merkmalen der Patentansprüche 10, 11 und 12.Method for packaging electronic assemblies and multiple chip packages having the features of claims 10, 11 and 12.
Weitere Ausgestaltungen der Erfindung ergeben sich aus den Unteransprüchen .Further embodiments of the invention will become apparent from the dependent claims.
Ein wesentlicher Gedanke der Erfindung besteht darin, dass unterschiedliche Schaltungsmodule, wie beispielsweise Logik- chips und Leistungshalbleiterchips in einer gemeinsamen Verpackung kombiniert werden, wobei das mindestens eine Logikchip und das mindestens eine Leistungshalbleiterchip auf einer gemeinsamen, im allgemeinen metallischen Grundplatte angeordnet werden.An essential idea of the invention is that different circuit modules, such as logic chips and power semiconductor chips are combined in a common packaging, wherein the at least one logic chip and the at least one power semiconductor chip are arranged on a common, generally metallic base plate.
Ein besonderer Vorteil der vorliegenden Erfindung besteht darin, dass bei einer vorgegebenen Gehäusegröße eine größere Gesamtchipflache verpackbar ist, als d es bei Verpackungen nach dem Stand der Tecnnik mit separaten Grundplatten für die einzelnen Module realisierbar ist.A particular advantage of the present invention is that with a given housing size a larger Total chip surface is packable, as d in packaging according to the state of Tecnnik with separate base plates for each module is feasible.
Das erf dungsgerαaße Verfahren zum Verpacken von elektronischen Baugruppen weist im wesentlichen die folgenden Schritte auf :The method of the invention for packaging electronic assemblies essentially comprises the following steps:
a) Aufbringen mindestens eines Leistungshalbleiterchips auf einer Grundplatte mit einem ersten Lotmittel;a) applying at least one power semiconductor chip on a base plate with a first solder;
b) Aufbringen mindestens eines Logikch ps auf der Grundplatte, wobei das Logikchip und die Grundplatte derart angeordnet werden, dass eine elektrische Isolierung zwischen dem minde- stens einen Logikchip und der Grundplatte bereitgestellt wird;b) applying at least one logic chip on the baseplate, the logic chip and the baseplate being arranged to provide electrical isolation between the at least one logic chip and the baseplate;
c) Verbinden des mindestens einen Logikchips mit dem mindestens einen Leistungshalbleiterchip mittels Signalubertra- gungsleitungen und Verbinden jeweils des mindestens einenc) connecting the at least one logic chip to the at least one power semiconductor chip by means of signal transmission lines and connecting each of the at least one
Logikchips und des mindestens einen Leistungshalbleiterchips mit entsprechenden ersten und zweiten Anschlussemheiten; undLogic chips and the at least one power semiconductor chip with corresponding first and second terminal units; and
d) Verpacken der aus dem mindestens einen Leistungshalblei- terchip und dem mindestens einen Logikchip bestehenden elektronischen Baugruppe mittels einer Moldmasse bzw. einem Kunststoffverguss, um eine Mehrfachchipverpackung zu erhalten und die der Mehrfachchipverpackung vorhandenen Leistungshalbleiterchips und Logikchips vor Umwelteinflüssen zu schut- zen.d) packaging of the at least one power semiconductor chip and the at least one logic chip existing electronic assembly by means of a molding compound or a Kunststoffverguss to obtain a multi-chip packaging and protect the multi-chip packaging existing power semiconductor chips and logic chips from environmental influences.
In vorte lnafter Weise werden erste und zweite Anscnlusse - heiten zum Anschluss von Leistungshalbleiterchips und Logikchips sowie mindestens eine Grundplattenanschlussemheit zum elektrischen Anschluss der Grundplatte freigelassen. In den ünteransprüchen finden sich vorteilhafte Weiterbildungen und Verbesserungen des jeweiligen Gegenstandes der Erfindung .In the first instance, first and second terminals for connecting power semiconductor chips and logic chips and at least one base plate terminal unit for the electrical connection of the base plate are left free. In the dependent claims are advantageous developments and improvements of the respective subject of the invention.
Gemäß einer bevorzugten Weiterbildung der vorliegenden Erfindung wird eine elektrische Isolierung des Logikchips von der Grundplatte durch eine auf das Logikchip aufgebrachte dielektrische Schicht bereitgestellt. In vorteilhafter Weise isoliert die dielektrische Schicht bzw. die dielektrische Isola- tionsschicht Teile oder die Gesamtheit des Logikchips von der Grundplatte, wobei auf die dielektrische Schicht eine Metallisierungsschicht für eine Lötverbindung der Logikchip- Schicht-Anordnung mit der metallischen Grundplatte bereitgestellt wird.According to a preferred development of the present invention, electrical isolation of the logic chip from the baseplate is provided by a dielectric layer applied to the logic chip. Advantageously, the dielectric layer isolates portions or the entirety of the logic chip from the baseplate, providing on the dielectric layer a metallization layer for soldering the logic chip layer assembly to the metal baseplate.
Gemäß einer weiteren bevorzugten Weiterbildung der vorliegenden Erfindung wird eine elektrische Isolierung des Logikchips von der Grundplatte durch eine Klebung des Logikchips auf die Grundplatte mittels eines elektrisch isolierenden Klebemit- tels bereitgestellt. Zweckmäßigerweise werden Teile oder die Gesamtheit des Logikchips durch die Klebeschicht zwischen dem Logikchip und der metallischen Grundplatte isoliert.According to a further preferred development of the present invention, electrical isolation of the logic chip from the base plate is provided by bonding the logic chip to the base plate by means of an electrically insulating adhesive. Conveniently, portions or the entirety of the logic chip are isolated by the adhesive layer between the logic chip and the metal baseplate.
Gemäß noch einer weiteren bevorzugten Weiterbildung der vor- liegenden Erfindung werden zur elektrischen Isolierung des Logikchips von der Grundplatte elektrisch isolierende Abstandshalter in eine aus dem Klebemittel bestehende Klebeschicht eingebracht, um einen gleichförmigen Abstand zwischen dem Logikchip und der Grundplatte bereitzustellen.In accordance with yet another preferred development of the present invention, in order to electrically insulate the logic chip from the baseplate, electrically insulating spacers are inserted into an adhesive layer consisting of the adhesive in order to provide a uniform spacing between the logic chip and the baseplate.
Gemäß noch einer weiteren bevorzugten Weiterbildung der vorliegenden Erfindung wird das mindestens eine Logikchip mittels einer auf die dielektrische Schicht des Logikchips aufgebrachten Metallisierungsschicht und mittels eines zweiten Lötmittels auf die Grundplatte gelötet. In vorteilhafterIn accordance with yet another preferred development of the present invention, the at least one logic chip is soldered onto the baseplate by means of a metallization layer applied to the dielectric layer of the logic chip and by means of a second solder. In an advantageous manner
Weise wird durch das zweite Lotmittel eine zuverlässige Lötverbindung bereitgestellt, wobei eine zuverlässige elektri- sehe Isolation zwischen dem Logikchip und der Grundplatte durch die dielektrische Schicht sichergestellt ist. In zweckmäßiger Weise werden die dielektrische Schicht und die Metallisierungsschicht aufeinanderfolgend auf eine Seite (bei- spielsweise die Unterseite) des Logikchips in einem Beschich- tungsprozess aufgebracht.In this way, a reliable solder connection is provided by the second solder, whereby a reliable electrical connection is achieved. see isolation between the logic chip and the base plate is ensured by the dielectric layer. Conveniently, the dielectric layer and the metallization layer are successively applied to one side (for example, the bottom side) of the logic chip in a coating process.
Gemäß noch einer weiteren bevorzugten Weiterbildung der vorliegenden Erfindung wird durch das erste Lötmittel eine hohe thermische Leitfähigkeit zwischen dem Leistungshalbleiterchip und der Grundplatte bereitgestellt, in vorteilhafter Weise wird dadurch eine thermische Energie von dem Leistungshalbleiterchip zu der Grundplatte abgeführt, wodurch eine Entwär- mung des Leistungshalbleiterchips erreicht wird.According to yet another preferred development of the present invention, a high thermal conductivity between the power semiconductor chip and the base plate is provided by the first solder, advantageously a thermal energy is dissipated by the power semiconductor chip to the base plate, whereby a Entwär- achieved power semiconductor chip becomes.
Gemäß noch einer weiteren bevorzugten Weiterbildung der vorliegenden Erfindung wird durch das erste Lötmittel eine hohe elektrische Leitfähigkeit zwischen dem Leistungshalbleiterchip und der Grundplatte bereitgestellt. In vorteilhafter Weise wird durch das erste Lötmittel ein Stromtransport zwischen dem Leistungshalbleiterchip und der Grundplatte ohne einen nennenswerten Spannungsabfall bereitgestellt, da das erste Lötmittel einen niedrigen elektrischen Widerstand aufweist .According to yet another preferred development of the present invention, a high electrical conductivity between the power semiconductor chip and the base plate is provided by the first solder. Advantageously, current transport between the power semiconductor chip and the baseplate is provided by the first solder without a significant voltage drop since the first solder has low electrical resistance.
Gemäß noch einer weiteren bevorzugten Weiterbildung der vorliegenden Erfindung wird eine • elektrische Isolierung des Logikchips von der Grundplatte durch ein SOI-Substrat bereitgestellt, wobei als SOI eine Siliziumaufbringung auf einem Isolator (Silizium-auf-Isolator; Silicon on Insulator) bezeichnet wird.In accordance with yet another preferred development of the present invention, electrical insulation of the logic chip from the baseplate is provided by an SOI substrate, wherein SOI is a silicon deposition on an insulator (silicon on insulator).
Gemäß noch einer weiteren bevorzugten Weiterbildung der vorliegenden Erfindung wird ein Leistungshalbleiterchip in der erfindungsgemäßen Mehrfachchipverpackung mit mindestens zwei unterschiedlichen Logikchips kombiniert, um eine Mehrfachchipverpackung bereitzustellen. In vorteilhafter Weise werden hierbei Kombinationen von Klebeverbindungen des mindestens einen Logikchips mit der Grundplatte und Lotverbindungen zwischen der Grundplatte und einer auf die dielektπscne Schicht mindestens eines weiteren Logikchips aufgebrachten Metallis erungsschicht bereitgestellt.In accordance with yet another preferred development of the present invention, a power semiconductor chip in the multiple chip package according to the invention is combined with at least two different logic chips in order to provide a multiple chip package. In an advantageous way In this case, combinations of adhesive bonds of the at least one logic chip to the baseplate and solder connections between the baseplate and a metallization layer applied to the dielectric layer of at least one further logic chip are provided.
Die erf dungsgemaße Mehrfachchipverpackung weist weiterhin auf:The erf Dungsgemaße multiple chip packaging further has:
a) eine Grundplatte, welche vorzugsweise als eine Einheit aus einem vorzugsweise metallischen Material wie oeispielsweise Kupfer ausgebildet ist;a) a base plate, which is preferably formed as a unit of a preferably metallic material such as copper, for example;
b) mindestens ein auf der Grundplatte angeordnetes Logikchip, wobei das mindestens eine Logikchip mit einem Klebemittel elektrisch isolierend auf die Grundplatte geklebt ist;b) at least one logic chip arranged on the base plate, wherein the at least one logic chip is glued to the base plate with an adhesive in an electrically insulating manner;
c) mindestens ein auf der Grundplatte angeordnetes Leistungshalbleiterchip, wobei das mindestens eine Leistungshalblei- terchip mit einem elektriscn und thermisch le tfahigen Lotmittel auf die Grundplatte gelotet ist;c) at least one power semiconductor chip arranged on the base plate, wherein the at least one power semiconductor chip is soldered to the base plate with an electrically and thermally conductive solder.
d) Signalubertragungsleitungen zur elektrischen Verbindung des Logikchips mit dem Leistungshalbleiterchip sowie zur elektrischen Verbindung des Logikchips und des Leistungshalö- leiterchips mit ersten und zweiten Anschlussemheiten; undd) signal transmission lines for the electrical connection of the logic chip to the power semiconductor chip and for the electrical connection of the logic chip and the Leistungshalö- conductor chip with first and second Anschlußemheiten; and
e) eine Moldmasse als eine Kunststoffvergussmasse zur Verpak- kung der aus der Grundplatte, dem mindestens einen Leistungs- halbleiterchip und dem mindestens einen Logikcnip bestehenden elektronischen Baugruppe, um dieselbe vor Umwelteinflüssen zu schützen.e) a molding compound as a Kunststoffvergussmasse for packaging of the base plate, the at least one power semiconductor chip and the at least one Logikcnip existing electronic assembly to protect the same from environmental influences.
Weiterhin weist die erfmdungsgemaße Menrfachchipverpackung an Stelle des o.a. Merkmals b) mindestens e auf der Grundplatte angeordnetes Logikchip auf, wobei das mindestens e ne Logikchip mit einer dielektrischen Schicht zur elektrischen Isolation von zumindest Teilen des Logikchips von der Grundplatte beschichtet ist, die dielektrische Schicht mit einer Metallisierungsschicht beschichtet ist und die Metallisie- rungsschicht mittels eines zweiten Lötmittels auf die Grund- platte gelötet ist.Furthermore, the inventive Menrfachchipverpackung in place of the above feature b) at least e arranged on the base plate logic chip, said at least e ne logic chip with a dielectric layer for electrical Insulation of at least parts of the logic chip of the base plate is coated, the dielectric layer is coated with a metallization layer and the metallization layer is soldered by means of a second solder on the base plate.
Die erfindungsgemäße Mehrfachchipverpackung weist weiterhin auf:The multiple chip package according to the invention further has:
a) eine Grundplatte;a) a base plate;
b) mindestens ein auf der Grundplatte angeordnetes Logikchip, wobei das mindestens eine Logikchip mit einem Klebemittel und elektrisch isolierenden Abstandshaltern -elektrisch isolierend auf die Grundplatte geklebt ist;b) at least one logic chip arranged on the base plate, the at least one logic chip being adhesively bonded to the base plate with an adhesive and electrically insulating spacers;
c) mindestens ein auf der Grundplatte angeordnetes Logikchip, wobei das mindestens eine Logikchip mit einer dielektrischen Schicht zur dielektrischen Isolation von zumindest Teilen des Logikchips von der Grundplatte beschicht ist, die dielektrische Schicht mit einer Metallisierungsschicht beschichtet ist und die Metallisierungsschicht mittels eines zweiten Lötmittels auf die Grundplatte gelötet ist;c) at least one logic chip arranged on the base plate, wherein the at least one logic chip is coated with a dielectric layer for dielectric isolation of at least parts of the logic chip from the base plate, the dielectric layer is coated with a metallization layer and the metallization layer is applied to the metallization layer by means of a second solder Base plate is soldered;
d) mindestens ein auf der Grundplatte angeordnetes Leistungshalbleiterchip, wobei das mindestens eine Leistungshalbleiterchip mittels eines elektrisch und thermisch leitfähigen Lötmittels auf die Grundplatte gelötet ist;d) at least one power semiconductor chip arranged on the base plate, wherein the at least one power semiconductor chip is soldered to the base plate by means of an electrically and thermally conductive solder;
e) Signalubertragungsleitungen zur elektrischen Verbindung des Logikchips mit dem Leistungshalbleiterchip und zur Ver¬ bindung des Logikchips und des Leistungshalbleiterchips mit ersten und zweiten Anschlusseinheiten; unde) Signalubertragungsleitungen for electrical connection of the logic chip with the power semiconductor chip and Ver ¬ connection of the logic chip and the power semiconductor chips having first and second ports; and
f) einer Moldmasse bzw. einem Kunststoffverguss zur Verpak- kung der aus der Grundplatte, dem mindestens einem Leistungshalbleiterchip und dem mindestens einen Logikchip bestehenden elektronischen Baugruppe, um dieselbe vor schädlichen Umwelteinflüssen zu schützen.f) a molding compound or a plastic encapsulation for packaging of the base plate, the at least one power semiconductor chip and the at least one logic chip existing electronic assembly to protect it from harmful environmental influences.
ZEICHNUNGENDRAWINGS
Ausfuhrungsbeispiele der Erfindung sind den Zeichnungen dargestellt und der nachfolgenden Beschreibung naher erläutert .Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the following description.
In den Zeichnungen zeigen:In the drawings show:
Figur 1 eine Mehrfachchipverpackung ohne Moldmasse bzw. ohne Kunststoffverguss mit einem Logikchip und einem Leistungshalbleiterchip, welche durch Signal- ubertragungsleitungen verbunden sind und auf einerFigure 1 shows a multi-chip package without molding compound or without Kunststoffverguss with a logic chip and a power semiconductor chip, which are connected by signal transmission lines and on a
Grundplatte angeordnet sind, als Seiten- Schnittansicht entlang einer Linie A-A' der Figur 3 gemäß einem bevorzugten Ausfuhrungsbeispiel der vorliegenden Erfindung;Base plate arranged as a side sectional view taken along a line A-A 'of Figure 3 according to a preferred embodiment of the present invention;
Figur 2 eine Mehrfachchipverpackung einer Seiten-FIG. 2 shows a multiple chip package of a side
Schnittansicht entlang einer Linie A-A' der Figur 3 gemäß einem weiteren bevorzugten Ausfuhrungsbeispiel der vorliegenden Erfindung;Sectional view along a line A-A 'of Figure 3 according to another preferred embodiment of the present invention;
Figur 3 eine Draufsicht einer Mehrfachchipverpackung gemäß einem bevorzugten Ausfuhrungsbeispiel der vorliegenden Erfindung;Figure 3 is a plan view of a multiple chip package according to a preferred embodiment of the present invention;
Figur 4a eine Draufsicht einer Mehrfachchipverpackung mit einer aufgebrachten Moidmasse bzw. einem aufge- bracnten Kunststoffverguss gemäß einem bevorzugten Ausfuhrungsbeispiel der vorliegenden Erfindung; undFIG. 4 a shows a plan view of a multiple-chip package with an applied Moidmasse or a bracenen Kunststoffverguss according to a preferred embodiment of the present invention; and
Figur 4b eine Seitenansicht einer Mehrfachchipverpackung mit aufgebrachter Moldmasse bzw. aufgebrachtem Kunst- stoffverguss der Figur 4a gemäß einem bevorzugten Ausfuhrungsbeispiel der vorliegenden Erfindung.FIG. 4b shows a side view of a multi-chip package with applied molding compound or applied plastic Substance casting of Figure 4a according to a preferred embodiment of the present invention.
BESCHREIBUNG DER AUSFÜHRUNGSBEISPIELEDESCRIPTION OF THE EMBODIMENTS
In den Figuren bezeichnen gleiche Bezugszeichen gleiche oder funktionsgleiche Komponenten.In the figures, the same reference numerals designate the same or functionally identical components.
In der in Figur 1 gezeigten Seiten-Schnittansicht einer Mehr- fachchipverpackung ist die Moldmasse bzw. der Kunststoffverguss 120 (untenstehend unter Bezugnahme auf die Figuren 4a und 4b erläutert) aus Gründen der Übersichtlichkeit weggelassen. Die dargestellte Mehrfachchipverpackung besteht aus zwei Schaltungsmodulen, d.h. einem Logikchip 102 und einem Lei- stungshalbleiterchip 103, welche erfindungsgemäß auf einer gemeinsamen Grundplatte 101 angeordnet sind. Zur Abführung der in dem Leistungshalbleiterchip 103 erzeugten Wärme sowie zur Durchleitung von hohen Strömen bei einem geringen Übergangswiderstand (Spannungsabfall) muss das Leistungshalblei- terchip 103 mit möglichst hoher thermischer und möglichst hoher elektrischer Leitfähigkeit mit der Grundplatte 101, welche im allgemeinen als eine metallische Grundplatte ausgebildet ist, verbunden werden. Wie in Figur 1 dargestellt, wird das Leistungshalbleiterchip 103 mittels eines ersten Lötmittels 105 (schraffiert in Figur 1) auf die Grundplatte 101 gelötet.In the side sectional view of a multi-chip package shown in FIG. 1, the molding compound or plastic encapsulation 120 (explained below with reference to FIGS. 4 a and 4 b) has been omitted for reasons of clarity. The illustrated multiple chip package consists of two circuit modules, i. a logic chip 102 and a power semiconductor chip 103, which according to the invention are arranged on a common base plate 101. To dissipate the heat generated in the power semiconductor chip 103 and to pass high currents at a low contact resistance (voltage drop), the power semiconductor chip 103 must have the highest possible thermal and highest possible electrical conductivity with the base plate 101, which is generally formed as a metallic base plate is to be connected. As shown in FIG. 1, the power semiconductor chip 103 is soldered onto the base plate 101 by means of a first solder 105 (hatched in FIG. 1).
Die Grundplatte weist eine nach einem Verguss der Gesamtanordnung mit einer Moldmasse freigelassene Grundplattenan- Schlusseinheit 112 auf, die einen von mehreren möglichen elektrischen Anschlüssen zu dem Leistungshalbleiterchip 103 bereitstellt.The base plate has a base plate connection unit 112 which is left free after encapsulation of the overall arrangement with a molding compound and which provides one of several possible electrical connections to the power semiconductor chip 103.
Weiterhin ist in Figur 1 ein Logikchip 102 gezeigt, welches, wie oben erwähnt, von dem durch die Grundplatte 101 getragenen elektrischen Potential des Leistungshalbleiterchips 103 entkoppelt werden muss. In dem in Figur 1 gezeigten Ausfüh- rungsbeispiel der vorliegenden Erfindung wird dies erreicht, indem das Logikchip 102 mittels eines Klebemittels 106, welches elektrisch isolierend ist, auf die Grundplatte 101 geklebt wird. Zur präzisen Auslegung eines gleichförmigen Ab- Standes zwischen dem Logikchip 102 und der Grundplatte 101 und zur Sicherstellung einer ausreichenden Isolation sind in die Klebeschicht Abstandshalter 107 eingebracht, welche selbst elektrisch isolierend sind.Furthermore, FIG. 1 shows a logic chip 102 which, as mentioned above, must be decoupled from the electrical potential of the power semiconductor chip 103 carried by the baseplate 101. In the embodiment shown in FIG. In the exemplary embodiment of the present invention, this is achieved by gluing the logic chip 102 onto the base plate 101 by means of an adhesive 106, which is electrically insulating. For precise design of a uniform distance between the logic chip 102 and the base plate 101 and to ensure sufficient insulation spacers 107 are introduced into the adhesive layer, which are themselves electrically insulating.
Eine von mehreren Signalubertragungsleitungen ist als eine Signalübertragungsleitung 104a zur elektrischen Verbindung des Leistungshalbleiterchips 103 mit dem Logikchip 102 dargestellt. Weitere Signalübertragungsleitungen dienen einer Verbindung jeweils des Logikchips 102 bzw. des Leistungshalb- leiterchips 103 mit ersten und zweiten Anschlussemheiten 111 bzw. 113 (in Figur 3 gezeigt) . Auf diese Weise wird eine Mehrfachchipverpackung 100 beispielhaft mit zwei Schaltungsmodulen, dem Logikchip 102 und dem Leistungshalbleiterchip 103 in einer vorteilhaften kompakten Bauweise bzw. Gehäuse- form erreicht.One of a plurality of signal transmission lines is shown as a signal transmission line 104a for electrically connecting the power semiconductor chip 103 to the logic chip 102. Further signal transmission lines serve to connect respectively the logic chip 102 and the power semiconductor chip 103 with first and second connection units 111 and 113 (shown in FIG. 3). In this way, a multi-chip package 100 is achieved by way of example with two circuit modules, the logic chip 102 and the power semiconductor chip 103 in an advantageous compact design or housing form.
Figur 2 veranschaulicht eine weitere bevorzugte Ausführungsform der vorliegenden Erfindung, wobei in Figur 2 beispielhaft wiederum zwei Schaltungsmodule, d.h. ein Logikchip 102 und ein Leistungshalbleiterchip 103 gezeigt sind, welche durch eine Signalübertragungsleitung 104a elektrisch miteinander verbunden sind. Die Aufbringung des Leistungshalbleiterchips 103 auf der Grundplatte 101 ist wie unter Bezugnahme auf Figur 1 dargestellt realisiert, während das Logikchip 102 auf andere Weise elektrisch isolierend auf der einheitlichen, metallischen Grundplatte 101 aufgebracht ist. Auf das Logikchip 102 ist an dessen Unterseite eine dielektrische Schicht 109 aufgebracht, welche elektrisch isolierend ist. Auf diese dielektrische Schicht 109 ist eine Metallisierungsschicht 201 aufgebracht, welche als ein lötbares Verbindungselement zu der metallischen Grundplatte 101 dient. Somit ist es möglich, das Logikchip 102 elektrisch isolierend mittels eines zweiten Lotmittels 108 auf die Grundplatte 101 zu loten, wobei eine Lotverbindung nur zwischen der Metalli- sierungsschicht 201 und der metallischen Grundplatte 101 bereitgestellt wird. Eine gleichförmige, flach verlaufende dielektriscne Schicht 109 kann beispielsweise durch einen thermischen Oxidationsprozeß oder einen Abscheideprozeß bei der Chipnersteilung bereitgestellt werden. Eine weitere Möglichkeit besteht darin, für die Herstellung des Logikchips ein SOI-Substrat (Silicon on Insulator) zu verwenden. In diesem Fall befindet sich oberhalb und unterhalb der dielektrischen Schicht 109 ein Halbleitermaterial, und die Metall- schicht 201 wird auf der Unterseite des unterhalb der dielektrischen Schicht 109 angeordneten Halbleitermaterials aufge- bracht.FIG. 2 illustrates a further preferred embodiment of the present invention, FIG. 2 again showing, by way of example, two circuit modules, ie a logic chip 102 and a power semiconductor chip 103, which are electrically connected to one another by a signal transmission line 104a. The application of the power semiconductor chip 103 on the base plate 101 is realized as shown with reference to Figure 1, while the logic chip 102 is applied in other ways electrically insulating on the uniform, metallic base plate 101. On the logic chip 102, a dielectric layer 109 is applied to its underside, which is electrically insulating. Onto this dielectric layer 109, a metallization layer 201 is applied, which serves as a solderable connection element to the metallic base plate 101. Thus, it is possible to electrically isolate the logic chip 102 by means of a second solder 108 on the base plate 101, wherein a solder connection is provided only between the metallization layer 201 and the metallic base plate 101. A uniform, flat dielectric layer 109 may be provided, for example, by a thermal oxidation process or a deposition process in chip-sharing. Another possibility is to use an SOI substrate (silicon on insulator) for the production of the logic chip. In this case, a semiconductor material is located above and below the dielectric layer 109, and the metal layer 201 is deposited on the underside of the semiconductor material disposed below the dielectric layer 109.
Figur 3 zeigt eine Mehrfachchipverpackung 100, in welcher ein Logikchip 102 und ein Leistungshalbleiterchip 103 eingeschlossen ist, m einer Draufsicht, wobei eine Moldmasse 120 aus Gründen der Ubersichtlicnkeit weggelassen ist. Wie mFIG. 3 shows a multiple-chip package 100, in which a logic chip 102 and a power semiconductor chip 103 are enclosed, in a plan view, wherein a molding compound 120 has been omitted for reasons of clarity. How m
Figur 3 gezeigt, dienen Signalubertragungsleitungen 104a und 104b einer elektrischen Verbindung des Logikchips 102 mit dem Leistungshalbleiterchip 103, wahrend Signalubertragungsleitungen 104c und 104e einer elektrischen Verbindung des Logik- chips mit ersten und zweiten Anschlussemheiten 111 bzw. 113 dienen. Eine Signalubertragungsleitung 104d dient einer Verbindung des Leistungshalbleiterchips 103 mit der zweiten Anschlussemheit 113.3, serve signal transmission lines 104a and 104b of an electrical connection of the logic chip 102 to the power semiconductor chip 103, while signal transmission lines 104c and 104e serve an electrical connection of the logic chip with first and second connection units 111 and 113, respectively. A signal transmission line 104d serves to connect the power semiconductor chip 103 to the second connection unit 113.
Eine weitere Verbindung des Leistungshalbleiterchips 103 wird über die Grundplatte zu der Grundplattenanschlussemheit 112 dadurch realisiert, dass das Leistungshalbleiterchip 103 mittels eines elektrisch leitfahigen Klebers 105 auf die Grundplatte 101 gelotet ist, wie obenstehend unter Bezugnahme auf Figur 1 beschrieben. Es sei darauf hingewiesen, dass die Signalubertragungsleitungen 104a-104e nur beispielhaft s nd, d.h. es können weniger oder mehr als fünf Signalubertragungsleitungen 104a-104e vorhanden sein.Another connection of the power semiconductor chip 103 is realized via the base plate to the base plate terminal 112 by soldering the power semiconductor chip 103 onto the base plate 101 by means of an electrically conductive adhesive 105, as described above with reference to FIG. It should be noted that the signal transmission lines 104a-104e only by way of example s nd, that is, fewer or more than five signal transmission lines 104a-104e may be present.
Das Leistungshalbleitercmp 103 kann beispielsweise als ein IGBT („msulated gate bipolar transistor" = Bipolartransistor mit isoliertem Gate) für Zundanwendungen ausgebildet sein, wobei das Logikchip 102 die zugehörige Logikschaltung, eine ESD- (electrostatic discharge, elektrostatische Entladung) Schutzschaltung und eine Stromregelschaltung aufweist. In diesem Beispiel stellt die Grundplattenanschlussemheit 112 eine mit einem Kollektor des IGBT verbundene Anschluss fahne bereit, an welche eine Zündspule angeschlossen werden kann, wobei die zweite Anschlusse heit 113 auf einem Bezugspoten- tial liegt und die erste Anschlussemheit 111 als e n Steuer- anschluss dient.The power semiconductor cluster 103 may be configured, for example, as an IGBT (Insulated Gate Bipolar Transistor) for ignition applications, wherein the logic chip 102 includes the associated logic circuitry, an ESD (Electrostatic Discharge) protection circuit, and a current control circuit. In this example, the base plate terminal 112 provides a terminal tag connected to a collector of the IGBT to which an ignition coil can be connected, the second terminal 113 being on a reference potential, and the first terminal unit 111 serving as a control terminal.
Das an der ersten Anschlusseinheit 111 anliegende Steuersignal wird über die Signalubertragungsleitung 104c, das Logikchip 102 und die Signalubertragungsleitung 104a an das Gate des IGBTs (des Leistungshalbleiterchips 103) weitergeleitet. Über die Signalubertragungsleitung 104b wird von dem IGBT 103 ein zum Spulenstrom der Zündspule proportionales Signal an die auf dem Logikchip 102 realisierte Stromregelschaltung zuruckgemeldet . Diese kann durch eine Verringerung der über die Signalubertragungsleitung 104a an den IGBT gelieferten Gate-Spannung ein Überschreiten eines Grenzwertes des durch die Zündspule fließenden Spuienstro s verhindern.The control signal applied to the first terminal unit 111 is forwarded via the signal transmission line 104c, the logic chip 102 and the signal transmission line 104a to the gate of the IGBT (the power semiconductor chip 103). Via the signal transmission line 104b, a signal proportional to the coil current of the ignition coil is returned by the IGBT 103 to the current control circuit implemented on the logic chip 102. This can prevent exceeding of a limit value of the Spuienstro flowing through the ignition coil by reducing the gate voltage supplied to the IGBT via the signal transmission line 104a.
Die Figuren 4a und 4b zeigen eine Mehrfachchipverpackung 100 mit einer aufgebrachten Moldmasse 120 bzw. einem aufgebrachten Kunststoffverguss, so dass eine vollständige Verpackung der unter Bezugnahme auf die Figuren 1 bis 3 gezeigten Schaltungsmodule, d.h. des Logikchips 102 und des Leistungshalbleiterchips 103 bereitgestellt wird. Hierbei ist in Figur 4b e ne Seitenansicht der Figur 4a dargestellt. Es sei darauf hingewiesen, dass die Moldmasse 120 zur Verpak- kung der aus dem mindestens einen Leistungshalbleiterchip 103 und dem mindestens einen Logikchip 102 bestehenden elektronischen Baugruppe mindestens eine Grundplattenanschlussemheit 112 der Grundplatte 101 und die von den Modulen 102 bzw. 103 wegweisenden Enden von ersten und zweiten Anschlusseinheiten 111 bzw. 113 freilässt. In vorteilhafter Weise weist die Grundplatte 101 selbst eine hohe elektrische und eine hohe thermische Leitfähigkeit auf, wobei die Grundplatte vorzugs- weise aus einem metallischen Material wie beispielsweise einem Kupfermaterial oder einer Kupferlegierung ausgeführt ist. Externe Schaltungseinheiten werden vorzugsweise an der Grundplattenanschlussemheit 112 sowie an der ersten Anschlusseinheit 111 und der zweiten Anschlusseinheit 113 ange- schlössen.FIGS. 4a and 4b show a multi-chip package 100 with an applied molding compound 120 or an applied plastic encapsulation, so that complete packaging of the circuit modules shown with reference to FIGS. 1 to 3, ie the logic chip 102 and the power semiconductor chip 103 is provided. Here, in FIG. 4b, a side view of FIG. 4a is shown. It should be noted that the molding compound 120 for packaging the electronic assembly consisting of the at least one power semiconductor chip 103 and the at least one logic chip 102 has at least one base plate terminal unit 112 of the base plate 101 and the ends of the first and of the modules facing away from the modules 102 and 103, respectively second connection units 111 and 113 leaves free. Advantageously, the base plate 101 itself has a high electrical and a high thermal conductivity, wherein the base plate is preferably made of a metallic material such as a copper material or a copper alloy. External circuit units are preferably connected to the base plate connection unit 112 and to the first connection unit 111 and the second connection unit 113.
Durch das erfindungsgemäße Verfahren zum Verpacken von elektronischen Baugruppen, wobei Leistungshalbleiterchips und Logikchips kombinierbar sind, sowie durch die erfindungsgemä- ße Mehrfachchipverpackung wird eine Anordnung einzelnerThe method according to the invention for packaging electronic assemblies, in which power semiconductor chips and logic chips can be combined, as well as the multiple chip package according to the invention makes an arrangement of individual components
Schaltungsmodule auf einer einheitlichen Grundplatte vereinfacht, ein Gehäuse bzw. eine Verpackung wird kompakter auslegbar, wodurch bei einer Fertigung der Mehrfachchipverpak- kung ein erheblicher wirtschaftlicher Vorteil bereitgestellt wird.Simplifies circuit modules on a common base plate, a housing or packaging is more compact interpretable, whereby a significant economic advantage is provided in a production of Mehrfachchipverpak- kung.
Obwohl die vorliegende Erfindung vorstehend anhand bevorzugter Ausführungsbeispiele beschrieben wurde, ist sie darauf nicht beschränkt, sondern auf vielfältige Weise modifizier- bar. Verfahren zum Verpacken von elektronischen Baugruppen und MehrfachchipyerpackungAlthough the present invention has been described above with reference to preferred embodiments, it is not limited thereto, but modifiable in many ways. Method for packaging electronic assemblies and multiple chip packaging
Bezugszeichenlist*Reference numeral List *
100 Mehrfachchipverpackung100 multiple chip packaging
101 Grundplatte101 base plate
102 Logikchip102 logic chip
103 Leistungshalbleiterchip103 power semiconductor chip
104a- Signalubertragungsleitungen104a signal transmission lines
104e104e
105 Erstes Lotmittel105 First Lot
106 Klebemittel106 adhesives
107 Abstandshalter107 spacers
108 Zweites Lotmittel108 Second Lot
109 Dielektrische Schicht109 Dielectric layer
111 Erste Anschlussemheit111 First connection unit
112 Grundplattenanschlussemheit112 base plate connection unit
113 Zweite Anschlussemheit113 Second connection unit
120 Moldmasse120 molding material
201 Metalllsierungsschient 201 metal alloy splitter

Claims

Verfahren zum Verpacken von elektronischen Baugruppen und MehrfachchipyerpackungPatentansprüche Method for packaging electronic assemblies and multiple chip packaging Patent claims
1. Verfahren zum Verpacken von elektronischen Baugruppen, wobei Leistungshalbleiterchips (103) und Logikchips (102) kombinierbar sind, mit den Schritten:1. A method for packaging electronic assemblies, wherein power semiconductor chips (103) and logic chips (102) can be combined, with the steps:
a) Aufbringen mindestens eines Leistungshalbleiterchips (103) auf einer Grundplatte (101) mit einem ersten Lötmittel (105) ;a) applying at least one power semiconductor chip (103) on a base plate (101) with a first solder (105);
b) Aufbringen mindestens eines Logikchips (102) auf der Grundplatte (101), wobei das Logikchip (102) und die Grundplatte (101) elektrisch voneinander isoliert angeordnet wer- den;b) applying at least one logic chip (102) on the base plate (101), wherein the logic chip (102) and the base plate (101) are arranged electrically isolated from each other;
c) Verbinden des mindestens einen Logikchips (102) mit dem mindestens einen Leistungshalbleiterchip (103) sowie des Logikchips (102) und des Leistungshalbleiterchips (103) mit ersten und zweiten Anschlusseinheiten (111, 113) mittels Signalübertragungsleitungen (104a-104e) ; undc) connecting the at least one logic chip (102) to the at least one power semiconductor chip (103) and the logic chip (102) and the power semiconductor chip (103) with first and second terminal units (111, 113) by means of signal transmission lines (104a-104e); and
d) Verpacken der aus dem mindestens einen Leistungshalbleiterchip (103) und dem mindestens einen Logikchip (102) beste- henden elektronischen Baugruppe mittels einer Moldmasse (120) , um eine Mehrfachchipverpackung (100) zu erhalten.d) packaging of the at least one power semiconductor chip (103) and the at least one logic chip (102) existing electronic assembly by means of a molding compound (120) to obtain a multi-chip package (100).
2. Verfahren nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , dass eine elektrische Isolierung des Logikchips (102) von der Grundplatte (101) durch eine auf das Logikchip (102) aufgebrachte dielektrische Schicht (109) bereitgestellt wird. 2. The method according to claim 1, characterized in that an electrical insulation of the logic chip (102) from the base plate (101) by a on the logic chip (102) applied dielectric layer (109) is provided.
3. Verfahren nach einem oder beiden der Ansprüche 1 und 2, d a d u r c h g e k e n n z e i c h n e t , dass eine elektrische Isolierung des Logikchips (102) von der Grundplatte (101) durch eine Klebung des Logikchips (102) auf die Grundplatte (101) mittels eines elektrisch isolierenden Klebemittels (106) bereitgestellt wird.3. The method according to one or both of claims 1 and 2, characterized in that an electrical insulation of the logic chip (102) from the base plate (101) by an adhesion of the logic chip (102) on the base plate (101) by means of an electrically insulating adhesive ( 106).
4. Verfahren nach einem oder mehreren der voranstehenden4. Method according to one or more of the preceding
Ansprüche, d a d u r c h g e k e n n z e i c h n e t , dass zur elektrischen Isolierung des Logikchips (102) von derClaims to claim that for electrical isolation of the logic chip (102) from the
Grundplatte (101) in eine aus dem Klebemittel (106) bestehen- de Klebeschicht elektrisch isolierende Abstandshalter (107) eingebracht werden.Base plate (101) in an adhesive layer consisting of the adhesive (106) adhesive layer electrically insulating spacers (107) are introduced.
5. Verfahren nach einem oder mehreren der voranstehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , dass das Logikchip (102) mittels einer auf die dielektrische Schicht (109) des Logikchips (102) aufgebrachten Metallisie- rungsschicht (201) und mittels eines zweiten Lötmittels (108) auf die Grundplatte (101) gelötet wird.5. The method according to one or more of the preceding claims, characterized in that the logic chip (102) by means of a dielectric layer (109) of the logic chip (102) applied metallization layer (201) and by means of a second solder (108) on the Base plate (101) is soldered.
6. Verfahren nach einem oder mehreren der voranstehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , dass durch das erste Lötmittel (105) eine hohe thermische Leitfähigkeit zwischen dem Leistungshalbleiterchip (103) und der Grundplatte (101) bereitgestellt wird.6. The method according to one or more of the preceding claims, characterized in that by the first solder (105), a high thermal conductivity between the power semiconductor chip (103) and the base plate (101) is provided.
7. Verfahren nach einem oder mehreren der voranstehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , dass durch das erste Lötmittel (105) eine hohe elektrische Leitfähigkeit zwischen dem Leistungshalbleiterchip (103) und der Grundplatte (101) bereitgestellt wird.7. The method according to one or more of the preceding claims, characterized a high electrical conductivity is provided between the power semiconductor chip (103) and the base plate (101) by the first solder (105).
8. Verfahren nach einem oder mehreren der voranstehenden Ansprüche, d a d u r c h g e k e n n z e i c h n e t , dass eine elektrische Isolierung des Logikchips (102) von der Grundplatte (101) durch ein SOI- (silicon on insulator) - Substrat bereitgestellt wird.8. The method according to one or more of the preceding claims, characterized in that an electrical insulation of the logic chip (102) of the base plate (101) by an SOI (silicon on insulator) - substrate is provided.
9. Verfahren nach einem oder mehreren der voranstehenden Ansprüche , d a d u r c h g e k e n n z e i c h n e t , dass ein Leistungshalbleiterchip (103)- mit mindestens zwei unterschiedlichen Logikchips (102) kombiniert wird, um eine Mehrfachchipverpackung (100) bereitzustellen.9. The method of claim 1, wherein a power semiconductor chip is combined with at least two different logic chips to provide a multi-chip package.
10. Mehrfachchipverpackung (100), mit:10. Multiple chip packaging (100), with:
a) einer Grundplatte (101) ;a) a base plate (101);
b) mindestens einem auf der Grundplatte (101) angeordneten Logikchip (102), wobei das mindestens eine Logikchip (102) mit einem elektrisch isolierenden Klebemittel (106) und mit elektrisch isolierenden Abstandshaltern (107) elektrisch isolierend auf die Grundplatte (101) geklebt ist;b) at least one on the base plate (101) arranged logic chip (102), wherein the at least one logic chip (102) with an electrically insulating adhesive (106) and with electrically insulating spacers (107) is electrically insulating glued to the base plate (101) ;
c) mindestens einem auf der Grundplatte (101) angeordneten Leistungshalbleiterchip (103) , wobei das mindestens einec) at least one on the base plate (101) arranged power semiconductor chip (103), wherein the at least one
Leistungshalbleiterchip (103) mittels eines elektrisch und thermisch leitfähigen Lötmittels (105) auf die Grundplatte (101) gelötet ist;Power semiconductor chip (103) is soldered by means of an electrically and thermally conductive solder (105) on the base plate (101);
d) Signalübertragungsleitungen (104a-104e) zur elektrischen Verbindung des Logikchips (102) mit dem Leistungshalbleiterchip (103) und des Logikchips (102) und des Leistungshalblei- terchips (103) mit ersten und zweiten Anschlusseinheiten (111, 113) ; undd) signal transmission lines (104a-104e) for the electrical connection of the logic chip (102) to the power semiconductor chip (103) and the logic chip (102) and the power semiconductor terchips (103) having first and second terminal units (111, 113); and
e) einer Moldmasse (120) zur Verpackung der aus der Grund- platte (101) , dem mindestens einen Leistungshalbleiterchip (103) und dem mindestens einen Logikchip (102) bestehenden elektronischen Baugruppe.e) a molding compound (120) for packaging the electronic assembly consisting of the base plate (101), the at least one power semiconductor chip (103) and the at least one logic chip (102).
11. Mehrfachchipverpackung (100), mit11. Multiple chip package (100), with
a) einer Grundplatte (101) ;a) a base plate (101);
b) mindestens einem auf der Grundplatte (101) angeordneten Logikchip (102), wobei das mindestens eine Logikchip (102) mit einer dielektrischen Schicht (109) zur elektrischen Isolation von zumindest Teilen des Logikchips (102) von der Grundplatte (101) beschichtet ist, die dielektrische Schicht (109) mit einer Metallisierungsschicht (201) beschichtet ist und die Metallisierungsschicht (201) mittels eines zweiten Lötmittels (108) auf die Grundplatte (101) gelötet ist .b) at least one logic chip (102) arranged on the base plate (101), wherein the at least one logic chip (102) is coated with a dielectric layer (109) for electrically insulating at least parts of the logic chip (102) from the base plate (101) in that the dielectric layer (109) is coated with a metallization layer (201) and the metallization layer (201) is soldered to the base plate (101) by means of a second solder (108).
c) mindestens einem auf der Grundplatte (101) angeordneten Leistungshalbleiterchip (103), wobei das mindestens eine Leistungshalbleiterchip (103) mittels eines elektrisch und thermisch leitfähigen Lötmittels (105) auf die Grundplatte (101) gelötet ist;c) at least one power semiconductor chip (103) arranged on the base plate (101), wherein the at least one power semiconductor chip (103) is soldered to the base plate (101) by means of an electrically and thermally conductive solder (105);
d) Signalübertragungsleitungen (104a-104e) zur elektrischen Verbindung des Logikchips (102) mit dem Leistungshalbleiter- chip (103) und des Logikchips (102) und des Leistungshalble! • terchips (103) mit ersten und zweiten Anschlussemheiten (111, 113) ; undd) signal transmission lines (104a-104e) for electrically connecting the logic chip (102) to the power semiconductor chip (103) and the logic chip (102) and the Leistungshalble! • terchips (103) having first and second Anschlussemheiten (111, 113); and
e) einer Moldmasse (120) zur Verpackung der aus der Grund- platte (101) , dem mindestens einen Leistungshalbleiterchipe) a molding compound (120) for packaging the base plate (101), the at least one power semiconductor chip
(103) und dem mindestens einen Logikchip (102) bestehenden elektronischen Baugruppe. (103) and the at least one logic chip (102) existing electronic assembly.
12. Mehrfachchipverpackung (100), mit:12. Multiple chip packaging (100), with:
a) einer Grundplatte (101) ;a) a base plate (101);
b) mindestens einem auf der Grundplatte (101) angeordneten Logikchip (102), wobei das mindestens eine Logikchip (102) mit einem elektrisch isolierenden Klebemittel (106) und mit elektrisch isolierenden Abstandshaltern (107) elektrisch isolierend auf die Grundplatte (101) geklebt ist;b) at least one on the base plate (101) arranged logic chip (102), wherein the at least one logic chip (102) with an electrically insulating adhesive (106) and with electrically insulating spacers (107) is electrically insulating glued to the base plate (101) ;
c) mindestens einem auf der Grundplatte (101) angeordneten Logikchip (102), wobei das mindestens eine Logikchip (102) mit einer dielektrischen Schicht (109) zur elektrischen Iso- lation von zumindest Teilen des Logikchips (102) von derc) at least one logic chip (102) arranged on the base plate (101), wherein the at least one logic chip (102) is provided with a dielectric layer (109) for the electrical isolation of at least parts of the logic chip (102) from the
Grundplatte (101) beschichtet ist, die dielektrische Schicht (109) mit einer Metallisierungsschicht (201) beschichtet ist und die Metallisierungsschicht (201) mittels eines zweiten Lötmittels (108) auf die Grundplatte (101) gelötet ist;Base plate (101) is coated, the dielectric layer (109) is coated with a metallization layer (201) and the metallization layer (201) is soldered to the base plate (101) by means of a second solder (108);
d) mindestens einem auf der Grundplatte (101) angeordneten Leistungshalbleiterchip (103) , wobei das mindestens eine Leistungshalbleiterchip (103) mittels eines elektrisch und thermisch leitfähigen Lötmittels (105) auf die Grundplatte (101) gelötet ist;d) at least one power semiconductor chip (103) arranged on the base plate (101), wherein the at least one power semiconductor chip (103) is soldered to the base plate (101) by means of an electrically and thermally conductive solder (105);
e) ' Signalübertragungsleitungen (104a-104e) zur elektrischen Verbindung des Logikchips (102) mit dem Leistungshalbleiterchip (103) und des Logikchips (102) und des Leistungshalblei • terchips (103) mit ersten und zweiten Anschlusseinheiten (111, 113) ; unde) 'signal transmission lines (104a-104e) for electrical connection of the logic chip (102) with the power semiconductor chip (103) and the logic chip (102) and the Leistungshalblei • terchips (103) having first and second terminal units (111, 113); and
f) einer Moldmasse (120) zur Verpackung der aus der Grundplatte (101) , dem mindestens einen Leistungshalbleiterchip (103) und dem mindestens einen Logikchip (102) bestehenden elektronischen Baugruppe. f) a molding compound (120) for packaging the electronic assembly consisting of the base plate (101), the at least one power semiconductor chip (103) and the at least one logic chip (102).
13. Mehrf chchipverpackung (100) nach einem oder mehreren der Ansprüche 10 bis 12, d a d u r c h g e k e n n z e i c h n e t , dass in das zur Klebung des mindestens einen Logikchips (102) auf die Grundplatte (101) eingesetzte Klebemittel (10S) elektrisch isolierende Abstandshalter (107) eingebracht sind.13. Mehrf chchipverpackung (100) according to one or more of claims 10 to 12, characterized in that in the bonding of the at least one logic chip (102) on the base plate (101) used adhesive (10S) electrically insulating spacers (107) are introduced ,
14. Mehrfachchipverpackung (100) nach einem oder mehreren der Ansprüche 10 bis 13, d a d u r c h g e k e n n z e i c h n e t , dass die Moldmasse (120) zur Verpackung der aus dem mindestens einen Leistungshalbleiterchip (103) und dem mindestens einen Logikchip (102) bestehenden elektronischen Baugruppe mindestens eine Grundplattenanschlussemheit (112) der Grund- platte (101) und die von den Modulen (102, 103) wegweisenden Enden von ersten und zweiten Anschlusseinheiten (111, 113) freilässt .14. Multi-chip package (100) according to one or more of claims 10 to 13, characterized in that the molding compound (120) for packaging the at least one power semiconductor chip (103) and the at least one logic chip (102) existing electronic assembly at least one Grundplattenanschlussemheit ( 112) of the base plate (101) and the ends of first and second terminal units (111, 113) facing away from the modules (102, 103).
15. Mehrfachchipverpackung (100) nach einem oder mehreren der Ansprüche 10 bis 14, d a d u r c h g e k e n n z e i c h n e t , dass die Grundplatte (101) hohe elektrische und hohe thermische Leitf higkeiten aufweist.15. The multi-chip package (100) according to one or more of claims 10 to 14, wherein a base plate (101) has high electrical and high thermal conductivities.
16. Mehrfachchipverpackung (100) nach einem oder mehreren der16. Multiple chip package (100) after one or more of
Ansprüche 10 bis 15, d a d u r c h g e k e n n z e i c h n e t , dass die Grundplatte (101) aus einem metallischen Material ausgeführt ist.Claims 10 to 15, d a d u r c h e c e n e c e in that the base plate (101) is made of a metallic material.
17. Mehrfachchipverpackung (100) nach einem oder mehreren der17. Multiple chip package (100) after one or more of
Ansprüche 10 bis 16, d a d u r c h g e k e n n z e i c h n e t , dass die Grundplatte (101) aus einem Kupfermaterial oder einer Kupferlegierung gebildet ist. Claims 10 to 16, characterized in that the base plate (101) is formed of a copper material or a copper alloy.
18. Mehrfachchipverpackung (100) nach einem oder mehreren der Ansprüche 10 bis 17, d a d u r c h g e k e n n z e i c h n e t , dass die Grundplatte (101) eine Grundplattenanschlussemheit (112) zum Anschluss von externen Schaltungseinheiten aufweist .18. The multi-chip package (100) according to claim 10, wherein the base plate (101) has a base plate connection unit (112) for connecting external circuit units.
19. Mehrfachchipverpackung (100) nach einem oder mehreren der Ansprüche 10 bis 18, d a d u r c h g e k e n n z e i c h n e t , dass das Leistungshalbleiterchip (103) als ein IGBT ausgebildet ist . 19. The multi-chip package (100) according to one or more of claims 10 to 18, wherein a power semiconductor chip (103) is formed as an IGBT.
EP02776729A 2001-10-09 2002-09-26 Method for packing electronic modules and multiple chip packaging Withdrawn EP1438740A2 (en)

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DE10149774 2001-10-09
DE10149774A DE10149774A1 (en) 2001-10-09 2001-10-09 Process for packing electronic modules comprises applying a power semiconductor chip on a base plate, applying a logic chip on the base plate, connecting the logic chip with the semiconductor chip, and packing the module
PCT/DE2002/003638 WO2003034495A2 (en) 2001-10-09 2002-09-26 Method for packing electronic modules and multiple chip packaging

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DE10149774A1 (en) 2003-04-24
WO2003034495A3 (en) 2004-03-18
US20050006758A1 (en) 2005-01-13
JP2005506702A (en) 2005-03-03
WO2003034495A2 (en) 2003-04-24
US7042085B2 (en) 2006-05-09

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