EP1454448A2 - Method for correcting initial sampling of the serial bit rate of a filter's output signal - Google Patents
Method for correcting initial sampling of the serial bit rate of a filter's output signalInfo
- Publication number
- EP1454448A2 EP1454448A2 EP02804844A EP02804844A EP1454448A2 EP 1454448 A2 EP1454448 A2 EP 1454448A2 EP 02804844 A EP02804844 A EP 02804844A EP 02804844 A EP02804844 A EP 02804844A EP 1454448 A2 EP1454448 A2 EP 1454448A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- sampling
- signal
- time
- filter
- edge signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000007704 transition Effects 0.000 claims abstract description 9
- 238000001914 filtration Methods 0.000 claims abstract description 7
- 238000001514 detection method Methods 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 108010076504 Protein Sorting Signals Proteins 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Definitions
- the invention relates to a method for correcting the start of the scanning of the start bit of a serial bit sequence of an output signal of a filter, in particular a read / write device, with the features of the preamble of patent claim 1.
- the prior art includes methods for bidirectional electromagnetic communication, in particular between read / write devices and mobile data carriers, e.g. known in the areas of manufacturing, warehousing, transport, traffic and / or personal control.
- Read / write devices and mobile data carriers are e.g. used in technical facilities where a large number of objects or goods must at least be moved as quickly and freely as possible.
- the objects can be of various types, e.g. Parcels in a shipping facility, assembly parts in a production facility, luggage in a transport system and much more. It is usually necessary to do this at certain points in the facility, e.g. a production system, such as the type and condition of the objects currently in spatial proximity to these locations, quickly and unhindered.
- the objects are provided with mobile data memories, which e.g. contain data identifying the type and the current state of the object.
- read / write devices are placed at certain points in the device and are often connected to central data processing devices.
- the invention has for its object to provide a method for scanning a serial bit sequence, in which faults in the serial bit sequence are detected and corrected during the scan.
- the RF data signal of a mobile data carrier received in the read / write device passes through a filter element of the read / write device for demodulation.
- the output signal of the filter element is used to scan and recognize the transmitted serial bit sequence via a scanning element known per se.
- the filtering of the received signal in the filter element of the read / write device begins when a first edge signal is detected, for example, according to the agreement, a logical 1-0 transition.
- the filtered signal passes through the filter element in the absence of interference in the filter time F.
- the sampling of the output signal of the filter element begins with a sampling time AI and the start bit and the further data bits of the serial bit sequence each with distant sampling times A2 are sampled until the end of the serial bit sequence, that is to say the transmitted byte, has been reached.
- a fault in the signal sequence to be filtered and scanned is detected if a second edge signal of the received signal is determined before the filter time F has elapsed. When such a disturbance occurs, the time period t of the disturbance is recorded.
- a correction according to the invention of the start of the scanning of the serial bit sequence takes place by reducing the scanning time AI following the filter time F by the time period 2t ⁇ . After this reduced sampling time AI has elapsed, the sampling of the start bit and the further data bits begins with equidistant and unchanged sampling times A2 until the serial bit sequence has been completely scanned and completed.
- the first and second edge signals are, in particular, opposite signals. If the rest position is defined as a logical “1”, the first edge signal can be implemented as a logical 1-O transition and the second edge signal as a logical 0-1 transition.
- the total time period T of the individual faults with the individual time periods t should not exceed half of the first sampling time AI, since otherwise no correction according to the invention of the start of the sampling can take place.
- the method according to the invention enables the detection and correction of faults which occur during the reception of the start bit of a serial bit sequence. These disturbances are corrected by a corresponding reduction in a preset sampling time AI, so that the beginning of the sampling with the equidistant sampling times A2 takes place with correct assignment to the start bit of the serial transmitted bit sequence.
- the sampling begins with the undiminished and preset sampling time AI after a complete filter time F without detection of a disturbance. This results in an overall delay of the filtered and sampled signal, which is composed of the sum of filter time F and sampling time AI.
- a counter can be used to record the time t of each individual fault, which at the start of filtering, e.g. upon detection of a first described edge signal starting from an initial value (e.g. the number 1) starts to run in a (e.g. increasing) direction and after the filter time F has passed without any disturbances occurring, it reaches an end value N (e.g. the number 100). If disturbances now occur and these are detected by detection of a second edge signal described, the counter changes its direction and counts in the opposite direction until a first edge signal is detected again.
- an initial value e.g. the number 1
- N e.g. the number 100
- the start of the sampling time AI is only triggered when the counter reaches the end value from the start value.
- the method is shown in more detail with the aid of the drawing figure using an exemplary embodiment.
- Signal 1 shows a serial bit sequence received by the read / write device, in which, in accordance with an agreed data protocol for the transmission of HF data signals between the read / write device and the mobile data carrier, the rest position as a logical “1 * (short: log 1) is agreed.
- the transmitted serial bit sequence then begins with a start bit (log 0) by a first edge signal, namely a logical 1-0 transition between the idle position and the start bit.
- the start bit is followed by the first and further data bits of the entire transmitted serial bit sequence, only the first three data bits (log 1, log 0 and log 1) of the serial bit sequence being shown in the drawing.
- the entire serial bit sequence received is scanned starting with the start bit, the first and the further data bits.
- the received signal 1 was not disturbed during the transmission of the start bit, so that the preset sampling time AI was retained unabated after the filter time F.
- Signal 4 shows a received signal 1 of the read / write device which is disturbed during the start bit, in the case of which after the first Edge signal, i.e. the logical 1-0 transition between the idle position and the start bit, the fault ti occurs after a period of 4 ⁇ s with a duration of 4 ⁇ s and after a further undisturbed period of 8 ⁇ s the fault t 2 also occurs with 8 ⁇ s.
- the filter time F starts again and is not interrupted by disturbances.
- the undiminished sampling time AI of AI 34 ⁇ s follows after the end of the filter time F according to signal 7, at the end of which the sampling would begin with the sampling times A2. At the time A, this sampling would determine a logical “1 w state” in the sampled signal 5 as the beginning of the serial bit sequence, although according to the corrected signal 6 the start bit would have to be sampled with a logical “O'state. If the start of the sampling of the start bits were not corrected, the sampling would be delayed with the sampling time A2. The reference to the start of the start bit, which is essential for a correct scanning of the serial bit sequence, is therefore not achieved with signal 7. This would incorrectly scan the transmitted serial bit sequence.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Communication Control (AREA)
Abstract
Description
Beschreibungdescription
Verfahren zur Korrektur des Beginns der Abtastung einer seriellen Bitfolge eines Ausgangssignals eines FiltersMethod for correcting the start of sampling a serial bit sequence of an output signal of a filter
Die Erfindung betrifft ein Verfahren zur Korrektur des Beginns der Abtastung des Startbits einer seriellen Bitfolge eines Ausgangssignals eines Filters insbesondere eines Schreib-/Lesegeräts mit den Merkmalen des Oberbegriffs des Patentanspruchs 1.The invention relates to a method for correcting the start of the scanning of the start bit of a serial bit sequence of an output signal of a filter, in particular a read / write device, with the features of the preamble of patent claim 1.
Als Stand der Technik sind Verfahren zur bidirektionalen elektromagnetischen Kommunikation insbesondere zwischen Schreib-/Lesegeräten und mobilen Datenträgern z.B. in den Bereichen Fertigung, Lagerhaltung, Transport, Verkehr und/oder Personenkontrolle bekannt.The prior art includes methods for bidirectional electromagnetic communication, in particular between read / write devices and mobile data carriers, e.g. known in the areas of manufacturing, warehousing, transport, traffic and / or personal control.
Schreib-/Lesegeräte und mobile Datenträger werden z.B. in technischen Einrichtungen eingesetzt, wo eine Vielzahl von Objekten bzw. Gütern möglichst schnell und frei zumindest bewegt werden müssen. Die Objekte können dabei unterschiedlichster Art sein, z.B. Pakete in einer Versandeinrichtung, Montageteile in einer Fertigungsanlage, Gepäckstücke in einem Transportsystem und vieles mehr. Dabei ist es in aller Regel erforderlich, an bestimmten Stellen der Einrichtung, z.B. einer Fertigungsanlage, etwa die Art und den Zustand der in einer räumlichen Nähe zu diesen Stellen aktuell befindlichen Objekte schnell und ungehindert zu erfassen. Hierzu werden einerseits die Objekte mit mobilen Datenspeichern versehen, welche z.B. die Art und den aktuellen Zustand des Objektes kennzeichnende Daten enthalten. Andererseits sind an den bestimmten Stellen der Einrichtung Schreib-Lese-Geräte platziert und häufig mit zentralen Datenverarbeitungseinrichtungen verbunden.Read / write devices and mobile data carriers are e.g. used in technical facilities where a large number of objects or goods must at least be moved as quickly and freely as possible. The objects can be of various types, e.g. Parcels in a shipping facility, assembly parts in a production facility, luggage in a transport system and much more. It is usually necessary to do this at certain points in the facility, e.g. a production system, such as the type and condition of the objects currently in spatial proximity to these locations, quickly and unhindered. For this purpose, the objects are provided with mobile data memories, which e.g. contain data identifying the type and the current state of the object. On the other hand, read / write devices are placed at certain points in the device and are often connected to central data processing devices.
Bei einer individuell spezifischen Maximaldistanz zwischen dem Schreib-/Lesegerät und einem zugeordneten mobilen Daten- träger können Störungen der Kommunikation aufgrund sehr kleiner empfangener Signale auftreten. Die Signalkontinuität kann durch Digitalisierungslücken unterbrochen werden, so dass bei der Abtastung einer übertragenen seriellen Bitfolge Abtast- fehler auftreten.With an individually specific maximum distance between the read / write device and an assigned mobile data Sluggish communication can occur due to very small received signals. The signal continuity can be interrupted by digitization gaps, so that scanning errors occur when scanning a transmitted serial bit sequence.
Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren zur Abtastung einer seriellen Bitfolge aufzubieten, bei welchem Störungen der seriellen Bitfolge bei der Abtastung erkannt und korrigiert werden.The invention has for its object to provide a method for scanning a serial bit sequence, in which faults in the serial bit sequence are detected and corrected during the scan.
Die Aufgabe wird durch die Merkmale des kennzeichnenden Teils des Patentanspruchs 1 in Verbindung mit den Merkmalen des Oberbegriffs gelöst. Vorteilhafte Verfahrensvarianten werden in den Unteransprüchen 2 - 8 beschrieben.The object is achieved by the features of the characterizing part of patent claim 1 in conjunction with the features of the preamble. Advantageous process variants are described in subclaims 2-8.
Das im Schreib-/Lesegerät empfangene HF-Datensignal eines mobilen Datenträgers durchläuft zur Demodulation ein Filterelement des Schreib-/Lesegeräts . Das Ausgangssignal des Fil- terelements dient zur Abtastung und Erkennung der übertragenen seriellen Bitfolge über ein an sich bekanntes Abtastelement.The RF data signal of a mobile data carrier received in the read / write device passes through a filter element of the read / write device for demodulation. The output signal of the filter element is used to scan and recognize the transmitted serial bit sequence via a scanning element known per se.
Erfindungsgemäß beginnt die Filterung des empfangenen Signals im Filterelement des Schreib-/Lesegeräts bei Detektion eines ersten Flankensignals, z.B. vereinbarungsgemäß eines logischen 1-0-Ubergangs . Nach Beginn der Filterung (Triggerung des Filterelements) durchläuft das gefilterte Signal das Filterelement bei Abwesenheit von Störungen in der Filterzeit F. Danach beginnt die Abtastung des Ausgangssignals des Filterelements mit einer Abtastzeit AI und das Startbit und die weiteren Datenbits der seriellen Bitfolge jeweils mit äqui- distanten Abtastzeiten A2 werden abgetastet, bis das Ende der seriellen Bitfolge, also des übertragenen Bytes, erreicht ist. Erfindungsgemäß wird eine Störung der zu filternden und abzutastenden Signalfolge detektiert, falls ein zweites Flankensignal des empfangenen Signals vor dem Ablauf der Filterzeit F festgestellt wird. Beim Auftreten einer derartigen Störung wird die Zeitdauer t der Störung erfasst.According to the invention, the filtering of the received signal in the filter element of the read / write device begins when a first edge signal is detected, for example, according to the agreement, a logical 1-0 transition. After the start of the filtering (triggering of the filter element), the filtered signal passes through the filter element in the absence of interference in the filter time F. Then the sampling of the output signal of the filter element begins with a sampling time AI and the start bit and the further data bits of the serial bit sequence each with distant sampling times A2 are sampled until the end of the serial bit sequence, that is to say the transmitted byte, has been reached. According to the invention, a fault in the signal sequence to be filtered and scanned is detected if a second edge signal of the received signal is determined before the filter time F has elapsed. When such a disturbance occurs, the time period t of the disturbance is recorded.
Wenn nun eine einzige Störung mit der Zeitdauer ti vorliegt, findet eine erfindungsgemäße Korrektur des Beginns der Abtastung der seriellen Bitfolge statt, indem die sich an die Fil- terzeit F anschließende Abtastzeit AI um den Zeitraum 2tι vermindert wird. Nach Ablauf dieser verminderten Abtastzeit AI beginnt die Abtastung des Startbits und der weiteren Datenbits mit äquidistanten und unveränderten Abtastzeiten A2 bis die serielle Bitfolge vollständig abtastet und abge- schlössen ist.If there is now a single disturbance with the time period ti, a correction according to the invention of the start of the scanning of the serial bit sequence takes place by reducing the scanning time AI following the filter time F by the time period 2tι. After this reduced sampling time AI has elapsed, the sampling of the start bit and the further data bits begins with equidistant and unchanged sampling times A2 until the serial bit sequence has been completely scanned and completed.
Beim erfindungsgemäßen Verfahren werden somit während der Übertragung des Startbits einer seriellen Bitfolge auftretende Störungen erfasst und eine entsprechende Korrektur des Beginns der Abtastung der seriellen Bitfolge eingeleitet. Damit wird der Anfang der seriellen Bitfolge, nämlich die Abtastung des Startbits zuverlässig auch bei auftretenden Störungen erreicht.In the method according to the invention, faults occurring during the transmission of the start bit of a serial bit sequence are thus detected and a corresponding correction of the start of the scanning of the serial bit sequence is initiated. The beginning of the serial bit sequence, namely the sampling of the start bit, is thus reliably achieved even in the event of faults.
Das erste und das zweite Flankensignal sind insbesondere entgegengesetzte Signale. Bei einer Signaldefinition der Ruhelage als logische „1* kann das erste Flankensignal als logischer 1-O-Ubergang und das zweite Flankensignal als logischer 0-1-Übergang realisiert sein.The first and second edge signals are, in particular, opposite signals. If the rest position is defined as a logical “1”, the first edge signal can be implemented as a logical 1-O transition and the second edge signal as a logical 0-1 transition.
Wenn mehrere Störungen während der Übertragung der Startbits vorliegen, werden diese auch in ihrer Gesamtzeitdauer T erfasst und es findet eine entsprechende verstärkte Korrektur des Beginn der Abtastung mit einer entsprechend verminderten Abtastzeit AI statt. Erfindungsgemäß soll die Gesamtzeitdauer T der einzelnen Störungen mit den einzelnen Zeitdauern t die Hälfte der ersten Abtastzeit AI nicht überschreiten, da ansonsten keine erfindungsgemäße Korrektur des Beginns der Abtastung stattfinden kann.If there are several faults during the transmission of the start bits, these are also recorded in their total time period T and there is a correspondingly increased correction of the start of the scan with a correspondingly reduced scan time AI. According to the invention, the total time period T of the individual faults with the individual time periods t should not exceed half of the first sampling time AI, since otherwise no correction according to the invention of the start of the sampling can take place.
Das erfindungsgemäße Verfahren ermöglicht eine Erfassung und Korrektur von Störungen, die während des Empfangs des Startbits einer seriellen Bitfolge auftreten. Diese Störungen wer- den durch entsprechende Verminderung einer voreingestellten Abtastzeit AI korrigiert, so dass der Beginn der Abtastung mit den äquidistanten Abtastzeiten A2 unter korrekter Zuordnung zum Startbit der seriellen übertragenen Bitfolge stattfindet.The method according to the invention enables the detection and correction of faults which occur during the reception of the start bit of a serial bit sequence. These disturbances are corrected by a corresponding reduction in a preset sampling time AI, so that the beginning of the sampling with the equidistant sampling times A2 takes place with correct assignment to the start bit of the serial transmitted bit sequence.
Wenn keine Störungen auftreten, beginnt die Abtastung mit der unverminderten und voreingestellten Abtastzeit AI nach Ablauf einer vollständigen Filterzeit F ohne Detektion einer Störung. Damit ergibt sich eine Gesamtverzögerung des gefilter- ten und abgetasteten Signals, welches sich aus der Summe von Filterzeit F und Abtastzeit AI zusammensetzt.If no disturbances occur, the sampling begins with the undiminished and preset sampling time AI after a complete filter time F without detection of a disturbance. This results in an overall delay of the filtered and sampled signal, which is composed of the sum of filter time F and sampling time AI.
Zur Erfassung der Zeitdauer t jeder einzelnen Störung kann ein Zähler verwendet werden, der bei Beginn der Filterung, also z.B. bei Detektion eines ersten beschriebenen Flankensignals ausgehend von einem Anfangswert (z.B. der Zahl 1) in eine (z.B. zunehmende) Richtung zu laufen beginnt und nach Ablauf der Filterzeit F ohne auftretende Störungen, einen Endwert N (z.B. die Zahl 100) erreicht. Wenn nun Störungen auftreten und diese durch Detektion eines beschriebenen zweiten Flankensignals festgestellt werden, ändert der Zähler seine Richtung und zählt in umgekehrter Richtung, bis wieder ein erstes Flankensignal festgestellt wird.A counter can be used to record the time t of each individual fault, which at the start of filtering, e.g. upon detection of a first described edge signal starting from an initial value (e.g. the number 1) starts to run in a (e.g. increasing) direction and after the filter time F has passed without any disturbances occurring, it reaches an end value N (e.g. the number 100). If disturbances now occur and these are detected by detection of a second edge signal described, the counter changes its direction and counts in the opposite direction until a first edge signal is detected again.
Der Beginn der Abtastzeit AI wird erst dann ausgelöst, wenn der Zähler ausgehend vom Anfangswert den Endwert erreicht. Das Verfahren ist anhand der Zeichnungsfigur an einem Ausführungsbeispiel näher dargestellt.The start of the sampling time AI is only triggered when the counter reaches the end value from the start value. The method is shown in more detail with the aid of the drawing figure using an exemplary embodiment.
Signal 1 zeigt eine vom Schreib-/Lesegerät empfangene seriel- le Bitfolge, bei dem entsprechend einem vereinbartem Datenprotokoll zur Übertragung von HF-Datensignalen zwischen dem Schreib-/Lesegerät und dem mobilen Datenträger die Ruhelage als logische „1* (kurz: log 1) vereinbart ist. Danach beginnt die übertragene serielle Bitfolge mit einem Startbit (log 0) durch ein erstes Flankensignal, nämlich einen logischen 1-0- Übergang zwischen Ruhelage und Startbit.Signal 1 shows a serial bit sequence received by the read / write device, in which, in accordance with an agreed data protocol for the transmission of HF data signals between the read / write device and the mobile data carrier, the rest position as a logical “1 * (short: log 1) is agreed. The transmitted serial bit sequence then begins with a start bit (log 0) by a first edge signal, namely a logical 1-0 transition between the idle position and the start bit.
Auf das Startbit folgen das erste und weitere Datenbits der gesamten übertragenen seriellen Bitfolge, wobei in der Zeich- nungsfigur nur die ersten drei Datenbits (log 1, log 0 und log 1) der seriellen Bitfolge dargestellt sind.The start bit is followed by the first and further data bits of the entire transmitted serial bit sequence, only the first three data bits (log 1, log 0 and log 1) of the serial bit sequence being shown in the drawing.
Im Filterelement des Schreib-/Lesegeräts wird Signal 1 innerhalb der Filterzeit F (hier: F = 17 μs) gefiltert (vgl. Sig- nal 2) . Nach Ablauf der Filterzeit F ohne Störungen beginnt die Abtastung gemäß Signal 3 im Abtastelement des Schreib- /Lesegeräts mit der ersten Abtastzeit AI (hier: AI = 34 μs) .In the filter element of the read / write device, signal 1 is filtered within the filter time F (here: F = 17 μs) (see signal 2). After the filter time F has elapsed without interference, the scanning according to signal 3 in the scanning element of the read / write device begins with the first scanning time AI (here: AI = 34 μs).
Nach Ablauf von AI beginnen äquidistante Abtastzeiten von A2 (hier: A2 = 52 μs) mit einer Abtastung des Ausgangssignals des Filterelements. Dabei wird die gesamte empfangene serielle Bitfolge beginnend mit dem Startbit, dem ersten und den weiteren Datenbits abgetastet. Das empfangene Signal 1 wurde während der Übertragung des Startbits nicht gestört, so dass die voreingestellte Abtastzeit AI im Anschluss an die Filterzeit F unvermindert beibehalten wurde. Damit wird gemäß Signal 3 die übertragene Bitfolge gemäß Signal 1 mit einer Gesamtverzögerung F + AI (hier also: 17 μs + 34μs = 51 μs) abgetastet.After AI has expired, equidistant sampling times of A2 (here: A2 = 52 μs) begin with sampling the output signal of the filter element. The entire serial bit sequence received is scanned starting with the start bit, the first and the further data bits. The received signal 1 was not disturbed during the transmission of the start bit, so that the preset sampling time AI was retained unabated after the filter time F. According to signal 3, the transmitted bit sequence according to signal 1 is thus scanned with a total delay F + AI (here: 17 μs + 34μs = 51 μs).
Signal 4 zeigt ein während des Startbits gestörtes empfangenes Signal 1 des Schreib-/Lesegeräts, bei dem nach dem ersten Flankensignal, also dem logischen 1-0-Übergang zwischen Ruhelage und Startbit nach einer Zeitdauer von 4 μs die Störung ti mit einer Zeitdauer von 4 μs und nach einer weiteren ungestörten Zeitdauer von 8 μs die Störung t2 mit ebenfalls 8 μs auftritt. Nach dem Ende der Störung t2 beginnt die Filterzeit F wieder zu laufen und wird nicht durch Störungen unterbrochen.Signal 4 shows a received signal 1 of the read / write device which is disturbed during the start bit, in the case of which after the first Edge signal, i.e. the logical 1-0 transition between the idle position and the start bit, the fault ti occurs after a period of 4 μs with a duration of 4 μs and after a further undisturbed period of 8 μs the fault t 2 also occurs with 8 μs. After the end of the disturbance t 2 , the filter time F starts again and is not interrupted by disturbances.
Danach schließt sich die Abtastzeit AI an, jedoch nicht mit dem voreingestellten Wert AI = 34 μs, sondern gekürzt um die doppelte Zeitdauer der Störungen (ti = 4 μs , t2 = 8 μs , mithin um 24 μs) . Damit ergibt sich eine neue verminderte Abtastzeit AI* von 10 μs, nämlich Al*= AI - 2 (ti + t2) (hier: lOμs = 34 μs - 2 (4 μs + 8 μs) ) . Signal 6 ist somit ein mit einem korrigierten Beginn der Abtastung (AI* = 10 μs statt AI = 34 μs) abgetastetes Signal, welches nach Korrektur der Abtastzeit AI wieder mit den äquidistanten und unveränderten Abtastzeiten A2 abgetastet wird. In allgemeiner Form lautet die Formel für die Korrektur des Abtastzeitpunktes AI bei n Störungen mit den Zeitdauern ti, t2 t3 ... tn:This is followed by the sampling time AI, however not with the preset value AI = 34 μs, but shortened by twice the duration of the faults (ti = 4 μs, t 2 = 8 μs, therefore by 24 μs). This results in a new reduced sampling time AI * of 10 μs, namely Al * = AI - 2 (ti + t 2 ) (here: 10 μs = 34 μs - 2 (4 μs + 8 μs)). Signal 6 is thus a signal sampled with a corrected start of the sampling (AI * = 10 μs instead of AI = 34 μs), which is sampled again with the equidistant and unchanged sampling times A2 after correction of the sampling time AI. In general terms, the formula for the correction of the sampling time AI for n disturbances with the durations ti, t 2 t 3 ... t n is
Al*= AI - 2{tι + t2 + t3 + ... + tn)Al * = AI - 2 {tι + t2 + t3 + ... + t n )
Nach Anspruch 4 gilt in allgemeiner Form für T = ti + t2 + t3 According to claim 4 applies in general for T = ti + t 2 + t 3
T < 0,5 * AIT <0.5 * AI
Falls keine Korrektur des Beginns der Abtastung, also keine Verminderung der Abtastzeit AI auftritt, schließt sich nach Ablauf der Filterzeit F gemäß Signal 7 die unverminderte Abtastzeit AI von AI = 34 μs an, an deren Ende die Abtastung mit den Abtastzeiten A2 beginnen würde. Diese Abtastung würde zum Zeitpunkt A im abgetasteten Signal 5 einen logischen „lw- Zustand als Beginn der seriellen Bitfolge feststellen, obwohl gemäß dem korrigierten Signal 6 das Startbit mit logischem „O'-Zustand abgetastet werden müsste. Bei fehlender Korrektur des Beginns der Abtastung der Startbits würde die Abtastung mit der Abtastzeit A2 verspätet auftreten. Der für eine korrekte Abtastung der seriellen Bitfolge unerlässliche Bezug zum Start des Startbits wird somit bei Signal 7 nicht erreicht. Damit würde die übertragene serielle Bitfolge fehlerhaft abgetastet. If there is no correction of the start of the sampling, that is to say no reduction in the sampling time AI, the undiminished sampling time AI of AI = 34 μs follows after the end of the filter time F according to signal 7, at the end of which the sampling would begin with the sampling times A2. At the time A, this sampling would determine a logical “1 w state” in the sampled signal 5 as the beginning of the serial bit sequence, although according to the corrected signal 6 the start bit would have to be sampled with a logical “O'state. If the start of the sampling of the start bits were not corrected, the sampling would be delayed with the sampling time A2. The reference to the start of the start bit, which is essential for a correct scanning of the serial bit sequence, is therefore not achieved with signal 7. This would incorrectly scan the transmitted serial bit sequence.
Claims
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10161631 | 2001-12-14 | ||
| DE10161631A DE10161631B4 (en) | 2001-12-14 | 2001-12-14 | Method for correcting the start of sampling a serial bit sequence of an output signal of a filter |
| PCT/DE2002/004319 WO2003052679A2 (en) | 2001-12-14 | 2002-11-25 | Method for correcting initial sampling of the serial bit rate of a filter's output signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP1454448A2 true EP1454448A2 (en) | 2004-09-08 |
Family
ID=7709309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP02804844A Withdrawn EP1454448A2 (en) | 2001-12-14 | 2002-11-25 | Method for correcting initial sampling of the serial bit rate of a filter's output signal |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20050055616A1 (en) |
| EP (1) | EP1454448A2 (en) |
| CA (1) | CA2470086A1 (en) |
| DE (1) | DE10161631B4 (en) |
| WO (1) | WO2003052679A2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2530550A4 (en) * | 2010-01-27 | 2013-12-25 | Toyota Motor Co Ltd | ANOMALY TESTING DEVICE AND ANOMALY TEST PROCEDURE FOR A CONTROL SYSTEM |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3909724A (en) * | 1973-06-26 | 1975-09-30 | Addressograph Multigraph | Start bit detector and data strober for asynchronous receiver |
| DE4015041A1 (en) * | 1990-05-10 | 1991-11-14 | Siemens Ag | Serial data transmission procedure - using start=stop principle in async. digital bus system |
| JPH0778774B2 (en) * | 1991-02-22 | 1995-08-23 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Short latency data recovery device and message data synchronization method |
| US5208839A (en) * | 1991-05-28 | 1993-05-04 | General Electric Company | Symbol synchronizer for sampled signals |
| JPH04354220A (en) * | 1991-05-31 | 1992-12-08 | Fujitsu Ltd | Start bit detection circuit |
| NL9202069A (en) * | 1992-11-30 | 1994-06-16 | Nedap Nv | Identification system with improved identification algorithm. |
| JP3466738B2 (en) * | 1994-11-21 | 2003-11-17 | ヤマハ株式会社 | Asynchronous serial data receiver |
| US5745502A (en) * | 1996-09-27 | 1998-04-28 | Ericsson, Inc. | Error detection scheme for ARQ systems |
| DE19642017C1 (en) * | 1996-10-11 | 1998-04-02 | Siemens Ag | Data receiving system e.g. for motor vehicle locking system or immobiliser |
-
2001
- 2001-12-14 DE DE10161631A patent/DE10161631B4/en not_active Expired - Fee Related
-
2002
- 2002-11-25 CA CA002470086A patent/CA2470086A1/en not_active Abandoned
- 2002-11-25 WO PCT/DE2002/004319 patent/WO2003052679A2/en not_active Application Discontinuation
- 2002-11-25 EP EP02804844A patent/EP1454448A2/en not_active Withdrawn
-
2004
- 2004-06-14 US US10/865,792 patent/US20050055616A1/en not_active Abandoned
Non-Patent Citations (1)
| Title |
|---|
| See references of WO03052679A2 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2470086A1 (en) | 2003-06-26 |
| WO2003052679A2 (en) | 2003-06-26 |
| US20050055616A1 (en) | 2005-03-10 |
| DE10161631A1 (en) | 2003-07-03 |
| DE10161631B4 (en) | 2004-01-22 |
| WO2003052679A3 (en) | 2003-09-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3706980C2 (en) | ||
| EP1878166B1 (en) | Method and device for decoding a signal | |
| WO2007101767A1 (en) | Method and system for compensating for asymmetric delays | |
| DE3111555A1 (en) | METHOD FOR STORING INFORMATION USING PREVIOUS RECORDING | |
| DE2125528A1 (en) | ||
| EP2742642B1 (en) | Measured value transmitting device | |
| DE2529589C2 (en) | Electronic security system with a signal detector circuit | |
| DE102011101172A1 (en) | Method for multi-address recognition in actuator sensor interface network, involves releasing switching or warning signal during overlapping of response signals, arranging recognition logic in slaves for recognizing multi-addressing | |
| DE3724572C2 (en) | ||
| EP1454448A2 (en) | Method for correcting initial sampling of the serial bit rate of a filter's output signal | |
| DE2719309B2 (en) | Serial data receiving device | |
| DE19909091A1 (en) | Bus system with improved data transmission security | |
| DE4135158C2 (en) | Method for detecting and correcting impulse disturbances in a learnable universal remote control device | |
| EP0727897B1 (en) | Circuit for receiving a signal transmitted on a bus as voltage level variations | |
| EP0236818B1 (en) | Method and circuit arrangement for monitoring subscribers' lines connected to a data switching or data transmission installation | |
| AT500350A1 (en) | APPENDIX FOR TRANSFERRING DATA IN A SERIAL, BIDIRECTIONAL BUS | |
| EP0221936B1 (en) | Automatic correction system for the servo-circuit of a device with optical scanning of a rotating information support | |
| DE2718226A1 (en) | DATA TRANSMISSION SYSTEM FROM A TRANSMITTER AND A RECEIVER | |
| WO2000060794A2 (en) | Diversity method for transmitting data | |
| DE2604763C3 (en) | Device with portable paging receivers which can be called by signals consisting of pulses of a single frequency | |
| DE1537837C2 (en) | Circuit arrangement for frequency-selective dialing code receivers in telecommunication systems, in particular telephone systems | |
| EP0704786B1 (en) | Circuit for eliminating glitches from a framing signal | |
| EP0385158B1 (en) | Pulse spacing decoding | |
| DE102005009874B4 (en) | Method for signaling a state or event | |
| DE10115804A1 (en) | Operating method for data bus for several subscribers involves placing information on bus, which is fault-free during error, after error at time and during period outside error time interval |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 20040422 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SK TR |
|
| GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20050219 |