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EP1206325A4 - Techniques de connexion en phase vapeur - Google Patents

Techniques de connexion en phase vapeur

Info

Publication number
EP1206325A4
EP1206325A4 EP00954052A EP00954052A EP1206325A4 EP 1206325 A4 EP1206325 A4 EP 1206325A4 EP 00954052 A EP00954052 A EP 00954052A EP 00954052 A EP00954052 A EP 00954052A EP 1206325 A4 EP1206325 A4 EP 1206325A4
Authority
EP
European Patent Office
Prior art keywords
conductive elements
conductive
holes
providing
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00954052A
Other languages
German (de)
English (en)
Other versions
EP1206325A2 (fr
Inventor
Belgacem Haba
John W Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera LLC filed Critical Tessera LLC
Publication of EP1206325A2 publication Critical patent/EP1206325A2/fr
Publication of EP1206325A4 publication Critical patent/EP1206325A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/083—Evaporation or sublimation of a compound, e.g. gas bubble generating agent
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/08—Treatments involving gases
    • H05K2203/085—Using vacuum or low pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Definitions

  • the piesent invention relates to microelectronic components and fabiication of microelectionic components
  • a multilayei microelectronic circuit panel may include several dielect ⁇ c layers Each dielect ⁇ c layer has conductors extending along one or both surfaces of the layer in horizontal directions and has vias extending through the layer to connect certain conductors on opposite sides of the panel with one another
  • a multi-layer circuit is fabricated by a sequential process Each dielectric layer is deposited on previously-formed dielectric layers and the processes needed to form the vias and the horizontal conductors are performed Such a sequential buildup process suffers from numerous drawbacks, including significant loss of productivity caused by
  • multi-layer circuit panels can be fabricated using a parallel- processing approach
  • the va ⁇ ous panels constituting the multi-layer structure are fabricated separately and then stacked together with mterposers incorporating a curable dielect ⁇ c matenal such as an epoxy and also incorporating masses of electrically conductive joining material such as solder extending through the mterposer at predetermined locations
  • the stacked assembly is then cured as, for example, under heat and pressure
  • the dielectric material joins the circuit panels to one another and the electrically conductive material forms conductive pathways between conductors on the va ⁇ ous panels Because the individual panels can be tested prior to assembly, defects in the panel manufactu ⁇ ng process do not result m loss of the entire assembly
  • the individual panels can be selectively treated so that vertical connections between panels are made only at certain locations Other processes involving parallel production of multiple circuit panels and assembly
  • the circuit panels typically still include v ias extending through dielectric layers
  • Such vias commonly are formed by providing holes m the dielectnc layers and depositing a conductive metal in the dielect ⁇ c layers by processes such as electroless plating and electroplating These processes work well with relatively large vias
  • it would be desirable to provide smaller vias so as to make the entire assembly more compact It is difficult to form relatively small vias, such as circular vias having diameters less than about 60 microns and, more particularly, less than about 25 microns by plating
  • the contacts of a semiconductor chip may be electrically connected to terminals on a small circuit panel or connection component overlying a face of the chip itself
  • the terminals on the connection component in turn are connected to contact pads on a substrate such as a cncuit panel
  • the connection component is movable with respect to the chip to accommodate dimensional changes caused by thermal effects during manufacture and/or use
  • the connections between the chip contacts and the mterposer can be made by various methods For example, these connections can be made by wire-bonding or by techniques such as thermosonic or ultrasonic bonding of pre-fab ⁇ cated leads on the mterposer to the chip contacts Further improvements in lead bonding are taught, for example, m United States Patent 5,536,909, 5,787,581 and PCT International Publication 94/03036 These processes provide marked improvements m chip connection processes and m the resulting assemblies
  • flip-chip bonding In a process known as flip-chip bonding, contacts on the chip are bonded directly to contact pads on a substrate such as a circuit board using solder balls All of the contacts of the chip may be connected simultaneously
  • flip-chip bonding requires considerable spacing between contacts on the chip to accommodate the solder balls and suffers from other drawbacks including susceptibility to thermal stresses
  • U S Patent 5,407.864 proposes mounting a chip on one surface of a circuit panel so that the contacts of the chip face down onto a top surface of a circuit boaid The contacts on the chip are aligned with through-holes extending through the circuit boaid, to the bottom suiface thereof A metal is deposited through the openings of the through-holes at the bottom surface, as by sputtering, screening, electroplating oi evaporation, so that the deposited metal forms conductive extensions of the chip contacts extending through the holes to conductors on the circuit boaid
  • This method suffers from the obvious drawback that holes must extend through the cncuit board at each chip contact location
  • This, m turn makes it impractical to mount a chip onto a multi-layer circuit panel Moieovei, where the process is performed using an evapoiative technique, the structure, including the chip and the cncuit panel must be retained m the evaporation apparatus for the full time required to deposit the metal Additionally, the resulting struct
  • a method according to this aspect of the invention includes the step of providing fust and second conductive elements and a dielectric so that the dielectric and the conductive elements cooperatively define a substantially closed chambei
  • a dispersible conductive material such as a metal having appreciable vapor pressure is also provided withm the chambei
  • low -melting metals such as tm, gallium, silver, mdium and alloys thereof may be used
  • Other low-melting alloys include alloys containing one or more of tin, bismuth and antimony
  • the method further includes the step of dispersing the conductive material withm the substantially closed chamber so that the conductive material deposits on the dielectric and forms a connector extending between the conductive elements
  • the step of dispersing the conductive material is performed by evaporating the conductive material withm the chambei
  • the chamber desirably is maintained under subatmosphe ⁇
  • the step of providing first and second conductive elements and a dielectric may include pioviding a dielect ⁇ c layer ha ⁇ mg oppositely directed first and second surfaces and having one oi moie holes extending through the layer between the surfaces, and providing the first and second conductive elements so that they overlie the hole on the first and second surfaces of the dielectric layer
  • the first conductive elements, the second conductive elements or both may be provided on separate bodies bearing these elements These bodies may be laminated onto the dielectric layer, thereby forming one or more chambers as discussed above
  • the conductive material may be provided on the conductive elements as, for example, by depositing the conductive material through one or more techniques such as electroplating, electroless plating, sputtering, evaporation and chemical vapor deposition
  • the process of evaporation simply requires maintaining the assembly at a suitable temperature for a sufficient time to allow the conductive material to redistribute itself withm the chambers by evaporation
  • the assembly may be maintained under an external, surrounding subatmosphe ⁇ c pressure as, for example, by holding the assembly withm a temporary housing or storage bin held at subatmosphe ⁇ c pressure so as to minimize mechanical stress on the assembly and minimize diffusion into the chamber or chambers
  • the evaporation process may occur, for example, withm a simple oven or holding fixture
  • connections can be formed simultaneously using these methods For example, hundreds or thousands of connections can be formed between individual conductive elements of an assembly during a single evaporation step
  • the process is inherently reliable, provided that the conductive matenal is present and the conductive elements are exposed to the interior of the chamber, the conductive material will form a conductor connecting the conductive elements Moreover, the evaporation process can be repeated after the assembly is tested to repair any defects detected dunng testing operation If an assembly has defects, the assembly is simply recycled into the heating step, without further processing Unlike conventional ia-formmg piocesses such as electroplating, the process according to this aspect of this invention works best with small holes For example, holes having cross-sectional dimensions on the ordei of 60 micrometers or less, and more prefeiably 25 micrometers (about 0 001 inches) oi less may be used successfully The process thus lends itself well to fabncation of extremely compact, high density circuits
  • a furthei process includes the step of providing a first dielectric layer having first and second surfaces and having a plurality of holes extending thiough such layei between the first and second surfaces and providing first conductive elements adjacent the first surface and second conductive elements adjacent to second suiface so that these conductive elements aie aligned with at least some of the holes
  • the step of providing the first conductive element may include providing a first body having the conductive elements thereon juxtaposed with first surface of the dielectric layer
  • the second conductive elements may be provided on a similar, second body juxtaposed with the second surface of the dielectric layer
  • a method desirably further includes the step of providing a conductive material in at least some of the holes which have the first and second conductive elements aligned therewith and dispersing the conductive materials, preferably by e ⁇ aporatmg the conductive mate ⁇ als, so as to form conductors interconnecting the first and second conductive elements which are aligned with at least some
  • At least one of the steps of providing first conductive elements, providing second conductive elements, and providing conductive material may be performed selectively so that the first conductive element, the second conductive element, or the conductive material is omitted at least some of the holes and hence no connection is made between first and second conductive elements at those holes
  • the process therefore can be used to form connections selectively
  • selective formation of conductive elements and/or selective application of conductive material can be achieved readily using known techniques such as selective plating or etching, screen printing and selective vapor deposition, as for example, using a mask to block vapor deposition in areas where deposition is not wanted
  • the process may incorporate the step of providing a stacked structure including one or more dielectric layers and plural layers of conductive elements separated from one another by these one or more dielect ⁇ c layers At least some of the conductive elements m different layers are aligned with one another at one or more sites and the dielectric layers have holes extending through them between the aligned conductive elements at at least some of the sites
  • a stacked structure including one
  • the one or more dielectric layers typically includes numerous dielect ⁇ c layers
  • the vertical conductors extending through the stacked structure can be provided selectively by conducting any one of several steps selectively
  • the step of providing holes m the dielectric layers may be performed selectively so that holes are provided at less than all of the sites
  • the holes may be disposed at locations of a regulai grid pattern, but less than all of such locations may be provided with holes
  • the step of applying the evaporable conductive material may be performed selectively For example, where the conductive material is applied onto the conductive elements before stacking as, for example, where the conductiv e material is applied by plating, the conductive material may be applied selectively by masking areas where conductive material is not wanted before plat
  • the layers of conductive elements may include first direction and second direction layers arranged m alternating order
  • the conductive elements m each first direction layer include elongated traces extending predominantly in a first horizontal direction whereas the conductive elements in each second direction layer have elongated traces extending predominantly m a second ho ⁇ zontal direction transverse to the first horizontal direction
  • the holes are desirably arranged at at lest some locations of a regular grid pattern corresponding to crossing points of the first direction and second direction traces Such an arrangement provides complete flexibility m layout of the circuit Moreover, because very small vias can be employed, there is no need to provide enlarged features at the crossing points
  • the conductive matenal may be dispersed withm the chambers by processes which do not entail evaporation as, for example, by applying sonic energy to atomize the conductive matenal m a liquid state or to mechanically spread the liquid conductive material
  • the process desirably does not rely upon filling of the chamber or via with liquid
  • a conductive material precursor is provided within the closed chambers and reacts to form a conductive matenal within the closed chambers BRIEF DESCRIPTION OF THE DRAWINGS
  • Figure 1 is a diagrammatic perspective view depicting certain components used n one embodiment of the invention
  • Figure 2 is a diagrammatic sectional view depicting the components of Fig 1 during an assembly piocedure in accordance with one embodiment of the invention
  • Figure 3 is a diagrammatic sectional view depicting components m accordance with a further embodiment of the invention.
  • Figure 4 is a diagrammatic sectional view depicting the components of Fig 3 m conjunction with another element during a later step of the process
  • Figure 5 is a diagrammatic top plan view depicting a component m accordance with yet another embodiment of the invention
  • Figuie 6 is a diagrammatic sectional view taken along line 6-6 m Fig 5
  • Figure 7 is a view similar to Fig 6 but depicting the component m conjunction with another element during a later stage of a manufactu ⁇ ng process
  • Figure 8 is a fragmentary, diagrammatic sectional view depicting components in accordance with another embodiment of the invention
  • Figure 9 is a diagrammatic elevational view of the components shown m Fig 8
  • Figure 10 is a diagrammatic elevational view depicting components in accordance with a further embodiment of the invention
  • Figure 11 is a fragmentary, partially-sectional perspective view depicting components m accordance with yet another embodiment of the invention
  • Figure 12 is a diagrammatic, partially-exploded view depicting certain components during a process according to a further embodiment of the invention
  • Figure 13 is a diagrammatic sectional view depicting components used m a further embodiment of the invention.
  • Figure 14 is a fragmentary, diagrammatic sectional view depicting components and process equipment dunng a method according to yet another embodiment of the invention
  • Figure 15 is a diagrammatic elevational view depicting components and process equipment during a method according to a still further embodiment of the invention
  • Figure 16 is a fragmentary, partially sectional elevational view depicting an assembly according to another embodiment of the invention MODES FOR CARRYING OUT THE INVENTION
  • a process in accordance with one embodiment of the invention utilizes a set of bodies 20 of a fust type and bodies 22 of a second type
  • Each body 20 includes a sheet-like dielectric layer having a top surface 24 and an oppositely directed bottom surface 26
  • each layer 20 is formed from a sheet of polyannde approximately 25-100 microns thick
  • Each of the bodies or layers 20 has a coating or sublayer 21 of a heat- curable bonding material on its bottom surface Bonding material layei 21 may be integral w ith body or layer 20 or else may include a distinct adhesive differing in composition from the remainder of the body or layer 20
  • Suitable adhesives include those commonly used in manufacture of laminated flexible circuits for high-temperature service, such as polyamides, epoxies and cyanate-PTFE materials
  • Each layer 20 also has holes 28 extending through it, from its top surface 24 to its bottom surface 26 These holes are arranged at locations of a regular, rectilinear grid pattern having columns of holes extending in a first or x horizontal direction and having rows of holes extending in a second or y horizontal direction orthogonal to the first or x-direction
  • the holes need not be provided at every location of the regular grid pattern For example, one hole is omitted at a location 30 withm the grid pattern
  • a typical layer may have tens, hundreds or thousands of holes and may have omitted holes at many locations of the regular grid patterns
  • each hole is less than about 60 microns in diameter, more preferably less than about 25 microns in diameter and most preferably about 12 5 microns in diameter or less
  • the dielectric layers 20 may be solid dielect ⁇ c Alternatively, some or all of the dielectric layers in bodies 20 may incorporate conductive elements disposed m the interior of the dielectric layers For example,
  • Each layer 20 also includes traces 32 extending along the top surface of the layer
  • the traces 32 on bodies 20 extend predominantly in the first or x direction, although some portions of the traces extend m other directions as well
  • the trace pattern is greatly simplified for clarity of illustration
  • a typical pattern of traces will include hundreds of traces
  • traces may be broken or continuous
  • trace 32a has a break 34 at one location. At least some of the traces 32 extend over the top ends of holes 28. Stated another way, the traces extend over locations of the regular grid pattern of the holes.
  • the holes and traces can be formed by essentially any conventional technique used in fabrication of microelectronic circuit panels.
  • the traces can be formed by subtractive etching from a sheet of copper or other conductive metal overlying the top surface of the body by using a photoresist or other patternable masking material to control the etchant process and leave the undesired traces.
  • the traces can be formed by conventional additive plating.
  • the holes may be formed by laser ablation or chemical etching of the dielectric layer again using a photoresist or other mask.
  • the dielectric layer itself may be formed from a photosensitive dielectric and the holes may be formed by selective exposure and curing of the dielectric.
  • Dielectric bodies 22 of the second type are essentially the same as bodies 20.
  • Each body 22 has a top surface 23, a bottom surface 25, and a curable bonding material 27 on its bottom surface 25.
  • Each body 22 has holes 39 extending through it.
  • the traces or conductors 38 on layers 22 extend predominantly in the second or y horizontal direction.
  • Spots of a high vapor pressure conductive metal 40 are disposed on the top surfaces of traces 38.
  • Similar spots of conductive metal 42 are disposed on the top surfaces of the traces 32 of first-direction layers 20.
  • the spots 40 and 42 are disposed in regular grid patterns with spacing in the first and second horizontal directions equal to the spacing used in the regular grid pattern of the holes.
  • the spots of high vapor pressure conductive material are omitted from body 20a, which will form the top layer in the stack.
  • bodies 20 having leads extending in the first or x direction are stacked in alternating order with bodies 22 having traces extending in the second or y direction.
  • the grid of conductive material spots 40 on each second-direction body 22 is aligned with the grid of holes 28 in the next higher first- direction layer 20 in the stack.
  • the grid of conductive material spots 40 on second-direction layer 22a is aligned with the grid of holes 28 in the next higher layer 20a.
  • the grid of conductive material spots 32 on first-direction layer 20b is aligned with the grid of holes 39 in the overlying second-direction layer 22a.
  • the layers are disposed in a vacuum lamination apparatus having an enclosed chamber and having a pair of opposed platens inside the chamber.
  • the chamber is flushed with an inert gas and brought to a substantial vacuum. This process is repeated to assure that the holes in all of the layers have been substantially flushed with the inert gas, and then the chamber is brought to a lower, subatmospheric pressure desirably about 200 Torr or less and more desirably about 10 Torr or less. Still lower pressures, of about 1 Torr or less can be used.
  • the layers may be held apart from one another by temporary spacers (not shown) to assure good communication between each of the holes and the surrounding atmosphere within the chamber. Alternatively, the flushing and the evacuation process can be perfonned before the layers are stacked on one another.
  • hole 39a has a first conductive element (trace 32a on layer 20b); a second conductive element (trace 38a at the top surface of layer 22a) and a dielectric (the dielectric of layer 22a) cooperatively defining a substantially closed, sealed chamber, and has a conductive material 42 disposed within such chamber.
  • first conductive element trace 32a on layer 20b
  • second conductive element trace 38a at the top surface of layer 22a
  • dielectric the dielectric of layer 22a
  • the joints between the layers are gas-tight, so that each hole is sealed.
  • the atmosphere within each hole consists essentially of inert gas at a low subatmospheric type of pressure corresponding to the pressure used in the vacuum chamber during the lamination step.
  • the assembly After lamination, the assembly is maintained at an elevated temperature for a time sufficient to evaporate some or all of the metal in spots 40 and 42.
  • the upper limit of the temperature used in this stage of the process should not exceed the degradation temperature of the materials constituting bodies 20.
  • typical polyamides degrade at temperatures of about 350-400 °C.
  • the pressure within the sealed chambers defined within the bodies increases with temperature. The temperature used in this stage should not be so high as to raise the pressure above the pressure prevailing on the exterior of the laminate. Thus, the internal pressure within the sealed chambers should not exceed atmospheric pressure when the assembly is maintained under normal atmospheric pressure during this stage of the process.
  • the bodies include organic polymers, the degradation temperature of the polymer normally controls.
  • the evaporated metal deposits as a coating on the interior walls of holes 28 and 39, and forms electrically conductive vias or vertical, z-direction conductors 50 extending through the various layers at the holes.
  • the vertical conductors join the conductive elements or traces bounding the various holes and thus forms vertical conductive paths through the stacked structure.
  • one such vertical conductive path extends almost entirely through the stack, from trace 32a at the top of layer 20a downwardly through hole 28a, hole 39a and so on through other holes to trace 32c at the top of the lowermost layer 20d
  • the conductive via lmers 50 also form connections with such internal conductive features Foi example, potential plane element 36 is electrically connected to the vertical conductor at hole 28b
  • the vertical conductive paths are provided selectively Thus, a vertical via oi conductiv e path through an individual layer is provided only where three conditions are met First, there must be a hole at such location, no path is formed at location 30 where a hole is omitted Second, there must be traces or conductive elements adjacent both ends of the hole For example, no trace oveihes the top end of hole 39c in layer 22c near the bottom of the stack Therefore, no vertical connection will be formed at this hole Third, the evaporable conductive material must be present withm the hole For example, at hole 39d, no conductive material is provided and hence no vertical connection will be formed Thus, the formation of vertical connections can be controlled by providing holes selectively, by providing conductive elements selectively and by providing the evaporable conductive matenal selectively, as well as by any combination of these measures Additionally, the locations and extent of vertical and honzontal conductive pads through the stacked assembly can be controlled by selective formation or interruption of the traces or conductive pads along the surfaces of the bodies For example, a break
  • the conductive elements should be substantially free of contaminants, particularly oxides, which may interfere with formation of a good, low resistance joint between the deposited conductive material and the conductive element or trace Where the traces are formed from a reactive metal such as copper, they will typically have an oxide layer
  • the oxide layer can be removed by baking m a atmosphere having very low partial pressure of oxygen as, for example, by holding the bodies bearing the conductive elements m a vacuum chamber at an elevated temperature
  • the reactive metal may be coveied with a non-ieacti e metallic surface coating such as a gold layei
  • a gold layer is applied over a coating of nickel
  • the assembly need not be maintained between the platens of the lamination process
  • each assembly can be laminated in a brief heating and pressing opeiation and then transferred to an oven for the evaporation operation
  • the assemblies can be handled in bulk m the
  • a first set of closed chambers can be formed by stacking a first set of parts, and the conductors can be formed m those chambers Then, one or more additional layers are added to form further chambers, and the conductor-forming steps are repeated This cycle of operations can be repeated add still more layers and form more conductors, until the desired number of layers have been added
  • a process accoiding to a furthei embodiment of the invention begins with a semiconductor wafer 100 having contacts 102 on a first oi front surface
  • the wafer desirably also has passivation layer 104 overlying the front surface except at contacts 102
  • the wafer incorporates internal electronic devices (not shown) electrically connected to contacts 102
  • Contacts 102 are treated to provide a good electrical connection with the material to be evaporated in latei stages of the process and also to prevent undesired reactions between the conductive metal to be evaporated and the material of the contacts
  • the zmcated aluminum contacts may be covered with a layer of nickel followed by an over-coatmg of gold
  • a high vapor pressure conductive metal 103 is applied onto contacts 102 using a conventional deposition process such as sputte ⁇ ng or evaporation
  • a mask is used during the sputtering or evaporation process so that the conductive material is deposited only on contacts 102
  • Other methods of applying the high vapor pressure metal can be employed
  • the high vapor pressure metal can be applied by depositing balls of the metal onto the contacts and melting the metal, using the same techniques as employed in application of conventional solder balls
  • the high vapor pressure metal may be applied by contacting the front face of the wafer with the metal in liquid form, using a technique similar to wave soldering The techniques taught m
  • each lead desirably is releasably attached to the top surface of layer 106, whereas the fixed end 114 of each lead desirably is securely attached to layer 106
  • Lead structures suitable for this purpose are disclosed m commonly assigned United States Patent 5,518,964, 5,904,498 and m co-pending, commonly assigned international application PCT US/99/02748 and United States Patent applications 09/020,750 and 09/195,371 the disclosures of which are hereby incorporated by reference herein
  • the lead sections may have differing bond strengths on different portions of the top layer
  • the tip end of the lead may be connected to the supporting dielectric by a small metallic or dielectric element which can be broken or dislodged readily
  • Layer 106 is laminated to wafer 100 using gas flush and vacuum lamination techniques similar to those discussed above m connection with formation of the stacked assembly
  • the dielectric layer 106 with its cured adhesive layer 108 forms a gas-tight seal to the wafer
  • Each hole 110 is sealed by the dielectric layer, by the fixed end 114 of the overlying conductoi 112 and by the wafer and contact 102 itself
  • Each holes contains an inert gas atmosphere at a low subatmospheric pressure as discussed above
  • the assembly is held at an elevated temperature so as to evaporate the conductive material 103 from each contact 102 and to the mtenor of the hole 110 and thereby form a vertical connector extending between the contact and the fixed end 114 of the associated lead
  • the wafer is engaged with a further element 122 having pads 124 exposed on a bottom surface 126
  • the further element may be a single-layer or multi layer st ⁇ cture having terminals 128 exposed at the top surface 130
  • Pads 124 are bonded to the tip ends 116 of the leads by activating the bonding matenal 118 earned on the tip ends of the leads Typically, the bonding material is activated by engaging the components under heat and pressure
  • element 122 is moved away from wafer 100 and away from dielectric layer 106 through a predetermined vertical displacement
  • These components may also move relative to one another in a horizontal direction Movement of these components relative to one another bends the leads towards a vertically extensive disposition Dunng or after movement of the components, a flowable, curable composition is introduced between the components and cured to form a dielectric, desirably compliant layer
  • dielectric layer 206 has numerous generally U-shaped slots 250 extending through it and subdividing the dielectric layer into a mam region 251 and a plurality of elongated lead regions 252 Holes 210 are formed in the mam region 251 of the sheet adjacent to each lead region Elongated conductors 212 extend from the main region of the sheet onto each lead region 252 Each such conductor overlies one hole 210 and has a bonding material 218 at the tip end of the lead region, remote from the mam region
  • the conductive, evaporable material 203 is provided on the undersides of conductors 212, withm holes 201
  • the adhesive layer 208 used to secure dielect ⁇ c layer 206 to the front surface of wafer 200 is a UN-degradable or other radiation degradable adhesive matenal
  • the lamination and evaporation steps are performed in substantially m the same way as discussed above so as to form vertical conductors 220 connecting contacts 202 with conductors 212 Before, or more desir
  • a component 300 in accordance with another embodiment of the invention incorporates numerous dielectric layers 302 and tiaces 304 extending between these dielectric layers
  • At least some of the traces 304 and vertical conductois 308 are arranged m pairs oi sets
  • the bottom suiface of body 300 has numerous leads 310 As best seen m Fig 8, each lead 310 includes a plurality of conductors 312 and 314, as well as a dielectric layer 316 separating the conductors from one another
  • the conductors 312 and 314 are connected to contacts 318 and 320 of a semiconductor device 322 such as a chip or wafer
  • the contacts 318 and 320 connected to each lead desirably are adjacent one another and may be connected to the same internal electronic device 324 disposed withm chip or wafer 322 As explained in greater detail
  • the controlled impedance signal paths provided m this arrangement may be used to conduct signals between different elements of chip or wafer 322 l e , to conduct signals with a single chip or wafei
  • traces 304c and 304d and the associated leads 310a and 310b provide a low impedance signal path between two widely separated electronic devices withm chip 322, as well as a path for conduction to external terminals 326
  • Provision of a low impedance signal path in turn allows rapid propagation of signals between widely separated elements of the chip and simplifies the task of loutmg signals withm the chip
  • the ability of the present invention to fomi connections withm small holes provides for a particularly compact assembly
  • the vertical conductors may be formed withm holes of different sizes and types
  • a vertical conductor 332 is formed withm hole 330 extending through several polymenc layers, whereas another vertical conductor is formed at the hole overly
  • the vapor phase connection process may be used within an assembly composed entirely of bodies formed from silicon or other semiconductor mate ⁇ als
  • a composite chip or wafer can be made by stacking chips 400, 402, and 404 Chips 400 and 404 may contain active semiconductor electronic devices 405, whereas the middle chip 402 may incorporate only insulating layers and conductors 406 Holes 408 m chip 402 may be aligned with contacts on the other chips and an evaporable conductive material may be evaporated withm the holes m substantially the same way as described above
  • the process of evaporation may occur simultaneously with a process of fusion which binds the chips together and fuses the same into a solid unit
  • such a process may occur at a relatively high temperature and may involve the fusion of silicon or other elements at the mating surfaces
  • such a fusion process may involve activation of a high- temperature adhesive or a eutectic bonding matenal
  • traces 406 may formed from a metal such as copper, gold, platinum or other metals which are difficult to deposit m conventional semiconductor fabncation processes or which have deleterious effects on active devices when present m close proximity to the active devices
  • the vapor phase connection process serves to unite these conductors with electronic devices 405 m chips 400 and 404
  • the conductois 406 are electrically connected to the devices 405, the conductois remain isolated from the devices so that little or no diffusion of the conductoi material into the devices occurs during fabrication or use Stated another way, the connections formed by the vapor phase connection process maintain chemical isolation
  • chips 400 and 404 may be formed by mutually incompatible processes or formed from mutually incompatible materials as, for example, where chip 400 is formed from a
  • an assembly includes a dielectric layer 500 having one or more conductors 502 disposed adjacent a top surface These conductors extend predominantly m first or x direction Dielectnc element 500 has holes 504 in the form of elongated slots extending generally in the x direction beneath some portions of conductors 502
  • Dielectnc element 500 has holes 504 in the form of elongated slots extending generally in the x direction beneath some portions of conductors 502
  • Another element such as a dielect ⁇ c layer or body 506 has conductors 508 extending predominately m a second or y direction transverse to and desirably orthogonal to the first or x direction
  • Conductors 508 have elongated masses of conductive matenal 510 thereon
  • bodies 500 and 506 are remote from one another. In a joining process, the bodies are engaged with one another in the same manner as described above and the conductive material 510 is evaporated so as to form a vertically extending conductor within each slot 504.
  • elongated conductive elements and slots in this embodiment helps to assure that a reliable connection will be made even if one or both of the elements is slightly out of nominal positron.
  • the connection will be made. Misalignment in the first or x direction will simply move the connection slightly along the length of slot 504 and trace 502, whereas misalignment in the y direction will simply move the interconnection along the lead 508. Tolerance sensitivity can be further reduced by providing the evaporable conductive material within slot 504. In this case, so long as slot 504 intercepts some portion of lead 508, the connection will be made.
  • the vapor phase connection process typically works best with relatively small holes.
  • the minimum dimension or width w of the hole or slot 504 desirably is less than about 60 microns and more desirably 25 microns or less.
  • the chambers are formed by providing openings in adhesive layers, so that the adhesive layer itself serves as the dielectric element which cooperatively defines the chamber.
  • the assembly shown in Fig. 12 includes several dielectric bodies 620.
  • Each dielectric body includes traces 602 extending on its top surface and traces 604 extending on its bottom surface. Traces 602 on all bodies other than the topmost body 620a are provided with an evaporable conductive material over their entire surfaces.
  • Adhesive layers 625 are provided on the top surfaces of the dielectric bodies other than the topmost body. These adhesive layers cover traces 602. Prior to laminating the layers, the adhesive is removed selectively to form holes 622 over traces 602 only at those locations where connections are to be formed.
  • the adhesive may be removed by laser ablation or by selective treatment with a solvent using a mask to protect areas which are not to be removed.
  • the layers are then laminated.
  • Adhesive layers 625 hold bodies 620 together, and insulate the traces 602 on the top of each dielectric layer from the traces 604 on the bottom surface of the next adjacent layer except at locations where holes are provided in the adhesive layers.
  • Holes 622 in the adhesive layers form chambers between the bodies 620.
  • the evaporable conductive material on traces 602 at holes 622 can be evaporated and deposited within these chambers to form conductive connections to the traces 604 in the same manner as discussed above.
  • the holes formed in the adhesive layers may have any of the configurations discussed above, such as round holes or elongated slots.
  • the adhesive layers may be provided in separate, self-supporting elements, referred to herein as "interposers".
  • Each such interposer may consist entirely of the adhesive. More typically, each interposer may include one or more sublayers such as structural reinforcements, electrically conductive elements or both, with the adhesive being disposed on opposite sides of the reinforcements.
  • the interposers may include internal structures as shown in commonly assigned United States Patents 5,367,764 and 5,282,312, the disclosure of which is hereby incorporated by reference herein. For example, an interposer 725 depicted in Fig.
  • the 13 includes a dielectric reinforcing layer 726 and layers of adhesive 727 and 728 on oppositely-facing top and bottom surfaces of the reinforcing layer, so that the adhesive layers define the first surface 731 and second surface 733 of the interposer. Holes 730 extend through all of these layers. Bodies 740 and 742 are laminated to the first and second surfaces, respectively, of the interposer. Conductive elements 744 on body 740 and conductive elements 746 on body 740 are aligned with holes 730 and thus exposed to the holes adjacent opposite ends of each hole. The conductive elements, bodies and interposer cooperatively define chambers in substantially the same manner as discussed above. A conductive material is provided within each such chamber, also in the same manner as discussed above.
  • the conductive elements may bear the conductive material.
  • the conductive material is evaporated within the chambers as described above, so as to form electrical conductors extending between the conductive elements associated with each hole.
  • the interposers may include metallic sheets having holes therein and dielectric material coated on the metallic sheets and lining the holes as disclosed, for example, in certain embodiments of United States Patents 5,590,460 the disclosure of which is hereby incorporated by reference herein. The coating may be performed selectively so as to leave the conductive sheet uncoated in the interiors of at least some of the holes. Electrical connections to the conductive sheet will be formed when the conductive material is dispersed in such holes as discussed above with reference to hole 28b, Fig. 1.
  • the conductive material is dispersed by conversion to a gaseous phase through application of heat, and deposited from the gaseous phase onto the walls of the holes so as to form the conductors.
  • energy may be supplied to promote dispersion of the conductive material by application of an electromagnetic, acoustical or ladiant eneigy as, for example, by inductive or microwave heating 01 a irradiation of the assembly with isible or infrared light or other ladiant energy
  • an ultrasonic energy applicator 800 dnven by a conv entional ultrasonic vibration source (not shown) is swept m a direction of movement M across one surface of the assembly while the opposite surface is supported on a support 802
  • the applicator thus applies ultrasonic energy to various sections of the assembly se ⁇ atim, so that conductors are formed in different holes at different times In the position shown, conductors have already been formed in holes 804, conductors are being formed m holes 806, and conductors have yet to be formed in holes 808
  • a localized heating device or a beam of radiant energy can be swept over the assembly in the same way Also, more complex sweep patterns such as raster scanning with or without momentary dwell at locations where the energy is directed onto holes may be employed
  • the relative motion between the energy applicator and the assembly may be imparted by motion of the assembly, by motion of the applicator, or both For example, as seen m
  • the dispersible conductive material is piovided in the fonn of a metal and does not change composition during the process
  • a conductive material may be provided withm the closed chambers by providing one oi more materials which decompose or otherwise react to yield a metal or other conductive matenal which disperses withm the chamber and deposits on the walls of the chamber
  • conductive material precursor is used in this disclosure to refer to such materials
  • a conductive material precursor may be provided as a single component or as multiple components which are mixed with one another withm the chambers
  • Some conductive material precursors include , for example, metal hyd ⁇ des, metal azides and metal acetates The reaction may occur in the vapor phase or m a liquid phase
  • a semiconductor device such as a chip or wafer is connected to another element through leads
  • the invention can be employed to make connections between a semiconductor device and another element without the use of leads
  • a semiconductor device 900 such as a chip or wafer having a front surface 902 and contacts 904 on such front surface is mounted to a substrate 906 having contact pads 908 on a top surface 909
  • Device 900 is mounted to the substrate by a dielectric layer 910 having holes 912 therein
  • the front face 902 of the semiconductor device faces toward the top surface 909 of the substrate
  • the holes 912 are aligned with contacts 904 and pads 908
  • Dielectric layer 910 may include adhesives, and may be provided in any of the ways discussed above For example, the layer may be applied as a coating on the device or on the substrate, and holes 912 may be formed in registration with the contacts or pads
  • the holes form chambers with conductive elements exposed therein A dispersible

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

On effectue des connexions électriques entre une paire d'éléments (32, 38) placés sur le côté opposé d'un alésage (28) s'étendant à travers une couche de diélectrique, (20) par évaporation d'un matériau conducteur (40) tel qu'un métal présentant une tension de vapeur élevée dans ledit alésage, tout en maintenant cet alésage dans un état sensiblement étanche. On peut exécuter ce procédé simultanément de façon à former de nombreuses connexions dans une unité micro-électronique, par exemple, dans un panneau de circuit multicouche.
EP00954052A 1999-08-11 2000-08-11 Techniques de connexion en phase vapeur Withdrawn EP1206325A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14823399P 1999-08-11 1999-08-11
US148233P 1999-08-11
PCT/US2000/022227 WO2001011662A2 (fr) 1999-08-11 2000-08-11 Techniques de connexion en phase vapeur

Publications (2)

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EP1206325A2 EP1206325A2 (fr) 2002-05-22
EP1206325A4 true EP1206325A4 (fr) 2006-08-02

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EP00954052A Withdrawn EP1206325A4 (fr) 1999-08-11 2000-08-11 Techniques de connexion en phase vapeur

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EP (1) EP1206325A4 (fr)
JP (1) JP2003506891A (fr)
KR (1) KR100764582B1 (fr)
AU (1) AU6640000A (fr)
WO (1) WO2001011662A2 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100730593B1 (ko) * 2005-09-07 2007-06-20 세크론 주식회사 이너비아 다층인쇄회로기판 제조 장치 및 그 방법
CN102369600B (zh) * 2009-04-02 2014-09-10 株式会社村田制作所 电路基板

Citations (4)

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Publication number Priority date Publication date Assignee Title
US3562009A (en) * 1967-02-14 1971-02-09 Western Electric Co Method of providing electrically conductive substrate through-holes
US5031308A (en) * 1988-12-29 1991-07-16 Japan Radio Co., Ltd. Method of manufacturing multilayered printed-wiring-board
US5614114A (en) * 1994-07-18 1997-03-25 Electro Scientific Industries, Inc. Laser system and method for plating vias
JPH1022628A (ja) * 1996-07-03 1998-01-23 Taiyo Yuden Co Ltd ビアホールへの導体充填方法

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Publication number Priority date Publication date Assignee Title
JPS6422097A (en) * 1987-07-17 1989-01-25 Hitachi Chemical Co Ltd Manufacture of metal base printed circuit board having through hole on both sides
JPH01312895A (ja) * 1988-06-09 1989-12-18 Fujitsu Ltd プリント基板の製造方法
US5239746A (en) * 1991-06-07 1993-08-31 Norton Company Method of fabricating electronic circuits
US5584956A (en) * 1992-12-09 1996-12-17 University Of Iowa Research Foundation Method for producing conductive or insulating feedthroughs in a substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3562009A (en) * 1967-02-14 1971-02-09 Western Electric Co Method of providing electrically conductive substrate through-holes
US5031308A (en) * 1988-12-29 1991-07-16 Japan Radio Co., Ltd. Method of manufacturing multilayered printed-wiring-board
US5614114A (en) * 1994-07-18 1997-03-25 Electro Scientific Industries, Inc. Laser system and method for plating vias
JPH1022628A (ja) * 1996-07-03 1998-01-23 Taiyo Yuden Co Ltd ビアホールへの導体充填方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 05 30 April 1998 (1998-04-30) *
See also references of WO0111662A3 *

Also Published As

Publication number Publication date
KR100764582B1 (ko) 2007-10-09
WO2001011662A3 (fr) 2001-05-17
AU6640000A (en) 2001-03-05
WO2001011662A2 (fr) 2001-02-15
EP1206325A2 (fr) 2002-05-22
JP2003506891A (ja) 2003-02-18
KR20020021405A (ko) 2002-03-20

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