Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
  • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Definitions

• the invention relates to a frequency detection method for adjusting the clock signal frequency of a local oscillator to the data rate of a received binary data signal.
• the invention also relates to a frequency detector circuit for carrying out the method.
• a PLL (Phase Located Loop) phase-locked loop is frequently used for clock signal synchronization, in which the clock signal phase of a local oscillator is compared with a phase detector with the phase position of the received data signal and readjusted. Since a phase locked loop does not engage if the frequency of the local oscillator deviates too much from the data rate, a frequency must also be carried out by means of which the oscillator frequency is pre-tuned.
• the invention has for its object to provide a method and a circuit with which a frequency comparison between the data rate of a received data signal and the clock signal frequency of a local oscillator can be carried out safely and without interference even with strong jitter of the received data signal, without accepting the disadvantage must have to supply a quartz-accurate reference signal or have to generate it with a quartz.
• the useful information is usually scrambled in transmission systems since this improves the spectral properties of the data signal for transmission.
• the probability that the state of a data signal bit changes at a possible point in time is 1/2. This property is used and exploited in the method according to the invention in order to obtain frequency information.
• a reset signal is advantageously derived from the final state of the subtractor, which resets the counters operating in parallel and avoids overflow in the subtractor.
• An advantageous further development of the invention consists in that after the frequency adjustment of the clock signal of the local oscillator has been carried out, the clock signal phase of the local oscillator is compared with the phase position of the received data signal by a PLL (phase locked loop) phase locked loop provided with a phase detector and a loop low-pass filter becomes.
• the analog output signal is fed into the PLL phase-locked loop to the loop low-pass filter during frequency adjustment via an adder, whereby the clock signal frequency of the local oscillator is changed until it has adjusted to the data rate of the received data signal.
• a lock-in signal is then advantageously derived, which is fed to the counters operating in parallel as a reset signal, so that the frequency control process is ended.
• the PLL phase locked loop then begins its phase control work.
• An advantageous further development of the method according to the invention consists in that, after a fixed number of clock signal pulses, a reset pulse is output by a counter called a plesiochronic counter, which resets the counters operating in parallel, so that the frequency control process is switched off.
• a frequency detector circuit which solves the task is characterized in that in order to divide the clock signal of the local oscillator in a clock signal path, first a 1: frequency divider, then a pre-counter and finally a ring counter, i.e. a counter, which starts counting again from the beginning (zero) after reaching its final value, is provided that in order to divide down the received binary data signal in a data signal path, a pre-counter that is the same as the pre-counter in the clock signal path and then one that is present in the clock signal path Ring counters of the same ring counter are provided, that the outputs of the two ring counters are each connected to one of the two inputs of the subtractor, that the differential output of the subtractor is connected to a digital / analog converter, which converts the difference into an analog value, and that on Output of the digital / analog converter, the analog output signal for regulating the clock signal frequency of the local oscillator is present.
• a 1: 2 frequency divider is expediently switched on in the clock signal path as well as in the data signal path between the pre-counter and the ring counter.
• the subtractor is advantageously designed in such a way that it also forms the difference between the counting values present at its two inputs beyond the overflow limits of the ring counter.
• the subtractor has yet another output at which a reset signal is present when the subtractor reaches a fixed positive or negative end position.
• the reset signal is sent to the two ring counters and to the two 1: 2 frequency dividers at their reset inputs.
• the reset signal can also be given to the two pre-counters at their reset inputs.
• the reset signals mentioned and possibly a "lock" signal which is emitted by a phase-locked loop when it snaps into place after a completed frequency adjustment of the clock signal frequency of the local oscillator, are additionally via an OR before being fed to the reset inputs of the counters and dividers. Gate led.
• a clock signal of a local oscillator which is introduced into a clock signal path 1, is first divided in a 1: 4 frequency divider 2 by the division factor "4", so that the frequency that occurs afterwards with the average frequency of a received binary data signal Edge change density 1/2 corresponds, which is introduced into a data signal path 3.
• a precount 4 or 5 is provided in data signal path 3 and in clock signal path 1, respectively.
• the two pre-counters 4 and 5 have the purpose of averaging longer identical or 0-1 sequences with short-term edge change densities 0 and 1, respectively.
• the output signals of the pre-counters 4 and 5 are in one
• a subtractor 10 is then provided, to which the output count signals of the two ring counters 8 and 9 of the clock signal path 1 and of the data signal path 3 are supplied at its two inputs A and B.
• the subtractor 10 works tet as in the book by U. Tietze; Ch. Schenk: “Semiconductor circuit technology", seventh, revised edition, Springer-Verlag, Berlin, 1985, p. 247.
• the subtractor 10 forms the difference between the ring counter readings supplied at the inputs A and B, even beyond the overflow limits, for example, in the case of a 4-bit subtractor 10, both 4-1 and 2-15 give the difference 3.
• On the output D of the subtractor 10 connected digital / analog converter 11 converts the counter difference into an analog voltage, the most significant bit serving as the sign bit for the two's complement.
• the reset signal is sent via an OR gate 12 with the reset signal of a plesiochronic counter 13, which is so-called because it resets the frequency detector in the initial state with an almost synchronous data and clock signal, and a possibly usable "lock" signal from a PLL - Phase control loop linked and given to the two 1: 2 divisors 6 and 7 and the two ring counters 8 and 9.
• the reset inputs are each designated R in the FIGURE.
• the reset signal can additionally be given to the pre-counters 4 and 5.
• the analog output voltage is passed to the loop low-pass filter 15 of the PLL phase-locked loop, which has a phase detector 16 for phase tracking and synchronization of the clock signal of the local oscillator.
• the pre-counter 4 located in the data signal path 3 will supply pulses with a higher frequency than the pre-counter 5 arranged in the clock signal path 1.
• the ring counter 8 will therefore count faster than the ring counter 9 via the 1: 2 divider 6, so that a value corresponding to the difference frequency is output from the subtractor 10 at the output D.
• the digital / analog converter 11 From this, the digital / analog converter 11 generates a positive analog voltage, which is passed via the adder 14 to the loop low-pass filter 15. This increases the clock frequency of the local oscillator until it has adjusted to the data signal rate.
• the signal of the phase detector 16 in the PLL phase-locked loop plays no role here, since it supplies the mean value 0 when the PLL phase-locked loop is not locked.
• the so-called plesiochron counter 13 can be dispensed with.
• a possible circuit for a "lock" indicator is a window comparator which emits a signal if the voltage of the phase detector 16 does not exceed certain limits for a sufficiently long time. If no latching signal is available, the plesochronous counter 13 takes over the task of preventing any interfering actions of the frequency detector when the PLL phase-locked loop has already been latched.
• the output signal of the pre-counter 4 is more or less irregular due to statistically distributed bit change clusters or identical sequences. Without regular resetting of the ring counters 8 and 9, their counter readings would gradually "diverge" and generate interfering frequency detector signals.
• a reset pulse is output via the plesiochron counter 13, which resets the ring counters 8 and 9.
• the output pulses of the pre-counters 4 and 5 can occur with a random shift from one another.
• the 1: 2 frequency dividers 6 and 7 are inserted, which are reset via the plesiochron counter 13 or via the "lock" signal or via the signal from the output E of the subtractor 10 become.
• the pre-counters 4 and 5 In order to make the circuit tolerant of g consecutive identical bits, the pre-counter must count up to g / 4.
• a reset pulse is to be generated via this counter 13 before the ring counters 8 and 9 have a difference of 1 if there is a frequency difference ⁇ f at the input.
• the beat frequency between the ring counter inputs is ⁇ f / 8VZ, where VZ are the pre-counting steps of the pre-counters 4 and 5 and the PZ specified below are the steps of the plesiochronous counter 13.
• ring counters 8 and 9 With large ring counters 8 and 9, a linearly operating frequency control loop can be set up; the manipulated variable becomes proportional to the difference frequency. This allows an optimal frequency response to be set. A simple 3-bit or 4-bit counter is sufficient for lower demands on the frequency-catching behavior. A 2-bit counter is not possible due to the reset output E.
• the ring gain must not be selected too large.
• the output signal of the digital / analog converter 11 must therefore not be too large.
• An analytical stability calculation is omitted here.
• the described frequency adjustment circuit according to the invention is used in particular in receiver circuits at the end of transmission links in a telecommunications and data transmission network.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Manipulation Of Pulses (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

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• 1998
  • 1998-09-25 DE DE19844126A patent/DE19844126C1/de not_active Expired - Fee Related
• 1999
  • 1999-09-01 JP JP2000573001A patent/JP3697158B2/ja not_active Expired - Fee Related
  • 1999-09-01 WO PCT/DE1999/002766 patent/WO2000019613A1/de not_active Application Discontinuation
  • 1999-09-01 EP EP99953679A patent/EP1116329A1/de not_active Ceased
• 2001
  • 2001-03-26 US US09/817,841 patent/US6362693B2/en not_active Expired - Lifetime

Non-Patent Citations (1)

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