Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K3/03—Astable circuits
  • H03K3/0315—Ring oscillators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
  • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
  • H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator

Definitions

• CMOS output amplifier independent of the temperature, supply voltage and manufacturing quality of its transistors.
• the present invention relates to output amplifiers of integrated circuits, and more particularly an output amplifier in CMOS technology, the operating speed of which may vary as a function of the environmental parameters of its transistors (temperature, supply voltage and quality Manufacturing).
• An output amplifier is used to transmit electrical signals to the outside of a circuit. Generally, signals are supplied to electrical conductors (pins, tracks) similar to inductive and capacitive loads.
• the function of the output amplifier is mainly to adapt the signal sent to the outside of the circuit to the power line receiving the signal.
• FIG. 1 schematically represents an output amplifier 10 driving a generally capacitive load 12.
• the amplifier 10 comprises a MOS switching transistor 14 with P channel connected between a supply voltage terminal Vdd and an output terminal O, and controlled by the output of an inverter 16.
• a N-channel MOS switching transistor 18 is connected between ground and the output terminal O, and is controlled by the output of an inverter 20.
• the inputs of the inverters 16 and 20 are connected together to an input terminal I.
• the output amplifier must produce a signal of sufficient amplitude to be able to be interpreted as a logic signal.
• the amplifier must charge and discharge capacity 12. The slope of the transition depends on the current which the amplifier can supply and on the value of capacity 12. If the current is insufficient and the operating frequency too high , the transition slope is too small for the required amplitude to be reached within a period.
• the intrinsic conductivity of the transistors therefore the current that the transistors can supply, changes as a function of the temperature of the circuit, the value of the supply voltage and the manufacturing quality of the transistors, the latter depending on the progress of the stages of the manufacture of the integrated circuit.
• an output amplifier we generally want to ensure that it operates at a predetermined frequency in a given range of temperatures and in a given range of voltage regardless of the quality of manufacture of the transistors. This leads to designing the transistors so that they have the required conductivity under the most unfavorable conditions (high temperature, low supply voltage, poor quality transistors). However, the real environment parameters of the transistors are never the most unfavorable. As a result, the output amplifiers are capable of supplying higher currents than required, so much so that they may produce too much noise at switching in some applications.
• An object of the present invention is to provide a device making it possible to compensate for the variations in the characteristics of an output amplifier caused by a variation in its environment parameters.
• the present invention provides a circuit, the operating speed of which varies as a function of the temperature, the supply voltage and the intrinsic quality of the transistors of the circuit, associated with a compensation circuit comprising a constant current source. providing a substantially constant current independent of the temperature, the supply voltage and the intrinsic quality of the circuit transistors, a variable current source providing a current which increases with the inverse of the temperature, the supply voltage and the intrinsic quality of the circuit transistors, and means for decreasing the operating speed of the circuit when the difference in currents produced by the first and second sources increases.
• said means are provided for decreasing the speed of variation of control signals of transistors of the circuit when said difference in currents increases.
• the circuit includes transistors
• Switching MOS connected in parallel, and said means are provided to make a decreasing number of said transistors conductive at the same time when said current difference increases.
• the circuit comprises inverters connected in a ring consisting of an oscillator, and said means are provided for increasing the number of inverters connected in the ring when said difference in currents increases.
• the circuit comprises a first MOS transistor of a first type of conductivity connected between a first potential supply and an output terminal, and an inverter whose output terminal is connected to the gate of the transistor, the means for decreasing the speed comprising an adjustable current source connected between a second supply potential and a terminal supply of the inverter, a second supply terminal of the inverter being connected to the first supply potential.
• the adjustable current source is a second MOS transistor of a second type of conductivity, controlled by a voltage varying in the opposite direction to said current difference.
• said current difference is a digital signal carried over several control lines, a decreasing number of which is activated for discrete increasing values of the difference
• the adjustable current source comprises a group of MOS transistors. of the second type of condutivity connected in parallel, each of which is controlled by one of the control lines.
• the variable current source comprises a current mirror reproducing a current which passes through a second MOS transistor of the first type of conductivity connected to the first supply potential and whose gate is connected to the second potential. power supply, and each control line is connected to an output of a current mirror reproducing a constant current and to an output of a current mirror connected to reproduce the current of the variable current source according to a predetermined ratio, different for each command line.
• the gate of each switching transistor is connected to an output of a current mirror reproducing a constant current and to an output of a current mirror connected to reproduce the current of the current source. variable according to a predetermined ratio, different for each command line.
• said means produce a digital control signal carried over several control lines, only one line being activated at a time, the rank of the activated line increasing with said difference, the control lines being connected by so that each line activates a loop comprising an increasing number of inverters with the rank of the line.
• FIG. 1 represents a conventional output amplifier
• FIG. 2 schematically represents an embodiment of an output amplifier provided with means for reducing its operating speed according to the present invention
• FIG. 3 represents a block diagram of a compensation device for reducing the operating speed of a circuit according to the present invention
• FIG. 4 represents a source producing a current which decreases with temperature, which increases with supply voltage, and which increases with the intrinsic quality of the transistors which compose it
• FIG. 5 represents a circuit producing a digital signal of difference between a constant current and a variable current
• FIG. 6 represents a group of transistors achieving a conductivity chosen by a digital signal such as that produced by the circuit of FIG. 5
• Figure 7 shows an analog embodiment of the digital devices of Figures 5 and 6
• FIG. 8 represents an alternative embodiment of an output amplifier according to the present invention
• FIG. 9 represents an application of a compensation device according to the present invention, to a ring oscillator.
• the present invention consists in compensating for the increase in the intrinsic conductivity of the transistors using a current which increases with this intrinsic conductivity.
• FIG. 2 represents an output amplifier 10 similar to that described in relation to FIG. 1.
• the inverter 16 controlling the transistor 14 is, according to the invention, supplied between the supply voltage terminal Vdd and a device 22 of current limitation.
• the inverter 20 is according to the invention supplied between a device 24 for limiting the current and the earth.
• the switching speed at 1 of the output amplifier 10 depends on the speed with which the inverter 16 discharges the gate of the transistor 14.
• the current limiting device 22 makes it possible to act on the current which flows through the inverter 16 when the latter discharges the gate of the transistor 14.
• the device 22 is designed to provide a current which decreases when the P channel MOS transistors of the circuit see their intrinsic conductivity increase. This compensates for the increase in the intrinsic conductivity of transistor 14 by a decrease in the speed at which it is controlled.
• the current limiting device 24 makes it possible to reduce the switching speed to 0 of the amplifier 10 by acting on the control of the transistor 18.
• the device 24 is designed to be crossed by a current whose value decreases when the conductivity of the N-channel MOS transistors increases.
• FIG. 3 represents a block diagram of a compensation device 22 or 24 represented in FIG. 2. It comprises a constant current source 26, a variable current source 28, and a subtractor 30 providing the difference Idif between the current Iref produced by the source 26 and that Imes produced by the source 28.
• the subtractor 30 controls a device 32 establishes an adjustable current, proportional to the signal Idif.
• the current source 26 provides a substantially constant current Iref independent of the environment parameters (EP) of the circuit, that is to say the temperature, the supply voltage, and the quality of the transistors of the circuit. .
• a current source can for example be a band gap generator.
• the variable current source 28 provides a measurement current Imes which increases when the conductivity of the MOS transistors increases as a result of variations in the environment parameters of the circuit. It is noted that when the environment parameters vary so that the intrinsic conductivity of the MOS transistors increases, that is to say that the variable current Imes increases, the current Idif decreases by causing a reduction in the current which crosses the device 32 and consequently a slowing down of the control of the corresponding transistor 14 or 18 of the amplifier.
• FIG. 4 represents an example of the variable current source 28 of FIG. 3.
• a P-channel measuring MOS transistor 34 is connected between the supply terminal Vdd and the input of a current mirror 36. The gate of transistor 34 is connected to ground.
• the transistor 34 behaves like a voltage source
• the output of the current mirror 36 produces the current Imes from the current source 28.
• the current Imes is proportional to the current passing through the measurement transistor 34.
• the circuit of FIG. 4 provides a measurement current Imes adapted to compensate for the variations in intrinsic conductivity of a P-channel MOS transistor, therefore of the transistor 14 of the output amplifier, since this current Imes depends on the conductivity of a MOS transistor 34 with P channel.
• a circuit symmetrical to that of FIG. 4 is used, that is to say one whose transistors are of the inverted conductivity type and whose supply terminals are inverted.
• FIG. 5 represents a digital embodiment of the current subtractor 30 of FIG. 3.
• This subtractor 30 produces a digital difference signal Idif on several control lines, here 6, Idif 1 to Idif ⁇ .
• Each Idif control line is connected to the output of a respective inverter INV whose input is connected to the connection node between a transistor T1 and a respective transistor T2.
• the transistors Tl are output transistors of a current mirror Ml whose input transistor Tle receives the constant current Iref produced by the source 26 (FIG. 3).
• the transistors Tl are all of the same dimensions so as to copy the current Iref with the same ratio.
• the transistors T2 are output transistors of a current mirror M2, the input transistor T2e of which receives the variable current Imes produced by the source 28 (FIG. 3).
• the transistors T2 of different dimensions so as to copy the current Imes with different ratios.
• connection node of the two transistors When a transistor T2 is more conductive than the transistor T1 which is associated with it, the connection node of the two transistors is brought to a high potential, and the corresponding command line Idif is deactivated. Similarly, when a transistor T2 is less conductive than the transistor Tl which is associated with it, the connection node of the two transistors is brought to a low potential, and the corresponding command line Idif is activated.
• the dimensions of the transistors T2 are chosen so that the number of transistors T2 more conductive than the associated transistors Tl increases with the current Imes and that when the current Imes corresponds to the most unfavorable conditions, no transistor T2 conducts more than the associated transistor Tl .
• FIG. 6 represents an example of an adjustable current device 32 which can be controlled by the digital signal Idif supplied by the circuit of FIG. 5.
• the device 32 comprises a group of N-channel T3 MOS transistors connected in parallel between a terminal IN input and an OUT output terminal.
• the gate of a first T3 0 of these transistors is connected to the supply terminal and the gates of the other transistors are each connected to one of the control lines Idif 1 to Idif ⁇ .
• the lines Idif 1 to Idif ⁇ are inactivated one after the other and the number of transistors in conduction in the device 32 decreases until only the first transistor T3 0 is in conduction and the device 32 conducts a minimum current.
• FIG. 7 represents an analog embodiment of a current subtractor 30 as described in connection with FIG. 3.
• a P-channel MOS transistor 26 connected between the supply terminal Vdd and a subtraction node S is controlled by a reference voltage Vref substantially constant as a function of the environmental parameters and establishes the reference current Iref.
• An N-channel MOS transistor 38 establishing a measurement current Imes is connected between the subtraction node S and the ground. The transistor 38 is for example the output mirror of the current mirror 36 described in relation to FIG. 4.
• FIG. 3 is here constituted by an N-channel MOS transistor connected in current mirror with the transistor 40.
• This transistor 32 thus establishes a current which decreases when the measured current Imes increases.
• the circuits of FIGS. 6 and 7 make it possible to adjust the current flowing through the inverter 16 to discharge the gate of the P-channel MOS transistor 14 from the amplifier.
• the circuits symmetrical to those of FIGS. 6 and 7 are used, that is to say of which the transistors are of the conductivity reversed and whose supply terminals are interchanged.
• FIG. 8 represents an output amplifier 42 according to a variant of the present invention.
• the output amplifier 42 comprises a group 44 of P-channel MOS switching transistors, TRIO to TR16 connected in parallel between the supply terminal Vdd and the output terminal 0 and a group 48 of N-channel MOS switching transistors , TR20 to TR26, connected in parallel between ground and output terminal 0.
• the gate of the first TRIO transistor of group 44 receives an input signal I via an inverter IV 1.
• the gate of each transistor TRI 1 to TRI 6 is connected to be activated when the input signal I and an associated control signal Idif 1 to Idif ⁇ are activated.
• the Idif control signals are for example produced by a current subtractor such as that of FIG. 5.
• the transistors of group 48 are similarly controlled by a digital difference signal evolving as a function of the intrinsic conductivity of a MOS transistor at channel N.
• the dimensions of the group 44 switching transistors are chosen so that the decrease in group conductivity due to the inactivation of one of its transistors compensates for the increase in intrinsic conductivity of the transistors.
• group 48 is similar to that of group 44. It makes it possible to limit the speed at which the amplifier 42 can discharge a capacitance connected to its output 0 when the environment parameters of the transistors of the circuit become favorable.
• the present invention can also be applied to circuits other than output amplifiers.
• Figure 9 shows an application of the present invention to a ring oscillator.
• the oscillator includes an odd number of inverters II to 17 connected in series.
• the output of the first inverter II is connected to the input of the first inverter II by means of a switch Bl controlled by a control signal Cl.
• the outputs of the inverters 13, 15, and 17 are connected to the input from the inverter II via respective switches B2 to B4 controlled by the control signals C2 to C4.
• the control signals C1 to C4 are supplied by a control circuit 50 so that only one of the signals C1 to C4 is activated at a time, as a function of the value of the difference Idif between the constant current Iref and the variable current Imes.
• the signals C1 to C4 can easily be produced from control signals such as the signals Idifl to Idif4 of FIG. 5.
• the control circuit 50 is provided for, using the signals C and the switches B, to insert an increasing number of inverters in the oscillator loop when the Idif current difference increases.
• an increase in the intrinsic conductivity of the transistors which would cause an increase in the frequency of an oscillator with a fixed number of inverters, is compensated by an increase in the number of inverters in the loop of the oscillator of FIG. 9.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Amplifiers (AREA)
• Logic Circuits (AREA)
• Dram (AREA)

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• 1998
  • 1998-07-21 FR FR9809436A patent/FR2781621A1/fr active Pending
• 1999
  • 1999-07-19 EP EP99941464A patent/EP1040580A1/de not_active Withdrawn
  • 1999-07-19 US US09/509,007 patent/US6414516B1/en not_active Expired - Fee Related
  • 1999-07-19 JP JP2000561708A patent/JP2002521906A/ja active Pending
  • 1999-07-19 WO PCT/EP1999/005339 patent/WO2000005818A1/fr not_active Application Discontinuation
• 2002
  • 2002-05-17 US US10/150,832 patent/US6724217B2/en not_active Expired - Fee Related

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