EP0978048A1

EP0978048A1 - Bus coupler between a system bus and a local bus in a multiple processor data processing system

Info

Publication number: EP0978048A1
Application number: EP97926974A
Authority: EP
Inventors: Michael Belhazy
Original assignee: Wincor Nixdorf International GmbH
Current assignee: Fujitsu Technology Solutions GmbH
Priority date: 1996-06-13
Filing date: 1997-06-04
Publication date: 2000-02-09
Also published as: JP2000512407A; US6295477B1; WO1997048055A1; DE19623668C1

Abstract

A process and device are disclosed for implementing an intervention-supporting coherence protocol for buffer memories in multiple processor data processing equipment. A bus coupler (15a, 15c) reproduces the coherence protocol of a system bus (10) in a local bus (14a, 14c). When an intervention concerns a buffer line located in the write register (22), the bus coupler (15a, 15c) transfers the buffer line from the write register (22) to the intervention register (21) by means of the local bus (14a, 14c).

Description

BUS COUPLER BETWEEN A SYSTEM BUS AND A LOCAL BUS IN A MULTI-PROCESSOR DATA PROCESSING SYSTEM

Technical field

The method and the arrangement relate to the organization of multi-computer systems with a system bus common to several modules and bus systems local to the modules.

State of the art

To improve the system performance, multi-computer systems have buffer memories on each processor, usually referred to as a 'cache'. To simplify the programming, various methods, for example in the book "Computer Architecture - A Quantitative Approach" by J.L. Hennessy and D.A. Patterson, San Franzisco 1995, measures described and referred to as cache coherence ensure that, despite the data copies in the buffer memories, uniform, consistent access to the entire memory of the multicomputer system is achieved at all times.

In such multicomputer systems with a hierarchy of bus systems, which are described in more detail below, additional buffers (registers) are useful for individual cache lines, which, however, can in turn conflict with the cache contents. In particular, the case in which data in a write register, such as data from an intervention register, must be transferred to the system bus, requires the corresponding circuitry for both registers.

The object of the invention is to reduce the effort for the treatment of such conflicts. This object is achieved in that the data from the write register are not transmitted directly to the system bus, but rather directly to the system bus via the local bus and the intervention register. This reduces the effort in that the write register supplies the data to the intervention register in the same way via the local bus as the processors, so that no difference is visible from the perspective of the intervention register.

Brief description of the drawings

Show it

Fig. 1 shows a modular multiprocessor computing system with two bus couplers and

Fig. 2 intervention, write and read registers from one of the bus couplers.

Detailed description of an embodiment

1 shows a modular multi-computer system with a system bus 10, a plurality of processor modules 13a, 13c and one of several possible memory modules 11 and other modules on the system bus, for example an I / O module 12.

Each processor module 13a, 13c contains a bus system 14a, 14c which is local to the module and to which one or more processors 16a..d are connected via buffer memories 17a..d. This connection is shown in functional form as a series connection of buffer memory 17a..d and processor 16a..d, without this being intended to restrict the actual implementation. Is located between the local bus 14a, 14c and the system bus 10 Each module has a bus coupler 15a, 15c which implements the signal protocols and in particular carries out the protocols for maintaining cache coherence.

For this purpose, as indicated in FIG. 2, three intermediate registers, namely the intervention register 21, the write register 22 and the read register 23, are usually used. The read register 23 is used when e.g. the processor 16a requests a data word which is not in its cache 17a (nor in the neighboring cache 17b on the same local bus 14a). The corresponding cache line, which contains the data word, is then requested by the coupler 15a on the system bus 10 and, when it arrives, is first buffered in the reading register 23 in order to then be transferred to the requesting cache 17a by means of the internal bus 14a.

If a cache line in the cache 17a is displaced and must be written back to the main memory 11 via the system bus 10, this is first temporarily stored in the write register 22 and then transmitted via the system bus 10.

Apart from very simple coherence protocols, the possibility is provided that the only valid copy of a cache line is in one of the cache memories, for example 17a, and not in the main memory 11. If a processor, for example 16c in the module 13c, a date from a cache line in the module 13a, the module 13a takes over the data transfer on the system bus 10 instead of the main memory 11. This is referred to as 'intervention'. In this case, protocols are preferably used on the system bus in which other address or data phases can be inserted between the address phase and the associated data phase. In response to a necessary intervention, the cache line is therefore first transferred to the intervention register 21 by means of the internal bus 14a and thereupon transmitted to the receiver by means of the data phase on the system bus 10 belonging to the triggering address phase.

The registers 21, 22 and 23 are usually been necessary because of the internal bus 14 and the system are constructed differently ₁ 0th In particular, the internal bus 14a can certainly transmit a cache line of 64 bytes at the same time, because an internal bus of 512 lines on a circuit board designed using multilayer technology is technically controllable. For a system bus with plug-in modules, smaller data widths, for example 64 bits, are common. In particular, only a lower speed is usually possible on the system bus because this is limited not only by the poor electrical properties of the plugs, but also by the relatively long lines determined by the size of the rear wall. In order to be able to freely select the frequency on the internal bus for a given frequency on the rear wall, decoupling of the bus systems via registers is expedient. When the data is transferred from the registers to the system bus or vice versa, for example, a conversion from space to time division multiplexing or vice versa takes place. Here, a cache line is also referred to as a block and in particular the amount of data that can be transmitted in parallel on the system bus is referred to as a subblock.

In order to reduce the waiting time for a data request caused by a cache until the first required data word from a cache line arrives, a sub-block swap is used. In this case, the sub-block is not transmitted in the order of the ascending addresses of the data words, but starting with the data word requested in each case, which can also be in the middle of a block. Such address-swapped subblocks can be entered in the intervention register 21 and in the 23 appear, but not in the write register, whose transfer to the main memory is a storage operation, which can take place in any order as well as in canonical order.

The introduction of a local bus 14a, 14c creates additional cases of conflict in cache coherence. In particular, the case may occur that, by means of a displacement in the cache 17a, this or its processor 16a has issued a cache line via the internal bus 14a, 14c with the aim of entering this cache line into the main memory 11 ¬ write back. At the end of the transmission on the internal bus 14a, only the copy in the write buffer 22 is the only valid one in the system. (Otherwise, the coherence protocol would have determined no writing back to the main memory.) The coupler 15a thus tries to assign the system bus with a corresponding address cycle in order to use the system bus 10 to write the content of the write register into the Main memory 11 to transfer. Before this succeeds, however, another processor can request data from precisely this cache line, which must therefore be fulfilled from the write buffer 22. However, the coupling of the coupler is designed to fulfill such requests from the intervention register 21. Apart from the inefficient solution of terminating the request in the hope that the write operation could have taken place until it is repeated, the data from the write buffer must therefore be transferred to the system bus 10. At first glance, this seems to be possible without any problems, since the write buffer 22 has a data connection 24 to the system bus anyway.

In practice, however, a problem arises in that the data in the write register must now be transferred to the system bus with sub-block exchange, although this is not the case when writing would be necessary. The write register would therefore have to be expanded by a multiplexer, which can effect the desired sub-block exchange when it is transferred to the system bus.

The invention uses the observation that the intervention register 21 already has this device and, furthermore, is mostly not occupied. An additional data path 25 is therefore introduced from the write register to the internal bus 14a, and the content of the write register is transferred to the intervention register by means of the internal bus and from there to the system bus with the correct subblock exchange.

Although this solution appears to be unfavorable and complex at first glance, it has proven to be very easy to carry out and efficient. An intervention in which the data is in the write register instead of in a cache 17a..d remains unchanged in the entire control of the intervention register 21 and thus significantly reduces the complexity of the control compared to the previous solutions. It is only necessary to activate the additional data connection 25 instead of the related cache 17a..d in order to put the data on the internal bus. It should be noted that in the event of an intervention, a cache 17a..d places the data as a complete cache line on the internal bus anyway. This new data path 25 is less complex than a multiplexer, which places the data in a different order on the system bus, and is more than offset by the gain due to the lower control effort. Since the system bus generally requires more data cycles than the internal bus to transmit an entire cache line due to the lower bandwidth, the detour via the internal bus does not have a significant delay. Furthermore the write register has become free again by transferring it to the intervention register.

The main memory 11 is shown in the description as a logical unit. It can be realized by one or more memory modules connected to the system bus. Alternatively or additionally, memory can also be present on the processor modules 13a, 13c, which from the point of view of the other modules behaves like an independent memory 11.

An expansion can also take place in such a way that a plurality of intervention registers or a plurality of intervention registers are present and the control thereby permits an additional parallel work in that a further intervention register is filled via the internal bus, while the first still contains its data via the system bus transmits.

Claims

claims

1. Arrangement in multiprocessor data processing devices with a coherence protocol for buffers (cache, 17a..d) and the features: - a bus coupler (15a, 15c) connects a system bus (10) with at least one local bus (14a, 14c) , to the processors (16a..d) with buffer lines containing buffers (17a..d) are connected,

- The bus coupler (15a, 15c) comprises devices which map the coherence protocol from the system bus (10) to the local bus (14a, 14c) and which each have at least one intervention register (21) and at least one write register (22) for buffer lines contain, which are each connected to the local bus (16a..d) and the system bus (10) in writing, characterized in that

- The write register (22) is additionally connected to the local bus (14a, 14c) in such a way that the content of the write register (22) can be transferred to the intervention register (21) in the event of an intervention relating to the content of the write register.

2. Operating method for an interventions-comprehensive coherence protocol for buffer memories (cache, 17a..d) in multiprocessor data processing devices, with the features:

- A bus coupler (15a, 15c) forms the coherence protocol on a system bus (10) on a local bus

(14a, 14c) from which processors (16a..c) with buffer memories (17a..d) containing buffer lines are connected,

- The bus coupler (15a, 15c) contains an intervention register (21) into the buffer lines on request the bus coupler (15a, 15c) is transferred from a buffer memory (17a..c) via the local bus (14a, 14c) and then transferred to the system bus (10),

- The bus coupler (15a, 15c) contains a write register (22), into which a buffer memory (17a..c) writes a buffer line upon request of its processor (16a .. c) with the determination via the system bus 10 in the Main memory to be transferred, characterized in that

- In the event that a buffer line is requested via the system bus, which is located in the write register (22), this is transferred from the write register (22) via the local bus (14a, 14c) into the intervention register (21) .