EP0798690B1 - Circuit arrangement for picture-in-picture insertion - Google Patents

Description

The invention relates to a circuit arrangement for fading in at least one small picture into a main picture, in which the small picture is temporarily stored in a memory.

In such circuit arrangements, one or more images are each displayed in a window in a main image and displayed on a display device, such as a screen. The images to be overlaid are generally moving images, possibly also the underlying main image. For a comfortable operation of a playback device with such a circuit arrangement, a sufficient number of windows of different sizes should be able to be overlapped with one another. The operator should be able to easily change the screen image.

In the reference DOS-International: " PIP technology in multimedia applications: how does the picture get into the picture? ", 1995, pages 192, 194 - 197 Implementation possibilities for a window-based picture-in-picture display on personal computers are described. In the frame buffer technique, the image content for the image to be superimposed is inserted directly into the graphics memory, which essentially contains the overall image displayed on the screen in pixels, in the place of the window to be superimposed and in the image size to be superimposed. In the case of image manipulations, for example the deletion or reduction of a window or the change of a window to the foreground or background, the picture information of the main picture or of a window which has been hitherto exposed in the background is restored by recalculation of the exposed picture elements. This requires processing time and puts a strain on the computer's computing capacity. As an improvement in the cited reference Video accelerator listed in which the images to be hidden are buffered in a separate memory and the accelerator itself takes over the multiplexing of the fade-in process and the image scaling.

In addition, picture-in-picture processors for use in television sets are known, for example the integrated module SDA 9088 from Siemens (" ICs for Entertainment Electronics ", edition 5.91, pages 38 - 47 , in particular Table ₄ ), in which a small image can be displayed only in a predetermined size at a preset position. The insertion point is determined by the coordinates of the upper left corner of the small picture. A user performed change of the small picture according to the above options is not provided in this module.

The GB 2 186 470 A describes an image processing arrangement for displaying one or more images on a screen. This image processing arrangement divides the screen into a number of horizontal stripes, each strip being divided into a number of segments. Each of these segments represents part of a window to be displayed on the screen. For each horizontal band of the image descriptive information is stored for each of these segments, which contains, inter alia, an address pointer to a memory position in which the image content associated with the respective segment is contained.

The object of the invention is to provide a circuit arrangement for fading in at least one small picture in a main picture, in which a manipulation of the or small images to be displayed is as unlimited as possible and can be carried out quickly. In particular, the computational effort to provide the image data should be as low as possible.

According to the invention, this object is achieved by a circuit arrangement solved according to the features of claim 1.

In the case of the circuit arrangement according to the invention, a change in presentation parameters, such as a change from foreground representation to background representation, erasure, reduction or enlargement of an image, has only an influence on the data stored in the overview table. Such changes only change these table entries, the actual image data remain stored unchanged. A restoration of any uncovered image areas when deleting a small picture or a picture reduction is eliminated. As a result of the parameter changes, only the address generation changes for accessing the image data. The computational effort for the previously necessary recalculation of uncovered pixel data is eliminated. The response time of a player to a corresponding screen change of the user is much faster. The recalculation for an address of a memory access therefore does not need to be done as in the prior art for each pixel, but only if within a line through the summary table switching from the main image to a small picture or between small pictures takes place among each other. These operations occur at the same location of the lines within an image area comprising a number of consecutive lines, each of which can be assigned the same parameter setting within the summary table. The overview table can therefore be stored in principle within a relatively slow mass memory, wherein in the control device fast-acting registers are provided, in which then the respective current parameter setting of such an image area is loaded.

The summary table contains parameter values assigned to each of the image areas comprising a number of lines, which indicate the start and the end within these lines of the image area for the respective small image and a pointer to the image content stored in the mass memory for the small image. From this, the control device calculates the physical memory addresses for the small image data to be displayed in the memory. Concretely, the overview table means comprise a first table in which the image area is marked, for which the following data are to apply. This indicator for the image area are assigned further characteristics which indicate the small images to be superimposed in the respective lines of the image area, the order of which corresponds to the order of the small images to be displayed in the horizontal direction. These latter identifiers, which represent, for example, window numbers, refer on another table, are stored in the pointers that point to the memory addresses of the small image in the mass storage. As a result, a small image can be superimposed several times in the main image with little memory overhead for the summary table. The further table, from which reference is made to the memory addresses of the small image, expediently contains the pixel number of the beginning and the end of the respective small image to be superimposed in the image area and a reference between the complete data stored in the image memory and the data portion to be read only for the overlay. The latter parameter is, for example, the "virtual width" of the small image in the image memory, ie the width which would result if all data stored for the small image were read out. In addition, in the first or the second table, an indicator for the priority of the window can be given, which concerns a statement about the representation in the foreground or in the background, so that the small image overlaps other images or can be overlapped by other images.

By the circuit arrangement according to the invention, the windows can be manipulated on the screen in a simple manner, without the large amounts of data must be copied or recalculated. The shifting of a read window within a larger information area to be displayed (horizontal or vertical scrolling) can easily be carried out by changing the parameters in the second table. The same window content can be displayed multiple times on the screen without consuming twice the storage space by listing the respective image numbers twice within the first table. The addressing of the window contents is independent of the display position on the screen. In summary, moving, deleting, moving forward / backward, or resizing a window is easily accomplished by changes in the table (s) stored in the table (s) performed, but not by changing the pixel data.

• Figur 1 eine Schaltungsanordnung gemäß der Erfindung und
• Figur 2 (a) bis (c) verschieden Bildschirmdarstellungen.

The invention will be explained in more detail with reference to the figures shown in the drawing. Show it

• FIG. 1 a circuit arrangement according to the invention and
• FIGS. 2 (a) to (c) different screen presentations.

The circuit arrangement contains a mass memory 1, in which the data of two images to be superimposed are stored in memory areas 2 and 3, respectively. The images stored in the memory areas 2, 3 are generally moving images, ie are overwritten and refreshed with the refresh rate with new data. By means of a reading device 4, which provides the addresses for driving the memory 1, the image data are read out at an output 5 and are available at a connection 6 for controlling a screen. A fade-in device 7 ensures within each line that is switched between an image signal H for the main image to be displayed and read from the memory 5 corresponding portion of the small image.

A controller 8 provides for presetting the addresses for the read-out means 4. The controller 8 calculates the addresses in response to tables 9, 10, described in detail below, which contain the parameters directed to the window-based small-image display in the main picture. The parameters indicate the changes with respect to the small images to be displayed in the line direction, one parameter set being valid for a number of consecutive lines. During an image area comprising this number of lines, the current parameter set is copied to a working register 13 of the control device 8. The working register 13 can be accessed quickly; the tables 9, 10 can then readily physically to a dedicated location of the mass storage 1 are arranged, but are then available only relatively slowly. The controller 8 further includes a line counter 11 which is incremented with each line of the main picture and a pixel (pixel) counter 12 which is incremented within a line with each pixel. The counters 11, 12 are compared with the parameter set in the register 9 and generate therefrom the corresponding presetting for the read-out counter 4 of the memory 1. The line counter 11 serves the image areas, for each of which a parameter set stored in the tables 9, 10 applies, to determine the pixel counter 12 is used to determine at which horizontal position within a line, a parameter change, ie switching to a small picture, a switch back to the main picture or switching between small pictures, occurs.

In FIG. 2 (a) is an example of a realizable with the invention screen display shown. The screen 20 with the main image 21 contains three small images 22, 23, 24, with the image contents "x", "y" and "z", of which the small image 23 is shown in the foreground and the small image 23 overlaps in the overlap areas. The screen is subdivided into image areas a... G, each image area comprising a number of lines in which the same presentation parameters are present in the line direction (horizontally) with respect to the small images. For example, in picture area a, only the main picture but no small picture is displayed. In the image area b, a section of the small image 24 is shown in the main image. In section c, a part of the small picture 22 as well as another part of the small picture 24, in the area d only a further part of the small picture 22, etc. In the area e the window 23 overlaps the window 22. The first table in the memory area 9, in which the image contents x, y, z to be superimposed are assigned to the image areas a... g, with the reproduction order occurring in the horizontal direction being satisfied, as follows: Area number a - b z c x, y d x e x, y f y G -

In Table 9, for the symbols a... G, in each case practically the number of lines to which this data record applies is stored. For the symbols x, y, z a picture number is stored.

The horizontal positions at which the small image 24 begins and ends are denoted by z1 and z2 respectively, the corresponding positions for the small image 22 by x1 and x2, etc. The second table in the memory area 10 contains for the small images 22, 23, 24th these image boundaries and an identifier for foreground or background representation. From this, the control unit 8 determines the corresponding address control for the readout address counter 4, so that only the part needed between the limits x1, x2 for the small picture window 22 to be inserted is read from the entire small picture contents x3 stored in the memory 1 in the memory section 2. All stored image content is called a "virtual width". The same can also be provided (not shown) with regard to the vertical extent of the images. In the image area e, the specification of the parameter for the small image 23 for display in the foreground controls that in the overlapping area from the horizontal position y1 the image content x of the small image 22 is overwritten by the image content y of the small image 23. This overwriting is done only by appropriate control of the read address counter 4 by the controller 8. The second table for the memory area 10 has the following overall appearance: number beginning The End virtual width Foreground / Background x x1 x2 x3 0 y y1 y2 y3 1 z z1 z2 z3 0

In the FIG. 2 (b) a slightly different screen is shown. Only the opposite of the are indicated FIG. 2 (a) changed window parameters, the remaining parameters remain the same. It is modified that the window 23 is shifted in the vertical direction with respect to the window 22, the latter being shown in the foreground, the former in the background. In addition, window 23 is reduced in horizontal direction. The changed parameters are denoted by primed reference numerals and replace the previous parameters in the first and second tables stored in the memory area 9 and 10. In addition, the foreground / background parameter for the image y is set to "0", for the image x is set to "1".

An alternative parameter distribution for characterizing the image representation is in Figure 2 (c) shown. Figure 2 (c) equals to FIG. 1 (a) with the difference that the parameter for foreground / background representation is omitted and instead a small image section contained within a region is regarded as a separate (partial) small image to which a separate image number is assigned. The first table stored in memory 9 has the following appearance: Area number a - b zI c xI, zII d xII e xIII, yI f yII G -

The second table stored in memory 10 contains the following data: number beginning The End virtual width zI z1 z2 z3 Zii z1 z2 z3 xI x1 x2 x3 xII x1 x2 x3 xIII x1 y1 x3 yI y1 y2 y3 yII y1 y2 y3

Claims (2)

1. A circuit configuration for fading at least one small image (22, 23, 24) into a main image (21) divided into lines, comprising
   a first memory (1), in which the image content (x, y, z) for the at least one small image is stored,
   a second memory (9, 10), in which an overview is stored, in which data are stored for an image region (a...g) containing a number of successive lines, from which data the image region (a...g), a position within the lines of the image region for the start (x1, y1 or z1) and the end (x2, y2 or z2) of the at least one small image (22, 23, 24) and a pointer to the image content (x, y or z) stored in the first memory (1) can be determined, and in which a characteristic for a foreground representation of the at least one small image (x, y, z) is contained, and
   a control unit (8) and a read-out counter (4), the control unit (8) determining an address control for the read-out counter from the overview such that the part required for the small image to be faded in is read out from the small image content stored in the first memory (1) only between the horizontal positions at which the small image begins and ends, and
   a fade-in device (7) which switches between an image signal (H) for the main image to be represented and the image content read out of the first memory (1),
   characterised in that the stored overview includes a first table (9), in which a characteristic for the image region (a...g) is contained, and also a characteristic for each small image (22, 23, 25) occurring in the horizontal direction inside the image area, the last characteristic referring to a second table (10) in which the horizontal positions at which the small image starts and ends and a caption for foreground and background representations are contained in allocated manner for each small image (22, 23, 24), and
   the control unit (8) determines the address control for the read-out counter to read out the part of the small image content, in an image region, required for the small image to be faded in from the information stored in the second table.
2. A circuit configuration according to Claim 1,
   characterised in that the control unit (8) comprises two counters (12, 11), one for pixels and one for lines of a main image (21), and a register for the intermediate storage (13) of the parameters that apply for an image region (a...g) of the main image (21)
   and in that the address counter (4) is set by the control unit (8) in dependence on comparison results between values of the counters (12, 11) and values stored in the register (13) such that it reads out the image content (x, y, z) for the small image (22, 23, 25) in connected manner.

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