Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04H—BROADCAST COMMUNICATION
  • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
  • H04H20/65—Arrangements characterised by transmission systems for broadcast
  • H04H20/67—Common-wave systems, i.e. using separate transmitters operating on substantially the same frequency

Definitions

• the invention relates to a method and a system for synchronizing a telecommunications network, ensuring the exchange of critical information in the time domain, by transmission of a digital multiplex signal between a point of emission of this signal associated with one or more reception or terminal points by a plurality of links, the transmission times of which vary according to the reception point and the architecture of this network, such as a single-frequency broadcasting network for example.
• the service area of each transmitter in the network is defined and limited by the area in which the useful level of the signal received from one of the transmitters is significantly higher than the level of the signal received from the other transmitter, playing the role of scrambler.
• This limit ratio called the protection ratio, depends on the emission system. It is most often of the order of 20 to 40 dB for analog mono frequency transmission systems.
• the characteristics of the transmissions carried out at the level of each transmitter are not strictly identical, as regards for example their central frequency and their modulation depth;
• the implementation of the abovementioned techniques makes it possible to obtain a significant reduction in the interference area, which allows better use of the radio resource and the use of a single transmission frequency for a program, the network used. then being a single frequency network.
• particular transmission and / or modulation techniques have been developed, in order to ensure the identity of the transmission characteristics, the digital transmission channels offering, for this purpose, a certain number of advantages. More specifically, it is indicated that for the abovementioned technical systems, as shown in FIG. 1, the identity of the delays in the interference zone is ensured by placing delay lines, digital or analog, in the detection device. transmission-emission. A delay line can thus be placed in series with the input of each transmitter, as shown in the above figure. The equalization of the delays must then be ensured with a precision of the order of a few tens of microseconds in the case of the DAB technique, respecti ⁇ vely of the order of the microsecond in the case of synchronous FM.
• the problem to be solved is that posed by the possible variations in transmission time on the different branches of the transmission network ensuring distribution to the transmitters.
• FIG. 1 it is thus understood that if the delay of one of the terrestrial circuits 1 or 2 varies independently of one another, the synchronization of the signals in the interference zone is no longer maintained, the interference phenomenon no longer being controlled.
• a variation of the delay between the emission studio A and the head TR of the distribution network has no influence whatsoever, insofar as this variation affects each of the transmitters identically.
• the routing mechanisms of these networks seek transmission paths without considering the corresponding transit time.
• the implementation of an emergency route can lead to a variation in length circuit length of 100 km or more, thus inducing delay variations of the order of 0.5 ms.
• These are insensitive in telephony on the aforementioned public network but render ineffective the delay equalizations of a dedicated monofrequency network;
• the object of the method and the system for synchronizing a telecommunications network according to the present invention is to remedy the aforementioned problem for any type of digital telecommunications network in which an exchange of critical information in the time domain is ensured, by transmission of a multiplex signal between a transmission point of this signal associated with one or more reception or terminal points by a plurality of links.
• Another object of the present invention is the implementation of a method and a system for synchronizing a telecommunications network in which, for each transmission point of the network, a global transmission time is imposed, this which makes it possible to synchronize the transmission at the aforementioned different points, with respect to a reference signal.
• the method and the system for synchronizing a telecommunications network ensuring the exchange of critical information in the time domain by transmission of a digital multiplex signal, between a transmission point of this signal, interconnected to one or more reception points or terminals by a plurality of links whose transmission times are variable depending on the reception point and the architecture of this network, are remarkable in that it consists in, respectively allows, to generate and transmit to the transmission point and to the terminals, via a transmission channel with stable propagation time, distinct from the network, a periodic reference signal, generate at a network reference point and insert into the digital multiplex a periodic series of time markers, these time markers being correlated to specific instants of the digital multi ⁇ plex signal and to the reference signal, then, compensate locally at each terminal for each relative delay caused by the telecommunications network on the digital multiplex and on the markets time seekers, with respect to the reference signal, to impose a predetermined overall transmission time, and synchronize all of the terminals from the reference signal.
• the method and the system for synchronizing a telecommunications network find application, in the field of telecommunications, in the implementation, maintenance and management of specialized telecommunications networks in which the transmission times are variable depending on the point reception and architecture of this network, in particular due to the routing operations of the transmitted messages, constituting the digital multiplex signal transmitted. They will be better understood on reading the description and on observing the drawings below in which, in addition to FIG. 1 relating to the prior art,
• FIG. 2a shows a block diagram of the different stages of implementation of the method, object of the present invention
• FIG. 2b shows a block diagram of a synchronization system of a telecommunications network in accordance with the object of the present invention
• FIGS. 3a and 3b represent timing diagrams of signals making it possible to illustrate a first respectively a second mode of implementation of the method, object of the present invention
• FIG. 4a represents the structure of a multiplex signal transmitted by a network subjected to the synchronization process in accordance with the object of the present invention
• FIG. 4b shows the structure of a transmitted multiplex signal, multiframe type
• FIG. 5a shows, on transmission, a detail of the system object of the present invention to generate a succession of synchro ⁇ nes markers of a reference signal
• FIG. 5b represents, on reception, a detail of the system for producing the system which is the subject of the present invention making it possible to measure, with respect to a reference signal, the transmission delay of the digital multiplex signal at the point of reception considered ;
• - Figure 5c shows, on reception, an advantageous embodiment of a delay compensation device of the digital multiplex signal
• - Figure 6a shows a device for transmitting an asynchronous marker in the digital multi ⁇ plex signal
• FIG. 6b shows a device for measuring the transmission delay of the digital multiplex signal using an asynchronous marker
• FIG. 7 shows a complete processing device on receipt.
• the digital signal consists of information representative of messages intended for at least one of the terminals, these terminals being intended to retransmit this message to ensure coverage of an area in which the telecommunications service is assured.
• the method which is the subject of the present invention consists in generating and transmitting, in a step 1000, to the aforementioned point of emission and terminals, by means of a transmission channel with stable propagation time, distinct from the network, a periodic reference signal.
• a periodic reference signal in order to ensure, by virtue of the periodic reference signal, a function analogous to that of a time base for the constituent elements of the telecommunications network and in particular for the terminals of the latter, the transmission channel with stable propagation time is a specialized, dedicated channel, not subject to the routing process usually used by telecommunication networks of the public type or of the Integrated Services Digital Network, ISDN type, previously. mentioned in the description.
• the transmission channel with stable propagation time making it possible to transmit to the transmission point and to the terminals the periodic reference signal which can advantageously be carried out by a satellite transmission channel, as will be described in more detail later in the description.
• the method, object of the present invention consists then, in a step 1001, to generate at a reference point of the network, and to insert into the digital multiplex, denoted MUX in FIG. 2a, a periodic series of time markers, marked M in step 1001 of the aforementioned figure.
• markers M are correlated to specific instants of the digital multiplex signal and to the reference signal.
• step 1001 of the method for synchronizing a telecommunications network which is the subject of the present invention, is then followed, as shown in FIG. 2, by a step 1002 consisting in compensating locally for each terminal, each relative transmission delay caused by the telecommunications network on the digital multiplex and on the time markers with respect to the reference signal.
• this compensation step 1002 makes it possible to impose a predetermined overall transmission time, which in turn makes it possible to synchronize all of the terminals from the reference signal.
• the synchronization of the terminals then makes it possible to carry out a transmission or broadcasting of the messages in order to ensure the coverage of the telecommunication service by the aforementioned network.
• This diffusion step is noted 1003 in FIG. 2.
• FIG. 2b the telecommunication network is shown, which is deemed to be constituted, for example, by a single frequency broadcasting network comprising a source A constituting the point of emission of the digital multiplex signal MUX, this source being interconnected with a plurality of '' single frequency transmitters, referenced B and C in the aforementioned Figure 2b, the number of single frequency transmitters being deliberately limited to two so as not to unnecessarily overload the drawing.
• the single frequency transmitters in this case constitute the network terminals, these being interconnected at source A via a network link, denoted R, comprising a head end, denoted TR.
• R a network link
• TR head end
• the single frequency transmitters constituting the terminals are provided with transmitting means making it possible to transmit messages under the conditions which will be explained below.
• both the source A and the single frequency transmitters B and C are provided with receiving means in order, of course, to receive the periodic reference signal transmitted, by the transmission channel with stable propagation time, both at the source.
• the transmission channel with stable propagation time is shown, produced in the form of a channel satellite S, which itself generates the periodic reference signal and therefore transmits the latter directly, on the one hand, to source A and, on the other hand, to each of the aforementioned single-frequency terminals or transmitters B and C.
• the method which is the subject of the present invention, it is understood that it consists in generating and inserting into the digital multiplex signal MUX the time markers M at a reference point of the telecommunications network comprised between the source A and the network head TR, the source A and the network head TR being of course interconnected by a single link allowing the routing of the multiplex signal MUX from the source A to the network head TR. It is further indicated that the creation and insertion into the digital multi-plex signal of the time markers M makes it possible, by synchronizing the emission of the single frequency transmitters B and C, to eliminate the risks of interference due to the relative delay of the between each single frequency transmitter, or terminals B, C above, under the conditions which will be described below.
• the reference signal is formed from a broadcast television program
• this television program can be broadcast by the satellite S and the reference signal can then be generated without difficulty from the synchronization information for the aforementioned broadcast television program.
• the specific instants of the digital multiplex signal MUX are then the instants of image synchronization of the television program.
• the time markers M are generated at the point of reference on reception by this reference point of the reference signal Re.
• the reference point of the network at the level of which the time markers M and the reference signal are synchronous, can for example so nonlimiting be constituted by source A.
• the step 1002 of local compensation at each terminal of each relative transmission delay generated by the telecommunication network on the digital multiplex MUX and the time markers consists, as shown in FIG. 3a, on the three lines of the corresponding timing diagram, to choose an overall transmission delay T at most equal to the period ⁇ of the reference signal, and to insert on the multiplex signal 11 digital MUX an additional delay to impose the aforementioned overall transmission delay T on the digital multiplex signal, this additional delay being equal to the overall delay T less the delay in reception of the time markers relative to the reference signal Re, corrected by the deviation of the propagation time of the reference signal to the reference point and to each terminal.
• FIG. 3a the three lines of the timing diagram, referenced A, B, C, of course schematize the operation of the synchronization system of a telecommunications network, object of the present invention, at source points A, respectively B and C of the terminals or single frequency transmitters.
• the up arrows represent the position in time of the reference signals Re received from the satellite S
• the down arrows represent the position of the markers M in the multiplex marked MUX * transmitted by the network R.
• the markers M always arrive after the corresponding reference signal Re since, on the ground, the length of the network between A and C is greater than the difference of the distances from satellite to source, SA, and satellite-terminal C, SC, and that the propagation speed on the terrestrial network cannot exceed that of the reference signal Re, equal in principle to the speed of light.
• the terminals or single frequency transmitters B and C broadcast the signal emitted by source A with a delay exactly equal to T less than or at most equal to the period t of the reference signal
• the method, object of the present invention in the synchronous embodiment, consists, in each transmission site, that is to say at each terminal B, C as shown in the corresponding chrono ⁇ grams of Figure 3a:
• this local synchronization pulse being obtained by delaying the reference signal Re received from satellite S by a duration corrected for the deviations due to satellite-transmitter path differences, these duration differences being denoted T b respectively T c for the single-frequency transmitters or corresponding terminals B and C; - a delay is also inserted on the multiplex marked MUX * transmitted, this delay being adjusted so that the markers M observed at the output of the multiplex marked MUX * coincide with the local synchronization pulse, symbolized by the star on the lines of chronograms B and C of FIG. 3a.
• These delays are noted D b , D c for the timing lines B and C relating to the single frequency transmitters or terminals B respectively C.
• the method of synchronization of a telecommunications network, object of the present invention can also be implemented in a so-called asynchronous manner, as will now be described in connection with FIGS. 2b and 3b.
• the time markers M are generated at the reference point, the source A for example, with a periodicity and a phase distinct from that of the reference signal Re.
• the method consists in measuring at the reference point, that is to say the point located between the source A and the network head TR, and more particularly in the described embodiment of in a nonlimiting manner in connection with FIGS. 2b and 3b, at the source A itself, the basic delay between the instant of reception of the last pulse of the reference signal Re, symbolized by the up arrows on line A of the timing diagram of FIG. 3b, and the time of insertion and transmission of the first time marker M following the last pulse of the reference signal Re, the first time marker M being symbolized by the first down arrow following the up arrow itself symbolizing the impulse of the reference signal Re.
• the basic delay is noted, for the sake of consistency of the notation in the case of the embodiment of FIG.
• the method which is the subject of the present invention then consists, as shown in FIG. 3b, for example for terminal B or single frequency transmitter B, of transmitting the information of the basic delay by the digital multiplex signal to each of the terminals. It will of course be understood that, for the sake of simplification of FIG. 3b, the corresponding timing diagram has been shown relative to the single terminal or single frequency transmitter B.
• the method which is the subject of the present invention also consists in measuring at each of the terminals, terminal B for FIG. 3b, the local delay between the moment of reception of the last signal pulse. of reference Re and the instant of reception of the first time marker, symbolized by the first arrow down, following the last pulse of the reference signal received.
• T b the aforementioned local delay
• the synchronization method of a telecommunications network, object of the present invention then consists in comparing at the level of each terminal or single frequency transmitter such as terminal B, for the same pulse of the reference signal Re, the local delay T b at the inma ⁇ tion of the basic delay T, received with the digital multiplex signal marked MUX * .
• the up arrows correspond to the instants of reception of the reference signals while the arrows directed downwards correspond to the instants of reception of the markers M.
• the difference T t it is indicated that it is relative to the corresponding value measured at the level of the 15 terminal B in the case of FIG. 3b, and that the difference T b -T, represents, modulo the period of the reference signal x, the transmission time on the telecommunications network increased by the difference between the propagation times of the reference signal Re by the satellite channel to the source A and to the terminal B, or single frequency transmitter B whose value is fixed and known. It is thus understood that it is possible to calculate the equalization delay necessary to then carry out a synchronized transmission delayed by a constant value T at most equal to the period x of the reference signal Re of each of the single frequency or terminal transmitters B, C or other.
• the digital multiplex signal MUX consists of information representative of messages intended for at least one of the terminals B or C as shown in FIG. 2b.
• the digital multiplex signal transmitted comprises, by nature, a repeating frame structure, as illustrated for example in FIG. 4a.
• a repetitive structure at 8 kHz defined by opinion G704 of the ITU (International Telecommunication Union).
• This type of multiplex provides signal transport at rates of up to 2 Mbits / s. It is used in particular for the transport of synchronous FM and DAB signals.
• the 8 kHz multiplex of form G704 comprises 256 bits distributed in 32 groups of eight, called time intervals and referenced IT 0 to IT 31 .
• the first time interval IT 0 is used to locate the start of the 32 groups according to conventional techniques.
• the IT time slot 16 is reserved for signaling functions and the other 30 time slots are used for the transport of 30 telecommunication channels at 64 kbit / s in a telephony application in general.
• the ITU G704 opinion allows ultrafine to be defined by grouping several G704 frames into one in order to constitute a longer frame, as shown in FIG. 4b.
• the ITU thus defines multiframes of duration of 2 ms, ie 16 G704 frames for signaling functions on the basis of the IT 16 time interval or for error rate control, according to the procedure called CRC4 using a bit of the first time interval IT 0 .
• the synchronization system of a telecommunications network comprises a module for generating and transmitting a periodic reference signal, this module being denoted 1, this generator and transmission module being a transmission module with stable propagation time, distinct from the network, as already mentioned in the description.
• this module is constituted by a satellite channel, denoted S, allowing the transmission of the reference signal Re in a stable manner under the usual propagation conditions of satellite telecommunication systems.
• the synchronization system of a telecommunications network comprises, at the reference point, the network reference point being, for the purposes of the description in conjunction with FIG.
• the module receiving the periodic reference signal Re carries the reference 2 and that the generator and insertion module in the digital multiplex signal MUX of a series of time markers thus delivering a marked digital multiplex signal, noted MUX * , bears the reference 3.
• the synchronization system of a telecommunications network comprises, at each of the terminals B or C, a receiver module 2 for the reference signal Re, this receiver module bearing the same reference as the receiver module installed at the reference point, in this case at the source A, because having the same structure and the same function regardless of the location of this receiver module 2 at source A or at each of terminals B or C.
• each of the terminals B or C comprises a module 4 for compensating for the relative delay generated by the telecommunications network on the digital multiplex, more precisely on the digital multiplex.
• marked MUX * and therefore on the time markers introduced in the latter, to impose a predetermined overall transmission time, as has been described previously in the description relating to the method of synchronization of a telecommunications network in accordance with object of the present invention, which of course makes it possible to synchronize all of the terminals B, C from the reference signal Re.
• this can be implemented either by the introduction of synchronous markers of the reference signal Re at the reception level of this reference signal to the reference point of the network R, that is to say in the particular case of FIG. 2b, without limitation, at 18 level of source A at the level of which the digital multiplex MUX and more particularly the digital multiplex marked MUX * are generated, either according to an embodiment known as asynchronous in which the markers M are generated at the reference point, that is to say at the source A, with a periodicity and a phase distinct from those of the reference signal Re.
• the module 1 generator and transmission of the periodic reference signal consists of the aforementioned satellite channel
• the reference signal Re can advantageously be formed by the vertical synchronization signal Sy of a television signal.
• this signal can be available without difficulty, and without additional cost of implementation, from the very infrastructure of the satellite to generate, on a channel specific to the satellite link, a series of pulses at the frequency of the vertical synchronization signal Sy, this series of pulses, constituting the reference signal Re, being transmitted on the one hand, to the reference point, the source A of FIG. 2b, and, on the other hand, to each of the terminals B, C as previously mentioned.
• the operating mode consists in fact in aligning the transmission frame of the digital multiplex MUX with the pulses of the reference signal Re.
• This multiframe can be signaled and identified by 19 using known techniques, for example one bit per frame G704, the first bit of each time interval IT t .
• This bit can be set equal to the value 0 to mark the first frame of each multiframe and to 1 in all the other frames.
• Other processes can be used, a process which makes it possible to introduce coding which is more resistant to transmission errors but whose implementation remains in accordance with the principle mentioned above. Since the 40 ms block or multiframe marking bit must be sent in synchronism with the useful information of the digital multiplex signal, the bits of time intervals 0 and 16, the content of which can be modified during transmission, should however be avoided. by network equipment. In general, with regard to the receiver modules 2 of the periodic reference signal Re, it is indicated that these, whatever their location on the network, may include, as shown for example in a nonlimiting manner in FIG.
• an antenna of the parabolic antenna type 20 in order to ensure reception of the reference signal Re of the satellite channel, as well as a satellite tuner 21, connected to the antenna 20, and a circuit 22 for extracting the vertical synchronization signal Sy from the television signal, this circuit 22 being interconnected with the satellite tuner 21 and delivering at least one counting initialization signal, as will be described later in the description.
• All of the elements 20, 21 and 22 are elements of conventional type in the technique of receiving satellite signals and extracting a vertical synchronization signal from a television signal and, as such, will not be described in detail.
• the generator and insertion module 3s in the digital multiplex signal MUX of the series of markers comprises, without limitation, a phase-locked loop PLL at 2048 kHz, bearing the reference 30, receiving a rhythm signal from the television signal delivered by the circuit 22 for extracting the above-mentioned vertical synchronization signal, the phase-locked circuit 30 making it possible to deliver a clock reference signal at 2048 kHz constituting makes it a source sync signal.
• the module 3s for generating and inserting the series of markers furthermore comprises a multiframe counter, denoted 31, which receives the count initialization signal delivered by the circuit 22 for extracting vertical synchronization of the television signal described above.
• the multiframe counting counter 31 makes it possible to generate a multiframe marking signal of the data packets corresponding to a series of successive frames of the digital multiplex signal, that is to say the 40 ms multi strings previously mentioned and consisting of 320 G704 frames.
• a time multiplexer 32 is further provided, which receives on the one hand the digital multiplex signal MUX and, on the other hand, the counting initialization signal delivered by the vertical synchronization extraction circuit 22, as well as the circuit of multiframe marking, the time multiplexer circuit 32 making it possible to deliver a marked digital multiplex signal, denoted MUX * , satisfying the recommendations of the above-mentioned opinion G704.
• the operation of the generator and insertion module 3s of the series of markers as shown in FIG. 5a is as follows:
• the multiplexer circuit 32 constitutes G704 frames into which the structure of the 40 ms multiframe described above is inserted. The start times of the frames
• G704 and multiframe are defined at startup as coinciding with the reception of the reference pulse Re at the period of the vertical television synchronization signal, ie 40 ms.
• the initial phase relationship is preserved throughout operation by phase locking the reference signal at 2048 kHz on the basis of the time of the television signal. In the event of discontinuity in the rhythm of the television signal, an incorrect phase relationship is detected, which allows the multiplexer circuit 32 to be reinitialized.
• a more detailed description of the module 4 for compensating for the relative delay generated by the telecommunications network at level of each of the terminals B or C, will now be described, in the case of synchronous implementation, in connection with FIGS. 5b and 5c.
• the module 4 for compensating the delay is formed of two sub-modules, represented in FIG. 5b, respectively 5c, each sub-module bearing the reference 4 a / s respectively 4 b / s / a , these sub-modules constituting the module 4 cited above, the sub-indices s, respectively a, indicating the possibility of use, for the so-called synchronous implementation, respectively for the so-called asynchronous implementation.
• the module 4 for compensating the delay and in particular the sub-module 4a / s is interconnected with the module 2 for receiving the reference signal Re located at the terminal B or C or any other terminal.
• This reception module 2 naturally includes the same elements as the reception module previously described in connection with FIG. 5a.
• the 4a / s sub-module comprises, to ensure reception of the digital multiplex signal marked MUX * , a demultiplexer circuit G704 referenced 40, which receives the clock reference signal at 2048 kHz delivered by the locking loop phase 30 of the transmission module, and a multiframe extraction circuit 41, which makes it possible to discriminate the start of each marked multiframe, as previously described in the description.
• the multiframe extraction circuit 41 delivers a multiframe start signal.
• a counter 42 is provided, which is clocked by the clock reference signal at 2048 kHz, and controlled by the counting initialization signal delivered by the circuit 22 for extracting the vertical television synchronization signal .
• a locking circuit 43 is connected to the counting circuit 42 and a measurement validation circuit 44 is provided, connected to the locking circuit 43, the measurement validation circuit 44 itself being followed by a circuit 45 for calculating delay equalization.
• the operation of the 4 a / s sub-module is as follows: the multiframe start signal delivered by the multiframe extraction circuit 41 is reconstructed by observation of the successive content of the first bit of each time interval IT t . The characteristic instants of the start of these received ultitrams are compared to the instants of reception of the reference pulse at 40 ms, that is to say in fact to the pulses constituting the counting initialization signal delivered by the circuit 22 for extracting the vertical television synchronization signal.
• the start of the received multiframes is late on the reference pulses d 'a quantity equal to the transmission time.
• This delay is measured by means of the counter 42 receiving as clock signal the clock reference signal at 2048 kHz, the counter 42 being reset to zero when the reference pulses of the reference signal Re are received and read. during the start of each multiframe by the control of the multiframe start signal, the reading being carried out by the locking circuit 43.
• Delays between 0 and 40 ms can be measured in a unit equal to the bit period of the multiplexing system, i.e. 488 ⁇ s.
• the measurement validation circuit 44 eliminating incoherent measurements, makes it possible to activate the circuit 45 for calculating the equalization delay, the calculation being carried out in accordance with the indications given in relation to FIG. 3a in the case of implementation. synchronous to the process which is the subject of the present invention.
• the circuit 45 delivers a signal representative of the equalization delay to be introduced for the terminal considered. This signal is a digital signal coded on 16 bits for values from 0 to 32 ms, in steps of 488 nanoseconds for example.
• the module 4 for compensating the relative delay comprises, as shown in FIG. 5c, a sub-module 4b / s / a, which advantageously includes a counter 46 receiving the clock reference signal at 2048 kHz from the phase locked loop 30 transmitted by the network and a subtractor circuit 47, which is constituted by a digital subtractor circuit modulo 65536.
• a circuit 48 of RAM dual access memory type, with storage capacity at least equal to 65536 x 1 bit, receives on the one hand, a digital signal delivered by the counter 46 and, on the other hand, the digital signal delivered by the subtractor 47.
• the memory 48 also receives the digital multiplex signal marked MUX * or the digital multiplex signal MUX and makes it possible to deliver a delayed digital multiplex signal, denoted MUXR, under the conditions which will be described below.
• the equalization delay to be inserted calculated in accordance with the process described in connection with FIG. 3a, by subtracting the measured delay from the total desired delay corrected for transmission deviations from the reference pulse Re, is applied to the global multiplex, that is to say the digital multiplex signal marked MUX * received by the memory circuit 48, which makes it possible to insert a corresponding number of bits to the equalization delay to be introduced.
• the dual-access memory 48 makes it possible to write the successive bits at addresses defined by a write pointer incremented by 1 for each new bit and modulo calculated the size of the counter 46, ie 65,536 bits for a maximum delay of 32 ms.
• the reading and the transmission of the delayed digital multiplex signal MUXR is then carried out by reading from the memory 48 on which the delay bits have been introduced using a read pointer, which also increases by the same so that the read address is equal to the write address minus the number of delay bits to be entered, modulo the size of the counter 46.
• the difference between the paths of satellite S, transmission site, source A on the one hand, and satellite S, reception site, terminals B, C d ' on the other hand, is less than the distance between these two sites. Consequently, the transmission time by the telecommunications network is always greater than the difference in the transmission times of the reference signal and the reception of a multiframe associated with a given reference pulse always follows the reception of the corresponding pulse. dante.
• the transmission deviations of the reference pulse Re are likely to exceed the transmission times on the telecommunications network R, it may be envisaged to modify the processing process, for example by delaying the transmission of the multiframe with respect to the reception of the reference pulse Re.
• the synchronous embodiment previously described requires synchronization between the rhythm of the digital multiplex signal and the rhythm of the reference signal Re.
• the frequency of the latter must be rigorously ensured.
• a discontinuity appears in the operation of the multiplexer 32, which is re-initialized as indicated above, which, of course, induces an interruption of service until the equipment supplied by the multiplex d restore their own synchronization.
• the asynchronous embodiment of the synchronization system of a telecommunications network, object of the present invention makes it possible to eliminate the various abovementioned constraints of interdependence.
• the markers M the role of which consists in characterizing the relative phase of the transmitted multiplex and of the reference signal, are then constructed as follows:
• the module 3a homologous for the asynchronous embodiment of the module 3s of the synchronous embodiment of inserting the series of markers, can for example comprise a first counter 33 receiving the signal for counting initialization delivered by the circuit 22 for extracting the television synchronization signal Sy and, connected to this counter, a locking circuit 34, the counter 33 and the circuit lock 34 playing a role similar to the counter 42 and the locking circuit 43 as shown in Figure 5b.
• the module 3a more particularly comprises a first multiplexer 35 of the G704 type, this multiplexer receiving the original multiplex signal MUX and delivering a marked multiplex signal denoted MUX * .
• the first multiplexer 35 also controls a multiframe counter 36, which controls a second multiplexer 37 which delivers, for each G704 frame, a bit which the first multiplexer 35 inserts into an 8 kbit / s channel, consisting of the first bit of each IT time interval t .
• the second multiplexer 37 inserts at the start of each multiframe an arbitrary word of fixed signature, such as for example "01111110", intended to identify the start of the multiframe considered.
• the first multiplexer 35 receives the clock reference signal at 2048 kHz, which also controls the counter 33.
• the operation of the asynchronous insertion module 3a represented in FIG. 6a is then as follows:
• each 8 ms multiframe is formed by associating, via the multiplexer 37, 64 G704 frames created by means of the multiplexer 35
• the counter 33 can be a 17-bit binary counter used to obtain a counting capacity exceeding 40 ms;
• HDLC High Data Link Control
• the module 4 for compensating for the relative delay generated by the telecommunication network at each of the terminals takes, analogously to the synchronous embodiment, a module 4a / a, for the asynchronous mode, for measuring the delay between the reference signal and the corresponding marker and, of course, a module 4b / a allowing insertion on the original digital multiplex signal MUX of a fixed equalization delay for the terminal considered.
• the module 4b / a for inserting the equalization delay can be produced in the same way as that implemented for the synchronous mode as shown in FIG. 5c.
• the module 4a / a for measuring the delay between the reference signal Re and the corresponding marker comprises, as shown in FIG. 6b, a counter 42 receiving the counting initialization signal delivered by the circuit 22 for extracting the vertical synchronization signal from the television signal, as well as the clock signal from reference to 2048 kHz, and a latch circuit 43, which is interconnected to the previous counter 42.
• the counter 42 and the locking circuit 43 play a role similar to the counter 33 and to the locking circuit 34 shown in FIG. 6a.
• a demulti ⁇ plexer circuit G704 bearing the reference 40 which receives the clock reference signal 2048 kHz and the digital multiplex signal marked MUX * . It makes it possible to deliver a clock signal and the data of the 8 kbit channel constituted by the first bit of the time interval IT X of each frame.
• a multi-frame extraction circuit 41 is provided, which makes it possible to generate a multiframe start signal making it possible to control the locking circuit 43, as well as a signal containing the information of the transmission delay which had been inserted in the digital multiplex signal marked MUX * as mentioned previously. This information is transmitted to a circuit 41a for reading the transmission delay, which transmits the transmission delay value read to a subtractor circuit 49.
• the subtractor circuit 49 is followed by a validation circuit 44, itself followed a circuit 45 for calculating the equalization delay.
• a validation circuit 44 itself followed by a circuit 45 for calculating the equalization delay.
• the operation of the delay measurement module 4a / a shown in FIG. 6b is as follows:
• the multiframes are discriminated on the basis of the digital multiplex signal marked MUX * via the demultiplexer 40, of the multi-frame extraction circuit 41.
• the time intervals separating the reception of a reference pulse from the start of the next multiframe are measured via the counter 42 and the locking circuit 43 in the same way, moreover than in the case of the insertion module 3a of the markers M shown in FIG. 6a.
• the delay measurement information represented by the state of the counter 33 inserted in each multiframe at the aforementioned module 3a is then compared with the measurement made locally, this comparison being carried out at the subtractor 49.
• the difference represents the transmission time to be corrected for deviations due to differences in the routing time of the reference signal between transmission sites A and reception of the digital multiplex signal, terminals B, C, being assumed a satellite routing of the reference pulses Re guaranteeing a positive difference for the same marker,
• the value measured at each terminal that is to say at the counter 42 is less than the measurement transmitted: in this case, the two measurements do not refer to the same reference pulse. It is then possible, either to ignore this measurement, or to correct it for the period between markers if the latter is known with sufficient precision.
• the measurements carried out are validated by the validation circuit 44, which can be analogous to the circuit 44 represented in FIG. 5b, by ensuring the absence of transmission error or by checking the consistency between successive delay calculations.
• the circuit 45 for calculating the equalization delay makes it possible to perform a calculation by subtracting the measured transmission delay and corrected for the arrival deviations of the reference pulses Re from the fixed value representing the desired total delay.
• the calculated equalization delay value makes it possible to determine the number of periods of the bit rate whose multiplex must be delayed, this operation being carried out at the module 4b / s / a as shown in FIG. 5c.
• the clock reference signal is chosen at a higher frequency of 16384 kHz by means of a phase locked loop analogous to loop 30 shown in FIG. 5a.
• This phase locked loop is locked in phase on the rhythm of the multiplex at 2048 kHz. Consequently, the size of the counter 33 is then increased to 20 bits and the same is true for the lock circuit 34.
• each terminal B or C there is a delay compensation module 4 having an architecture similar to that shown in FIGS. 6b and 5c, that is to say composed of two sub-modules 4a / a and 4b / a.
• the elements used for the configuration of the aforementioned architecture of the sub-module 4a / a are similar to those represented in FIG. 6b and bear the same reference.
• the counter 42 and the locking circuit 43 are digital elements or components whose size is increased to 20 bits, and the equalization delay calculation circuit 45 delivers an equalization delay signal coded on 19 bits, the delay can take a value between 0 and 32 ms in steps of 61 nanoseconds.
• the subtractor 47 is a 19 bit subtractor controlled by a 19 bit locking circuit bearing the reference 461
• the random access memory 48 is addressed by the subtractor 47 by the intermediary of a chain comprising a filtering circuit d phase difference 471, an oscillator circuit 472 at 16384 kHz and a frequency divider by eight circuit 473, which also controls a second modulo counter 65536, 474, receiving the equalization delay signal delivered by the circuit calculation of equalization delay 45 and allowing read addressing of the RAM 48.
• the frequency divider circuit 473 delivers the clock reference signal at 2048 kHz.
• the delay measurements are carried out with a resolution of 60 ns, that is to say a clock period at 16384 kHz and the equalization delay to be introduced is calculated by the equalization delay calculation circuit 45.
• the random access memory 48 makes it possible to perform the equalization delay function and the drift correction function of this delay, the writing of the data received from the original multiplex MUX being carried out on a time base linked to the rhythm of the multiplex original received.
• the delay on the digital multiplex signal MUX or on the digital multiplex signal marked MUX * is obtained by means of the random access memory 48 formed by a dual-access memory, the write and read pointers being delivered by the modulo counters the size of the random access memory 65536 bits , that is to say by the counter 46 and the counter 474.
• the first pointer is incremented by the rhythm at 2048 kHz of the digital multiplex signal received MUX or MUX * while the second pointer, that is to say the counter 474 is controlled by a local clock at 2048 kHz formed by the local crystal oscillator 472, voltage-controlled, and by the divider circuit by eight 473.
• the difference between the write and read pointers of the RAM 48 is representative of the delay introduced, this delay being measured periodically for example by memorizing the value of the read pointer when the write pointer passes by the value 0.
• the state of the divider by eight is also memorized.
• This difference is compared with the nominal value of the equalization delay previously calculated by the equalization delay circuit 45. The result of the comparison is used to control the frequency control of the local oscillator circuit 472, this control being carried out by l 'intermediary of the phase difference filtering circuit 471.
• the read speed of the RAM 48 is adjusted in order to bring the difference between the desired equalization delay and the delay actually introduced to zero.
• a particularly efficient method and system for synchronizing a telecommunications network has thus been described, insofar as, by virtue of the use of a transmission channel with stable propagation time, such as a satellite channel.
• a transmission channel with stable propagation time such as a satellite channel.
• the stability of transmission delays is ensured, these transmission delays depending only on the position of the satellite on the geostationary-type orbit and the position latitude, longitude and altitude of the transmitters to be supplied. It can in particular be verified that the movements of a satellite correctly maintained at position in geostationary orbit have a comparable impact on the delay in transmission to each transmitter, which maintains the synchronous nature of the emissions.

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• Engineering & Computer Science (AREA)
• Signal Processing (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

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• 1994
  • 1994-10-17 FR FR9412349A patent/FR2725860A1/fr active Granted
• 1995
  • 1995-10-13 WO PCT/FR1995/001353 patent/WO1996012360A1/fr not_active Application Discontinuation
  • 1995-10-13 EP EP95935494A patent/EP0787388A1/de not_active Ceased
  • 1995-10-17 ZA ZA958763A patent/ZA958763B/xx unknown

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