EP0654791B1 - Non-voltaile memory device having means for supplying negative programming voltages - Google Patents
Non-voltaile memory device having means for supplying negative programming voltages Download PDFInfo
- Publication number
- EP0654791B1 EP0654791B1 EP93830464A EP93830464A EP0654791B1 EP 0654791 B1 EP0654791 B1 EP 0654791B1 EP 93830464 A EP93830464 A EP 93830464A EP 93830464 A EP93830464 A EP 93830464A EP 0654791 B1 EP0654791 B1 EP 0654791B1
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- Prior art keywords
- plate
- capacitor
- memory cells
- transistor
- voltage supply
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- 239000003990 capacitor Substances 0.000 claims description 17
- 238000007667 floating Methods 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000002179 total cell area Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
Definitions
- the present invention relates to a non-volatile memory device comprising a structure for supplying negative programming voltages to non-volatile memory cells in said non-volatile memory device.
- EEPROM and Flash EEPROM memory devices can be programmed in one or another of two logical states by respectively introducing electrons into or removing electrons from the memory cells' floating gates. This latter operation is termed “writing” in EEPROMs, while in Flash EEPROMs it is referred to as "erasure”.
- the removal of electrons from a cell's floating gate is accomplished by tunnelling electrons from the floating gate into an underlying N+ diffusion, which in the case of a Flash EEPROM device constitute the source region of the cell while in an EEPROM device can represent either the source or the drain region of the cell, through a thin oxide region called "tunnel oxide"; electron tunnelling takes place if the potential difference between the floating gate and said underlying diffusion is made negative and its absolute value exceeds a value depending on the cells' characteristics.
- a common technique provides for grounding the cell's control gate (which is capacitively coupled to the floating gate), while raising the underlying diffusion potential to a value generally higher than 10 V.
- band-to-band tunnelling causes significant leakage currents to appear, thereby making it impossible to program the memory device by just supplying it one single voltage supply, or to use the memory device in a battery-supplied environment.
- a circuit implementing this technique is described in the US Patent 5,077,691, and comprises three P-channel MOSFETs, two of which are connected in series between the output of a positive high voltage (Vpp) source and an N-channel MOSFET having a source connected to ground, while the third is connected between the common node of the previous two MOSFETs and the output of a negative high voltage (Vnn) source;
- the common node to which the three MOSFETs are connected represents a control gate line or word line which is connected to the control gates of the cells to be programmed;
- the Vpp and Vnn sources are constituted by charge pumps or voltage boosters internal to the memory device, and generally located at the periphery of the chip.
- the charge pump for generating Vpp is activated, and the MOSFET connected between Vpp and the control gate line is on; the remaining two MOSFETs are instead kept off, and the charge pump for generating Vnn is deactivated. It is thus possible to transfer the voltage Vpp to the control gate line.
- the charge pump generating Vnn is activated, the two serially-connected MOSFET are kept off, and the third MOSFET is on, so that Vnn can be transferred to the control gate line.
- the voltage effectively transferred to the control gate line is actually given by the voltage applied to the gate of the third MOSFET minus the MOSFET threshold voltage (which is negative since P-channel MOSFETs are used); the gate voltage of the third MOSFET is never equal to Vnn, since voltage drops always occur between the output of the Vnn charge pump and the gate of the third MOSFET, due to the long interconnection line and the presence of selection transistors: the gate voltage of the third MOSFET is therefore, in an absolute value sense, lower than Vnn.
- the MOSFET threshold voltage increases (in absolute value) and the voltage effectively transferred to the control gate line can be 2 or 3 V higher than the voltage applied to the gate of the MOSFET. This value could be not sufficiently negative to start tunnelling of electrons.
- a possible solution to the abovementioned problem provides for voltage boosting the gate of the third MOSFET, at the expense of an increase in both the complexity of the circuit and in the total memory chip area.
- US-A-5,077,691 discloses a Flash EEPROM device with a memory cell array, a +12V charge pump, a -2V charge pump, a -12V charge pump, and a plurality of gate switch circuits, one for each word line of the array, for selectively coupling the respective word line to either the +12V, or the -2V, or the -12V common voltage rails.
- US-A-4,797,899 discloses a monolithic integrated circuit including a positive voltage doubler, a voltage inverting portion for generating a negative voltage, and in RS-232-transmitter/receiver. The capacitors for the positive voltage doubler and the inverting circuit portion are not integrated in the chip, but are external.
- EP-A-0 456 623 discloses a Flash EEPROM memory having a unique negative charge pump, coupled to the word lines through respective MOSFETs, each MOSFET being controlled by a respective bootstrapping circuit.
- the object of the present invention is to provide a structure for supplying negative voltages to non-volatile memory cells in a non-volatile memory device which, without increasing significantly the total chip area, is not affected by the abovementioned problems.
- said elementary circuit occupies a limited area making it possible to accomplish a memory device in which each word line is closely connected, at its ends, to a respective elementary circuit (which works as a "local" negative voltage charge pump) so that the negative voltage required to program the memory cells connected to a selected word line is generated directly on such word line; in this case, it is only necessary to provide the memory device with a positive voltage charge pump.
- Figure 1 is a schematic diagram of a structure according to an embodiment of the invention.
- an elementary circuit 1 for generating a negative voltage starting from a positive high voltage supply Vpp is shown.
- the circuit 1 comprises a first MOSFET TX whose drain and source are respectively connected to a positive high voltage supply line Vpp and to a first node A, a second MOSFET TY with drain and source respectively connected to node A and to a reference voltage line GND, a third MOSFET TB whose drain and source are respectively connected to the reference voltage line GND and to a second node B representing a negative voltage output of the elementary circuit 1 and to which in this embodiment a control gate line CG (constituting a word line of the memory matrix) is also connected, and a capacitor C connected between node A and node B.
- CG consisttituting a word line of the memory matrix
- Non-volatile memory cells are connected to the control gate line CG by their control gates.
- a fourth MOSFET TA with source and drain respectively connected to Vpp and to node B is also shown, and is used in a per se know way to transfer to the control gate line CG the voltage Vpp when electrons are to be transferred to the floating gates of the memory cells connected to CG.
- TA and TB are P-channel MOSFETs, while in the example of Figure 1 TX and TY are high-voltage N-channel MOSFETs, but could as well be both P-channel MOSFETs, or one a P-channel and the other an N-channel MOSFET.
- the high voltage supply line Vpp can be connected to an external high-voltage supply, or to the output of a conventional charge pump not shown in the drawings, which starting from a supply voltage applied externally to the memory device raises it to a value sufficient to determine the transfer of electrons, either by tunnelling (EEPROMs) or by hot electrons injection (Flash EEPROMs) to the floating gates of the memory cells.
- Said charge pump is normally located at the periphery of the memory device chip.
- control gate line CG the control gate line CG
- TA and TB the higher the value of C compared to said parasitic capacitances, the better said negative potential approximates -Vpp. Since the control gate capacitance of a memory cell is essentially determined by the active area region of the cell (which actually represents a small portion of the total cell area), and since negative potentials on the control gate line CG ranging from -0.5Vpp to -0.7Vpp are sufficient to start electron tunnelling, the value of capacitor C does not have to be very high, and the total memory chip area is not exagerately increased.
- a negative potential of about -0.5Vpp can be obtaned on the control gate line CG provided that C has at least an area of 3 ⁇ m 2 per bit, i.e. per each cell connected to the control gate line CG; this value should be compared to the cell's area, which in the case of an EEPROM device ranges from 15 ⁇ m 2 to 20 ⁇ m 2 . while for Flash EEPROMs it ranges from 7 ⁇ m 2 to 12 ⁇ m 2 .
- the capacitor C could also be obtained using as plates one polysilicon layer and an underlying N type diffusion.
- the capacitor can be obtained between a polysilicon layer and an inversion layer in the P-type substrate since potential on node A never falls to negative values.
- the MOSFET TA must be able to sustain a voltage of 2Vpp between source and drain; alternatively, the source of MOSFET TA could be disconnencted from the output of the charge pump generating Vpp before TY is turned on.
- each word line of the memory matrix With a respective elementary circuit 1, no negative voltage charge pumps are required to program the memory cells, since the negative voltage is generated directly on the selected word line of cells to be programmed by the elementary circuit 1.
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
The present invention relates to a non-volatile memory device comprising a structure for supplying
negative programming voltages to non-volatile memory cells in said
non-volatile memory device.
It is known that EEPROM and Flash EEPROM memory devices can
be programmed in one or another of two logical states by
respectively introducing electrons into or removing electrons
from the memory cells' floating gates. This latter operation is
termed "writing" in EEPROMs, while in Flash EEPROMs it is
referred to as "erasure".
The removal of electrons from a cell's floating gate is
accomplished by tunnelling electrons from the floating gate
into an underlying N+ diffusion, which in the case of a Flash
EEPROM device constitute the source region of the cell while in
an EEPROM device can represent either the source or the drain
region of the cell, through a thin oxide region called "tunnel
oxide"; electron tunnelling takes place if the potential
difference between the floating gate and said underlying
diffusion is made negative and its absolute value exceeds a
value depending on the cells' characteristics.
A common technique provides for grounding the cell's
control gate (which is capacitively coupled to the floating
gate), while raising the underlying diffusion potential to a
value generally higher than 10 V.
When however the diffusion potential is raised to such
values, band-to-band tunnelling causes significant leakage
currents to appear, thereby making it impossible to program the
memory device by just supplying it one single voltage supply,
or to use the memory device in a battery-supplied environment.
To overcome such a problem, a different technique has been
introduced, which provides for lowering the control gate
potential to a negative value (with respect to the ground
reference voltage) ranging from -6 V to -8 V and generated by a
circuitry internal to the memory device, and raising the
potential of the N+ diffusion under the tunnel oxide to a
moderately high value, for example corresponding to the voltage
supply value of the memory device.
A circuit implementing this technique is described in the
US Patent 5,077,691, and comprises three P-channel MOSFETs, two
of which are connected in series between the output of a
positive high voltage (Vpp) source and an N-channel MOSFET
having a source connected to ground, while the third is
connected between the common node of the previous two MOSFETs
and the output of a negative high voltage (Vnn) source; the
common node to which the three MOSFETs are connected represents
a control gate line or word line which is connected to the
control gates of the cells to be programmed; the Vpp and Vnn
sources are constituted by charge pumps or voltage boosters
internal to the memory device, and generally located at the
periphery of the chip.
To transfer electrons to the floating gates of the cells to
be programmed, the charge pump for generating Vpp is activated,
and the MOSFET connected between Vpp and the control gate line
is on; the remaining two MOSFETs are instead kept off, and the
charge pump for generating Vnn is deactivated. It is thus
possible to transfer the voltage Vpp to the control gate line.
To remove electrons from the floating gates of the cells to
be programmed, the charge pump generating Vnn is activated, the
two serially-connected MOSFET are kept off, and the third
MOSFET is on, so that Vnn can be transferred to the control
gate line. The voltage effectively transferred to the control
gate line is actually given by the voltage applied to the
gate of the third MOSFET minus the MOSFET threshold voltage
(which is negative since P-channel MOSFETs are used); the gate
voltage of the third MOSFET is never equal to Vnn, since
voltage drops always occur between the output of the Vnn charge
pump and the gate of the third MOSFET, due to the long
interconnection line and the presence of selection transistors:
the gate voltage of the third MOSFET is therefore, in an
absolute value sense, lower than Vnn.
Since moreover the third MOSFET has its source connected to
the control gate line and the body (i.e. the N well in which
the P-channel MOSFETs are obtained) connected to ground, the
MOSFET threshold voltage increases (in absolute value) and the
voltage effectively transferred to the control gate line can be
2 or 3 V higher than the voltage applied to the gate of the
MOSFET. This value could be not sufficiently negative to start
tunnelling of electrons.
A possible solution to the abovementioned problem provides
for voltage boosting the gate of the third MOSFET, at the
expense of an increase in both the complexity of the circuit
and in the total memory chip area.
US-A-5,077,691 discloses a Flash EEPROM device with a memory cell array, a +12V
charge pump, a -2V charge pump, a -12V charge pump, and a plurality of gate
switch circuits, one for each word line of the array, for selectively coupling the
respective word line to either the +12V, or the -2V, or the -12V common voltage
rails. US-A-4,797,899 discloses a monolithic integrated circuit including a positive
voltage doubler, a voltage inverting portion for generating a negative voltage, and
in RS-232-transmitter/receiver.
The capacitors for the positive voltage doubler and the inverting circuit portion
are not integrated in the chip, but are external. EP-A-0 456 623 discloses a Flash
EEPROM memory having a unique negative charge pump, coupled to the word
lines through respective MOSFETs, each MOSFET being controlled by a respective
bootstrapping circuit.
In view of the state of the art just described, the object
of the present invention is to provide a structure for supplying
negative voltages to non-volatile memory cells in a
non-volatile memory device
which, without increasing
significantly the total chip area, is not affected by the
abovementioned problems.
According to the present invention, such object is attained
by means of
a non-volatile memory
device as set forth in claim 1.
Thanks to the above mentioned structure, said elementary
circuit occupies a limited area making it possible to
accomplish a memory device in which each word line is closely
connected, at its ends, to a respective elementary circuit
(which works as a "local" negative voltage charge pump) so that
the negative voltage required to program the memory cells
connected to a selected word line is generated directly on such
word line; in this case, it is only necessary to provide the
memory device with a positive voltage charge pump.
The features of the present invention shall be made more
evident by the following detailed description of an
embodiment, illustrated as a non-limiting example in
the annexed drawing, wherein:
Figure 1 is a schematic diagram of a structure according to an embodiment of the invention.
Figure 1 is a schematic diagram of a structure according to an embodiment of the invention.
In Figure 1, an elementary circuit 1 according to the
invention for generating a negative voltage starting from a
positive high voltage supply Vpp is shown. The circuit 1
comprises a first MOSFET TX whose drain and source are
respectively connected to a positive high voltage supply line
Vpp and to a first node A, a second MOSFET TY with drain and
source respectively connected to node A and to a reference
voltage line GND, a third MOSFET TB whose drain and source are
respectively connected to the reference voltage line GND and to
a second node B representing a negative voltage output of the
elementary circuit 1 and to which in this embodiment a control
gate line CG (constituting a word line of the memory matrix) is
also connected, and a capacitor C connected between node A and
node B. Non-volatile memory cells (not shown) are connected to
the control gate line CG by their control gates. A fourth
MOSFET TA with source and drain respectively connected to Vpp
and to node B is also shown, and is used in a per se know way
to transfer to the control gate line CG the voltage Vpp when
electrons are to be transferred to the floating gates of the
memory cells connected to CG. TA and TB are P-channel MOSFETs,
while in the example of Figure 1 TX and TY are high-voltage
N-channel MOSFETs, but could as well be both P-channel MOSFETs,
or one a P-channel and the other an N-channel MOSFET. The high
voltage supply line Vpp can be connected to an external
high-voltage supply, or to the output of a conventional charge
pump not shown in the drawings, which starting from a supply
voltage applied externally to the memory device raises it to a
value sufficient to determine the transfer of electrons, either
by tunnelling (EEPROMs) or by hot electrons injection (Flash
EEPROMs) to the floating gates of the memory cells. Said charge
pump is normally located at the periphery of the memory device
chip.
When electrons are to be transferred to a floating gate of
a selected cell whose control gate is connected to the control
gate line CG, TA is turned on by applying to its gate electrode
the reference voltage GND, while TB is kept off by applying to
its gate electrode the high voltage Vpp. In this condition the
control gate line CG voltage is raised to Vpp. In order to
reduce the parasitic capacitances to be charged in this phase,
TX and TY should also be kept in the off state so that node A
is left floating.
When electrons are to be extracted from a floating gate of
a selected cell belonging to the word line CG, TA is turned
off, while TB and TX are turned on by applying to their gate
electrodes the voltages GND and Vpp, respectively; this causes
node A to be connected to Vpp and node B to be grounded; this
fact determines the charging of capacitor C to the voltage Vpp.
Obviously, in the case that TX is a P-channel MOSFET, the
reference voltage GND must be applied to its gate electrode to
turn TX on. After capacitor C has been charged, TX and TB are
turned off and TY is turned on, so that the potential on node A
is lowered from Vpp to ground. This causes, by charge
conservation, the potential on node B (i.e. on the control gate
line CG) to drop to a negative potential given by the partition
of the charge stored in the capacitor C between C and the
parasitic capacitances associated to the control gate line CG,
and to TA and TB: the higher the value of C compared to said
parasitic capacitances, the better said negative potential
approximates -Vpp. Since the control gate capacitance of a
memory cell is essentially determined by the active area region
of the cell (which actually represents a small portion of the
total cell area), and since negative potentials on the control
gate line CG ranging from -0.5Vpp to -0.7Vpp are sufficient to
start electron tunnelling, the value of capacitor C does not
have to be very high, and the total memory chip area is not
exagerately increased. If for example the memory device is
fabricated in a 0.8 µm technology and the capacitor C is
obtained using as plates the two polysilicon layers
constituting the floating gate and the control gate of the
memory cells, a negative potential of about -0.5Vpp can be
obtaned on the control gate line CG provided that C has at
least an area of 3 µm2 per bit, i.e. per each cell connected to
the control gate line CG; this value should be compared to the
cell's area, which in the case of an EEPROM device ranges from
15 µm2 to 20 µm2. while for Flash EEPROMs it ranges from
7 µm2 to 12 µm2. The capacitor C could also be obtained using
as plates one polysilicon layer and an underlying N type
diffusion. As a third possibility, the capacitor can be
obtained between a polysilicon layer and an inversion layer in
the P-type substrate since potential on node A never falls to
negative values.
The MOSFET TA must be able to sustain a voltage of 2Vpp
between source and drain; alternatively, the source of MOSFET
TA could be disconnencted from the output of the charge pump
generating Vpp before TY is turned on.
Furthermore, it is possible to control the shape of the
voltage pulse applied to CG, i.e. to sharpen or to smooth its
edges, by just modulating the conductivity of TY.
By providing each word line of the memory matrix with a
respective elementary circuit 1, no negative voltage charge
pumps are required to program the memory cells, since the
negative voltage is generated directly on the selected word
line of cells to be programmed by the elementary circuit 1.
Claims (8)
- A non-volatile memory device comprising a structure for supplying negative programming voltages to non-volatile memory cells in said non-volatile memory device, said non-volatile memory cells each comprising a floating gate and a control gate, said matrix comprising a plurality of word lines (CG) each of which is connected to a plurality of control gates of respective memory cells, characterized in that said structure comprises a plurality of elementary circuits (1;2;VB1-VBn) each elementary circuit being constituted by a capacitor (C), first switching means (TX,TY) for alternatively connecting a first plate (A) of the capacitor (C) to a positive high-voltage supply (Vpp) or to a reference voltage supply (GND), and second switching means (TB) for respectively connecting or disconnecting a second plate (B) of the capacitor (C), which second plate is also connected to at least one word line, to the reference voltage supply (GND), the second plate (B) of the capacitor (C) of each elementary circuit being directly connected to a respective word line (CG) to supply said word line (CG) with a negative voltage suitable to remove electrons stored on the floating gates of the memory cells connected to said word line (CG).
- The device according to claim 1, characterized in that said first switching means comprises a first transistor (TX) connected between the positive high voltage supply (Vpp) and the first plate (A) of the capacitor (C) and a second transistor (TY) connected between said first plate (A) and the reference voltage supply (GND), and the second switching means comprises a third transistor (TB) connected between the second plate (B) of the capacitor (C) and the reference voltage supply (GND).
- The device according to claim 2, characterized in that said first (TX) and second (TY) transistors are N-channel MOSFETs, while said third transistor (TB) is a P-channel MOSFET.
- The device according to claim 2, characterized in that said first (TX), second (TY) and third (TB) transistors are P-channel MOSFETs.
- The device according to claim 2, characterized in that said first (TX) and third (TB) transistors are P-channel MOSFETs, while said second transistor (TY) is an N-channel MOSFET.
- The device according to claim 2, characterized in that said first transistor (TX) is an N-channel MOSFET, while said second (TY) and third (TB) transistors are P-channel MOSFETs.
- A device according to claim 1, characterized in that said capacitor (C) has the first plate (A) represented by a first polysilicon layer from which the floating gates of the memory cells are also obtained and the second plate (B) represented by a second polysilicon layer from which the control gates of the memory cells are also obtained.
- A device according to claim 1, characterized in that said capacitor (C) has the first plate (A) represented by a semiconductor region, and the second plate (B) represented by a polysilicon layer superimposed on and insulated from said semiconductor region by a dielectric layer.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE69325809T DE69325809T2 (en) | 1993-11-24 | 1993-11-24 | Non-volatile memory arrangement with means for generating negative programming voltages |
| EP93830464A EP0654791B1 (en) | 1993-11-24 | 1993-11-24 | Non-voltaile memory device having means for supplying negative programming voltages |
| JP28634994A JP2718902B2 (en) | 1993-11-24 | 1994-11-21 | Apparatus for supplying a negative programming voltage to a non-volatile memory cell |
| US08/344,232 US5528536A (en) | 1993-11-24 | 1994-11-23 | Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device |
| US08/639,931 US5659501A (en) | 1993-11-24 | 1996-04-26 | Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device |
| US08/871,226 US5818760A (en) | 1993-11-24 | 1997-06-09 | Method and device for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP93830464A EP0654791B1 (en) | 1993-11-24 | 1993-11-24 | Non-voltaile memory device having means for supplying negative programming voltages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0654791A1 EP0654791A1 (en) | 1995-05-24 |
| EP0654791B1 true EP0654791B1 (en) | 1999-07-28 |
Family
ID=8215251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP93830464A Expired - Lifetime EP0654791B1 (en) | 1993-11-24 | 1993-11-24 | Non-voltaile memory device having means for supplying negative programming voltages |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US5528536A (en) |
| EP (1) | EP0654791B1 (en) |
| JP (1) | JP2718902B2 (en) |
| DE (1) | DE69325809T2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69325809T2 (en) * | 1993-11-24 | 1999-12-09 | Stmicroelectronics S.R.L., Agrate Brianza | Non-volatile memory arrangement with means for generating negative programming voltages |
| US5999461A (en) * | 1996-06-07 | 1999-12-07 | Ramtron International Corporation | Low voltage bootstrapping circuit |
| DE69619972D1 (en) * | 1996-06-18 | 2002-04-25 | St Microelectronics Srl | Non-volatile memory device with low supply voltage and voltage booster |
| KR100255519B1 (en) * | 1997-05-08 | 2000-05-01 | 김영환 | Stable data latch for sram and method thereof |
| US5841695A (en) * | 1997-05-29 | 1998-11-24 | Lsi Logic Corporation | Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell |
| JP4827040B2 (en) * | 1999-06-30 | 2011-11-30 | 株式会社日立プラズマパテントライセンシング | Plasma display device |
| US6671769B1 (en) * | 1999-07-01 | 2003-12-30 | Micron Technology, Inc. | Flash memory with fast boot block access |
| US7038945B2 (en) * | 2004-05-07 | 2006-05-02 | Micron Technology, Inc. | Flash memory device with improved programming performance |
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|---|---|---|---|---|
| JPS5619676A (en) * | 1979-07-26 | 1981-02-24 | Fujitsu Ltd | Semiconductor device |
| US4435785A (en) * | 1981-06-02 | 1984-03-06 | Texas Instruments Incorporated | Unipolar voltage non-volatile JRAM cell |
| US4742492A (en) * | 1985-09-27 | 1988-05-03 | Texas Instruments Incorporated | EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor |
| US4797899A (en) * | 1986-12-15 | 1989-01-10 | Maxim Integrated Products, Inc. | Integrated dual charge pump power supply including power down feature and rs-232 transmitter/receiver |
| JPH03219496A (en) * | 1990-01-25 | 1991-09-26 | Hitachi Ltd | Nonvolatile semiconductor memory device |
| US5077691A (en) * | 1989-10-23 | 1991-12-31 | Advanced Micro Devices, Inc. | Flash EEPROM array with negative gate voltage erase operation |
| IT1239781B (en) * | 1990-05-08 | 1993-11-15 | Texas Instruments Italia Spa | CIRCUIT AND METHOD TO SELECTIVELY SWITCH NEGATIVE VOLTAGES IN CMOS INTEGRATED CIRCUITS |
| US5103160A (en) * | 1991-04-25 | 1992-04-07 | Hughes Aircraft Company | Shunt regulator with tunnel oxide reference |
| US5428568A (en) * | 1991-10-30 | 1995-06-27 | Mitsubishi Denki Kabushiki Kaisha | Electrically erasable and programmable non-volatile memory device and a method of operating the same |
| US5331188A (en) * | 1992-02-25 | 1994-07-19 | International Business Machines Corporation | Non-volatile DRAM cell |
| JP2905666B2 (en) * | 1992-05-25 | 1999-06-14 | 三菱電機株式会社 | Internal voltage generation circuit in semiconductor device and nonvolatile semiconductor memory device |
| JPH06104672A (en) * | 1992-09-22 | 1994-04-15 | Mitsubishi Electric Corp | Clamp circuit |
| DE69325809T2 (en) * | 1993-11-24 | 1999-12-09 | Stmicroelectronics S.R.L., Agrate Brianza | Non-volatile memory arrangement with means for generating negative programming voltages |
-
1993
- 1993-11-24 DE DE69325809T patent/DE69325809T2/en not_active Expired - Fee Related
- 1993-11-24 EP EP93830464A patent/EP0654791B1/en not_active Expired - Lifetime
-
1994
- 1994-11-21 JP JP28634994A patent/JP2718902B2/en not_active Expired - Lifetime
- 1994-11-23 US US08/344,232 patent/US5528536A/en not_active Expired - Lifetime
-
1996
- 1996-04-26 US US08/639,931 patent/US5659501A/en not_active Expired - Lifetime
-
1997
- 1997-06-09 US US08/871,226 patent/US5818760A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2718902B2 (en) | 1998-02-25 |
| US5818760A (en) | 1998-10-06 |
| JPH07254293A (en) | 1995-10-03 |
| DE69325809T2 (en) | 1999-12-09 |
| US5528536A (en) | 1996-06-18 |
| US5659501A (en) | 1997-08-19 |
| EP0654791A1 (en) | 1995-05-24 |
| DE69325809D1 (en) | 1999-09-02 |
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