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EP0653105A1 - Planarizing bumps for interconnecting matching arrays of electrodes - Google Patents

Planarizing bumps for interconnecting matching arrays of electrodes

Info

Publication number
EP0653105A1
EP0653105A1 EP93917226A EP93917226A EP0653105A1 EP 0653105 A1 EP0653105 A1 EP 0653105A1 EP 93917226 A EP93917226 A EP 93917226A EP 93917226 A EP93917226 A EP 93917226A EP 0653105 A1 EP0653105 A1 EP 0653105A1
Authority
EP
European Patent Office
Prior art keywords
bumps
electrodes
resin
layer
diamond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP93917226A
Other languages
German (de)
French (fr)
Inventor
Stanley F. Tead
Stephen J. Znameroski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Co
Original Assignee
Minnesota Mining and Manufacturing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minnesota Mining and Manufacturing Co filed Critical Minnesota Mining and Manufacturing Co
Publication of EP0653105A1 publication Critical patent/EP0653105A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01006—Carbon [C]
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01023—Vanadium [V]
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01061—Promethium [Pm]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12033—Gunn diode
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    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting

Definitions

  • the invention concerns interconnecting arrays of electrodes of two electronic devices, e.g., connecting pads of a semiconductor device to a matching pattern of traces and/or pads on a printed circuit board or an interconnect.
  • it relates to an improved process for preparing metal bumps on the electrodes of one electronic device for use in such interconnecting.
  • Electrodes are becoming smaller and more complex, e.g., having larger numbers of electrodes of finer pitch. Hundreds of individual connections between two electronic devices must be made across areas that may be about a square centimeter in area or even smaller.
  • a semiconductor device may have a large number of electrodes or contact pads, as they are known, to be connected individually to another set of electrodes such as traces or pads on an interconnect or circuit board.
  • the term "electronic device” will be understood to refer to active semiconductor integrated circuits as well as circuit boards and interconnects on which such circuits are to be mounted and test coupons for testing such circuits.
  • One method of making such connections involves forming a metal bump on each pad of the semiconductor device or appropriate traces or pads of the interconnect or circuit board.
  • the bumps are formed on the traces or pads of the interconnect to reduce the number of processing steps, and resultant yield loss, on the more sensitive semiconductor device.
  • the two devices can be bonded by applying pressure and/or temperature to provide electrical contact between each aligned pair of electrodes. Such electrical contact may be maintained by a metallurgical bond, by an adhesive, or simply by maintaining the exerted pressure.
  • the bumps can be of a variety of metals, but are commonly of gold because of its high electrical conductivity as well as its corrosion resistance.
  • the bumps can be electroplated directly onto the electrodes or, as suggested in United Kingdom Patent Specification No. 1,243,097 (Gurler), they can be formed on a temporary substrate and then transferred and bonded to the electrodes. Transferring protects the electronic device from damage that might otherwise result from the cleaning and plating solutions normally used in the formation of the bumps.
  • bumps formed on a temporary substrate can be from 5 to 40 ⁇ in height and have flat contact surfaces that can be 20 ⁇ m square.
  • the bumps can be transferred to aluminum electrodes of a first semiconductor device at 250° to 450°C and a pressure on each bump of "10 to 70 g.”
  • the first semiconductor device can then be connected to a second semiconductor device at 250° to 450 °C and a pressure on each bump of "50 to 200 g.”
  • the pads of a semiconductor device typically are formed at its top level and are separated from the active circuitry by a passivating layer that has an opening or via at each of the pads. It is known in the art that the surfaces of the pads should lie in a plane, but they may not be quite coplanar due to differences in underlying levels of circuitry and other causes. Pads and traces on a circuit board or interconnect also may not be coplanar due to variations in their thicknesses.
  • traces formed by electroplating tend to build to different thicknesses in areas of different trace density. Additionally the contact surfaces of traces and pads may not be coplanar because failure to center the traces or pads precisely with respect to the electroplating anode and cathode will result in nonuniformity of their thicknesses.
  • the contact surfaces of bumps are generally not coplanar. This is because when bumps are formed on pads or on traces that deviate from a plane, the contact surfaces of the bumps tend to mirror those deviations. Additionally, it is difficult to form bumps to uniform heights for the same reasons that its difficult to form coplanar pads and traces. These problems are magnified with the bumps because, generally, they are thicker than the pads or traces. At the present time, bumps are generally formed to a height of 20 ⁇ m to allow for both recesses at the pads due to variation of the passivating layer, as well as deviations from coplanarity of the contact surfaces of bumps, while leaving a generous margin of error.
  • the electronic device may not work while under such pressure.
  • many III-N semiconductor materials such as gallium arsenide, are piezoelectric.
  • the pressure gradient resulting from the compression of the tips of the higher bumps so that the lower bumps make good electrical contact will also create an electric field across the chip. Such a field may prevent the chip from operating properly even though there is no actual defect and the chip would operate properly upon release of the pressure.
  • United States Patent No. 4,879,258 (Fisher) concerns the planarization of an integrated circuit by mechanical polishing.
  • one abrasive device taught by the Fisher patent is a glass disk with finely divided diamond particles embedded therein.
  • An alternative abrasive device that is mentioned is a diamond-tipped stylus.
  • an electronic device having a plurality of electrodes is prepared for bonding with another electronic device by positioning metal bumps surrounded by a resin on selected electrodes.
  • the bumps are then diamond turned so that the outer surfaces of all of them lie substantially in a plane.
  • the resin is then removed.
  • Figures 1 through 8 show an electronic device in various stages of processing according to the method of the present invention
  • Figure 9 is a flow chart of the most general method according to the invention.
  • Figure 10 is a flow chart of a first more specific embodiment of a method according to the present invention.
  • Figure 11 is a flow chart of a second more specific embodiment of a method according to the present invention.
  • the present invention provides a method of preparation for array bonding of an electronic device bearing a large number of electrodes by the steps of positioning on selected electrodes metallic bumps surrounded by a protective resin, diamond turning the resin layer and the bumps so that the exposed surfaces thereof lie substantially in a plane, and removing the resin layer to leave the bumps exposed.
  • Figure 1 shows two metallic conductors 10 on a substrate 12.
  • Conductors 10 could be contact pads or connector traces and could be of copper, aluminum, or other appropriate metallic conductor material.
  • Substrate 12 could be, for example, a semiconductor integrated circuit, a circuit board, or any other interconnect to which an integrated circuit may be attached.
  • a layer, 14, of a metallic electrical conductor is deposited on substrate 12 and conductor 10.
  • Layer 14 could be deposited by any known technique, such as sputtering. Layer 14 will be used in later steps to provide a field plane for electroplating.
  • a layer of resin, 16, is next applied over metallic conductor layer 14.
  • resin layer 16 is of a material that, after curing, will be machinable without excessive smearing or chipping at ordinary room temperatures and will support the bumps during machining.
  • the resin is preferably a radiation curable resist.
  • the most commonly used types of radiation curable resists are photoresists. Examples of photoresists that may be machined without undue smearing at ordinary room temperatures are cresol novolak resins and acrylates.
  • Other resins useful in the present process include polyimides and epoxies.
  • Resin layer 16 is next patterned using a standard process. Typically resin 16 is patterned by photolithography and is exposed through an appropriate mask although other techniques, such as writing the pattern with a laser, may be used. Alternatively, resin 16 could be patternable in other ways, such as by exposure to an electron beam. After exposure the resist is developed leaving openings in the locations where bumps are desired. As shown in Figure 4, two openings 18 have been formed. A metallic conductor, preferably copper, is then deposited, typically by electroplating, into the openings such as opening 18 formed in resin layer 16. As shown in Figure 5, the copper bumps 20 are preferably slightly shorter than resin layer 16. In addition the thickness of underlying conductor layer 10 should be great enough to be resistant to breakage during machining. Experience has shown that thicknesses of layer 10 of less than 1 ⁇ m are subject to such breakout. Furthermore such breakage is reduced when conductor layers 10 are wider than bumps 20.
  • Resin layer 16 and electrically conductive bumps 20 are next machined by diamond turning to produce a smooth coplanar surface.
  • Diamond turning is a well-known machining technique in which a single point diamond tool is used to cut to a well controlled depth in the material until the machined surface matches a desired profile.
  • Preferable diamond tools for use with the present invention will have a tip radius in the range of 0.5 to 5 mm.
  • resin layer 16 is preferably of a material that is machinable without undue smearing or chipping at room temperature. If, however, for some reason it is desired to use a material that is not so machinable during the electroplating step, that material may be removed and replaced with a machinable material after bumps 20 have been formed.
  • the use of resin layer 16 during the diamond turning step provides significant advantages. This material protects bumps 20 from abrupt contact with the diamond tool and absorbs much of the shear force applied to the bumps during the diamond turning process. This helps to prevent the breakage discussed previously.
  • the use of diamond turning provides significant advantages over the prior art. As stated previously, it is very difficult, if not impossible, to form the bumps to uniform heights due to variations in the deposition process. This problem is exacerbated by underlying variations in height at different locations on the substrate. For example, if the bumps are formed by an electroplating process, the height difference due to process variations will typically be about 5 percent. This is in addition to the variations due to the unevenness of underlying surface.
  • the height of the bumps following a diamond turning operation are determined by the position of the diamond tool relative to the surface being planarized.
  • the surface being diamond turned will be brought very close to a uniform plane, identified as plane 22 in Figure 6.
  • Using diamond turning techniques it is possible to planarize the surfaces of bumps 20 such that the maximum deviation from plane 22 is 0.5 micrometer. It is believed that it is possible to reduce the maximum deviation to 0.1 micrometer.
  • a different material may be applied to the planarized surfaces of bumps 20. For example, a thin layer of gold 28, as shown in Figure 7, may be applied.
  • layer 28 is very thin, it will not significantly reduce the degree of planarization of the surfaces of bumps 20. If the material is gold, however, thin layer 28 will provide the desirable electrical contact properties of gold while minimizing the amount of gold required and thus the expense.
  • the use of the process of the present invention makes possible the use of much thinner layers of gold than would be possible in the prior art.
  • the prior art bumps would include thicker layers of gold in order to take advantage of the greater compressibility of gold as compared with copper in order to correct for the fact that the surfaces of the bumps are not coplanar. If greater precision is required, the diamond turning could be performed after gold layer 28 is applied instead of before although this increases the amount of gold required.
  • bumps 20 may be formed on a temporary substrate and later transferred to electrically conductive layers 10 as taught by the Gurler and Hatada patents discussed previously. If this procedure is used, the bumps should be surrounded by a protective resin prior to planarization by diamond turning.
  • FIG 9 is a flow chart of the process of the invention in its most basic form.
  • a substrate having electrodes thereon has selected electrodes provided with electrically conductive bumps that are surrounded by a protective resin.
  • the bumps and the resin layer are diamond turned in order to planarize their exposed surfaces. The resin is then removed to expose the bumps.
  • FIG 10 is a flow chart of a more specific embodiment of the invention.
  • a substrate having a plurality of electrodes has a layer of a metallic conductor material sputtered thereon.
  • a layer of a radiation-sensitive resin is then applied to the substrate covering the sputtered metal.
  • the resin is then exposed and developed leaving openings over selected ones of the electrodes.
  • Electrically conductive bumps are formed in those openings by electroplating.
  • the exposed surfaces of the resin and the bumps are then planarized by diamond turning.
  • a thin layer of gold is then applied to the tops of the bumps.
  • the resin and sputtered metallic layer, except for that portion lying between the bumps and the electrodes, are removed.
  • a plurality of bumps are formed on a temporary substrate preferably by electroplating. Those bumps are removed from the temporary substrate and bonded to electrodes on the permanent substrate. A layer of resin is then coated over the bumps. The resin and the bumps are planarized by diamond turning and the resin is removed.
  • the invention will provide significant advantages even in situations where it is not used to permanently bond two electrical or electronic devices to one another.
  • One field where such advantages arise is that of the testing of integrated circuits. In order to test such circuits, there must be good electrical contact between the circuit under test and the test apparatus. One way to accomplish this is to install the integrated circuit into its packaging prior to conducting the test. In this way the integrated circuit communicates electrically with the test equipment in the same manner that it would in actual use.
  • the disadvantage of this approach is that all chips, even those that will eventually be rejected, must incur the expense of packaging. Furthermore, in many currently used methods, the package is eliminated entirely, so package level testing is not an available option.
  • An alternative to packaging the chips prior to testing thep is to provide a system for physically contacting the conductor pads on the chip to the test apparatus without actually soldering anything to those conductor pads.
  • One way to do this is to provide appropriate conductor traces on a test coupon and connect those traces to metal bumps corresponding to the contact pads on the chip. These metal bumps may then be pressed into contact with the contact pad on the chip in order to perform the tests. Due to the lack of coplanarity of the bumps manufactured according to the prior art, an undue amount of pressure must be exerted on the chip and the test coupon in order to insure good electrical contact to all of the conductor pads of the chip.
  • the chip may well test as defective even though it is not. If all of the contact pads are in contact with the bumps on the test coupon, the force required may cause damage to the chip. Alternatively, as described previously, if the chip is of a piezoelectric material, the electric field caused by the pressure could cause the chip to test as defective.
  • a test coupon may be manufactured according to the present invention. This will provide a test coupon having bumps whose surfaces are highly coplanar. In this way the test coupon may be contacted to the chip to be tested using much less pressure than otherwise would be necessary, helping to eliminate the problems of prior art test coupons.
  • Example 1 The following sequential steps were carried out: 1. A 0.5 mm thick silicon wafer, 10 cm in diameter, was primed with an adhesion layer to be used as a substrate. 2. A copper layer was sputter-deposited to a thickness of 0.3 ⁇ m.
  • the wafer thickness was measured with a digital micrometer to determine a baseline for later use in determining the level of planarization.
  • the backside of the wafer was spin-coated with American Hoechst AZP 4620 photoresist at 4000 rpm for 20 seconds, and baked at 85 °C for
  • liquid photoresist contains acetates, cresol novolak resin, and sulfonic esters.
  • the backside photoresist coating was applied to prevent electroplating onto errant copper that had been sputtered directly onto the reverse side of the wafer.
  • the front side of the wafer was coated with the same photoresist, AZP 4620, which was spin-coated at 2200 rpm for 40 seconds and baked at 85 °C for 15 minutes to produce a film approximately 12 ⁇ m thick.
  • the photoresist-coated wafer was exposed through a lithographic plate (mask) to ultraviolet (UN) radiation of 405 nm wavelength and
  • the mask contained a chrome-on-glass lithographic pattern corresponding to an electronic circuit.
  • the photoresist was developed in 1:4 solution of AZ400K developer and deionized (DI) water for 2 minutes and 15 seconds, followed by a
  • the circuit pattern was electroplated with copper to build bumps approximately 6 ⁇ m in height.
  • the photoresist was stripped using J.T. Baker PRS-1000, and the heights of the bumps were measured using the Alpha-Step 200 profilometer.
  • step 4 the backside of the wafer was coated again with a thin layer of photoresist to prevent the plating of stray copper.
  • the wafer was coated with AZP 4620 photoresist at a spin speed of 1600 rpm for 40 seconds and baked at 85 °C for 15 minutes. The spin-on and bake were again repeated to create a double layer of photoresist approximately 30 ⁇ m thick. 12.
  • a photolithographic mask having features corresponding to the bumps was aligned with the circuit trace features on the wafer and the photoresist layer was exposed for 60 seconds to UV radiation as in Step 6. The photoresist layer was then developed in 1:4 AZ400K/DI water developing solution and then rinsed.
  • the bump pattern was electroplated with copper such that the height of each of the bumps plus underlying circuit trace was approximately 23 ⁇ m.
  • Step 14 The photoresist was stripped to allow the bump + trace height to be measured. 15. A double layer of photoresist was spin coated onto the wafer surface as in Step 11, covering the bumps and the underlying copper traces. This step reinstated the support film removed in Step 15. In practice it would not be necessary to measure the bump height before planarization and therefore Steps 14 and 15 would not normally be required. 16. Planarization was performed with an Anorad diamond-turning machine; the diamond tool consisted of a steel shank on which was mounted a single crystal diamond with a face rounded to 0.75 mm and 0° rake angle.
  • the wafer was mounted on the machine's vacuum chuck, and the diamond tool was set to cut the bump/photoresist composite to a nominal 20 ⁇ m above the wafer surface; a spindle speed 3000 rpm and 15 cm/min. feed rate were used. 17. The photoresist was stripped from the wafer. **
  • the heights of the planarized bumps + trace features were measured with respect to the surface of the silicon wafer over short distances in several places using an Alpha-Step 200 surface profilometer.
  • the measured feature heights fell within a range of 19.5 - 20.6 ⁇ m, the average being 20.04 ⁇ m with a standard deviation of 0.2 ⁇ m.
  • Example 2 After repeating Steps 1 through 14 as described in Example 1, the following sequential steps were carried out: 15. A layer of Ciga-Geigy ProbimideTM 412 polyimide was spin- coated onto the surface of the wafer at a spin speed of 600 rpm for 40 seconds and baked at 55 °C for 30 minutes and 110°C for 1 hour, covering the bumps and underlying copper traces.
  • Planarization was performed with an Anorad diamond-turning machine; the diamond tool consisted of a steel shank on which was mounted a single crystal diamond with a face rounded to 0.75 mm and 0° rake angle.
  • the wafer was mounted on the machine's vacuum chuck, and the diamond tool was set to cut the bump/photoresist composite to a nominal 20 ⁇ m above the wafer surface; a spindle speed 3000 rpm and 15 cm/min. feed rate were used. 17.
  • the polyimide was stripped using ethanolamine.
  • the heights of the planarized bumps were measured with respect to the surface of the silicon wafer over short distances in several places using an Alpha-Step 200 surface profilometer.
  • the measured feature heights were within a range of 18.6 ⁇ m to 20.8 ⁇ m with an average height of 20.0 ⁇ m and standard deviation of 0.5 ⁇ m.

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Abstract

An electronic device having a plurality of electrodes is prepared for bonding with another electronic device by positioning metal bumps surrounded by a resin on selected electrodes. The bumps are then diamond turned to that the outer surfaces of all of them lie substantially in a plane. The resin is then removed.

Description

PLANARIZING BUMPS FOR INTERCONNECT ΪG MATCHING ARRAYS OF ELECTRODES
Field of the Invention The invention concerns interconnecting arrays of electrodes of two electronic devices, e.g., connecting pads of a semiconductor device to a matching pattern of traces and/or pads on a printed circuit board or an interconnect. In particular, it relates to an improved process for preparing metal bumps on the electrodes of one electronic device for use in such interconnecting.
Background of the Invention
Electronic devices are becoming smaller and more complex, e.g., having larger numbers of electrodes of finer pitch. Hundreds of individual connections between two electronic devices must be made across areas that may be about a square centimeter in area or even smaller. For example, a semiconductor device may have a large number of electrodes or contact pads, as they are known, to be connected individually to another set of electrodes such as traces or pads on an interconnect or circuit board. For purposes contained herein, the term "electronic device" will be understood to refer to active semiconductor integrated circuits as well as circuit boards and interconnects on which such circuits are to be mounted and test coupons for testing such circuits.
One method of making such connections involves forming a metal bump on each pad of the semiconductor device or appropriate traces or pads of the interconnect or circuit board. Preferably the bumps are formed on the traces or pads of the interconnect to reduce the number of processing steps, and resultant yield loss, on the more sensitive semiconductor device.
After aligning each bump with an electrode to which it is to be bonded, the two devices can be bonded by applying pressure and/or temperature to provide electrical contact between each aligned pair of electrodes. Such electrical contact may be maintained by a metallurgical bond, by an adhesive, or simply by maintaining the exerted pressure. The bumps can be of a variety of metals, but are commonly of gold because of its high electrical conductivity as well as its corrosion resistance.
The bumps can be electroplated directly onto the electrodes or, as suggested in United Kingdom Patent Specification No. 1,243,097 (Gurler), they can be formed on a temporary substrate and then transferred and bonded to the electrodes. Transferring protects the electronic device from damage that might otherwise result from the cleaning and plating solutions normally used in the formation of the bumps. In United States Patent No. 4,693,770 (Hatada), bumps formed on a temporary substrate can be from 5 to 40 μ in height and have flat contact surfaces that can be 20 μm square. The bumps can be transferred to aluminum electrodes of a first semiconductor device at 250° to 450°C and a pressure on each bump of "10 to 70 g." The first semiconductor device can then be connected to a second semiconductor device at 250° to 450 °C and a pressure on each bump of "50 to 200 g." The pads of a semiconductor device typically are formed at its top level and are separated from the active circuitry by a passivating layer that has an opening or via at each of the pads. It is known in the art that the surfaces of the pads should lie in a plane, but they may not be quite coplanar due to differences in underlying levels of circuitry and other causes. Pads and traces on a circuit board or interconnect also may not be coplanar due to variations in their thicknesses. For example, traces formed by electroplating tend to build to different thicknesses in areas of different trace density. Additionally the contact surfaces of traces and pads may not be coplanar because failure to center the traces or pads precisely with respect to the electroplating anode and cathode will result in nonuniformity of their thicknesses.
Another aspect of the nonplanarity problem is discussed in United
States Patent No. 4,749,120 (Hatada) which says that "if a mounting surface of a wiring board has some twisted or curved portion and a semiconductor device is mounted and fixed on such twisted or curved surface portion through a metal bump connection, it may occur that the semiconductor device itself or a metal bump connection is destroyed by unnecessary force owing to the twisted or curved surface portion" (col. 1, lines 42 through 49). It copes with this by interposing a hardenable insulating resin such as an epoxy resin between the metal bumps of the semiconductor device and the wiring pattern and then applying sufficient pressure to force the bumps and wiring pattern through the resin. The hardened resin is said to prevent an end portion of the semiconductor device from being damaged by contacting the wiring pattern.
In addition to the fact that the traces and contact pads are not coplanar, the contact surfaces of bumps are generally not coplanar. This is because when bumps are formed on pads or on traces that deviate from a plane, the contact surfaces of the bumps tend to mirror those deviations. Additionally, it is difficult to form bumps to uniform heights for the same reasons that its difficult to form coplanar pads and traces. These problems are magnified with the bumps because, generally, they are thicker than the pads or traces. At the present time, bumps are generally formed to a height of 20 μm to allow for both recesses at the pads due to variation of the passivating layer, as well as deviations from coplanarity of the contact surfaces of bumps, while leaving a generous margin of error.
In known techniques for producing electronic devices in economical, large-scale production that have large numbers of bumps, either on pads or on traces, the contact surfaces of the bumps of each electronic device commonly deviate from a plane by ± 1 μm or more. When such devices are electrically contacted to other devices, either permanently by bonding or temporarily by pressure, it is necessary to apply pressures and/or temperatures sufficient to compress the tips of the higher bumps until the contact surfaces of the lower bumps come into contact with a matching electrode. Only then will all of the bumps be in electrical contact with the electrodes. Such temperatures and pressures have the potential of damaging sensitive electronic devices. Even when temperatures and pressures are kept so low that any damage cannot be detected initially, that damage might lead to eventual failure. Furthermore, even if no actual damage is done, the electronic device may not work while under such pressure. For example, many III-N semiconductor materials, such as gallium arsenide, are piezoelectric. Thus the pressure gradient resulting from the compression of the tips of the higher bumps so that the lower bumps make good electrical contact will also create an electric field across the chip. Such a field may prevent the chip from operating properly even though there is no actual defect and the chip would operate properly upon release of the pressure.
Because of concerns about possible damage to semiconductor devices in the bonding process, designers tend to avoid placing circuitry in areas under the pads. Any assurance against such damage would allow more efficient use of space in placing circuitry. The article "A Planar Approach to High Density Copper-polyimide
Interconnect Fabrication," Proceedings of the Technical Conference. Eighth Annual International Electronics Packaging Conference, Nov. 7-10, 1988, (Pan et al.) concerns a method of making a multilayer interconnect that can be used as a multi-chip substrate. The interconnect is built using "pattern electroplating to plate copper to form the conductor layers and the pillar layers. These copper features are overcoated with nickel for enhanced reliability before polyimide is spin coated over the plated features to partially planarize the topography. Mechanical polishing is then carried out to fully planarize the substrate surface and expose the copper pillars. The substrate is then ready for the next layers of conductor and pillar fabrication." A similar process is described in United States Patent No. 4,810,332 (Pan).
United States Patent No. 4,879,258 (Fisher) concerns the planarization of an integrated circuit by mechanical polishing. Among other possibilities, one abrasive device taught by the Fisher patent is a glass disk with finely divided diamond particles embedded therein. An alternative abrasive device that is mentioned is a diamond-tipped stylus.
To the extent that Pan and Fisher employ mechanical polishing to make rough surfaces more smooth, those surfaces might be called "planarized. " However, it is well-known in the art that surfaces that are not initially coplanar cannot be polished to become coplanar. This is because polishing involves using essentially a constant and equal pressure on all of the surfaces to be polished. This removes substantially equal amounts of material from across the surfaces except at areas of differing hardness. Furthermore, it is not possible to directly control the final height of the bumps with an abrasion process. Instead the bump height must be monitored and the process stopped when the desired height is reached.
Summary of the Invention
According to the present invention, an electronic device having a plurality of electrodes is prepared for bonding with another electronic device by positioning metal bumps surrounded by a resin on selected electrodes. The bumps are then diamond turned so that the outer surfaces of all of them lie substantially in a plane. The resin is then removed.
Brief Description of the Drawings Figures 1 through 8 show an electronic device in various stages of processing according to the method of the present invention;
Figure 9 is a flow chart of the most general method according to the invention;
Figure 10 is a flow chart of a first more specific embodiment of a method according to the present invention; and Figure 11 is a flow chart of a second more specific embodiment of a method according to the present invention.
Detailed Description of a Preferred Embodiment The present invention provides a method of preparation for array bonding of an electronic device bearing a large number of electrodes by the steps of positioning on selected electrodes metallic bumps surrounded by a protective resin, diamond turning the resin layer and the bumps so that the exposed surfaces thereof lie substantially in a plane, and removing the resin layer to leave the bumps exposed.
The process of the present invention may be better understood by reference to the figures. Figure 1 shows two metallic conductors 10 on a substrate 12. Conductors 10 could be contact pads or connector traces and could be of copper, aluminum, or other appropriate metallic conductor material. Substrate 12 could be, for example, a semiconductor integrated circuit, a circuit board, or any other interconnect to which an integrated circuit may be attached. As shown in Figure 2, a layer, 14, of a metallic electrical conductor is deposited on substrate 12 and conductor 10. Layer 14 could be deposited by any known technique, such as sputtering. Layer 14 will be used in later steps to provide a field plane for electroplating.
As shown in Figure 3, a layer of resin, 16, is next applied over metallic conductor layer 14. Preferably, resin layer 16 is of a material that, after curing, will be machinable without excessive smearing or chipping at ordinary room temperatures and will support the bumps during machining. Furthermore, the resin is preferably a radiation curable resist. The most commonly used types of radiation curable resists are photoresists. Examples of photoresists that may be machined without undue smearing at ordinary room temperatures are cresol novolak resins and acrylates. Other resins useful in the present process include polyimides and epoxies.
Resin layer 16 is next patterned using a standard process. Typically resin 16 is patterned by photolithography and is exposed through an appropriate mask although other techniques, such as writing the pattern with a laser, may be used. Alternatively, resin 16 could be patternable in other ways, such as by exposure to an electron beam. After exposure the resist is developed leaving openings in the locations where bumps are desired. As shown in Figure 4, two openings 18 have been formed. A metallic conductor, preferably copper, is then deposited, typically by electroplating, into the openings such as opening 18 formed in resin layer 16. As shown in Figure 5, the copper bumps 20 are preferably slightly shorter than resin layer 16. In addition the thickness of underlying conductor layer 10 should be great enough to be resistant to breakage during machining. Experience has shown that thicknesses of layer 10 of less than 1 μm are subject to such breakout. Furthermore such breakage is reduced when conductor layers 10 are wider than bumps 20.
Resin layer 16 and electrically conductive bumps 20 are next machined by diamond turning to produce a smooth coplanar surface. Diamond turning is a well-known machining technique in which a single point diamond tool is used to cut to a well controlled depth in the material until the machined surface matches a desired profile. Preferable diamond tools for use with the present invention will have a tip radius in the range of 0.5 to 5 mm. As previously stated, resin layer 16 is preferably of a material that is machinable without undue smearing or chipping at room temperature. If, however, for some reason it is desired to use a material that is not so machinable during the electroplating step, that material may be removed and replaced with a machinable material after bumps 20 have been formed. The use of resin layer 16 during the diamond turning step provides significant advantages. This material protects bumps 20 from abrupt contact with the diamond tool and absorbs much of the shear force applied to the bumps during the diamond turning process. This helps to prevent the breakage discussed previously. The use of diamond turning provides significant advantages over the prior art. As stated previously, it is very difficult, if not impossible, to form the bumps to uniform heights due to variations in the deposition process. This problem is exacerbated by underlying variations in height at different locations on the substrate. For example, if the bumps are formed by an electroplating process, the height difference due to process variations will typically be about 5 percent. This is in addition to the variations due to the unevenness of underlying surface. Further, if a constant pressure abrading process is used to attempt to planarize the bumps, there will still be significant height variation due to the nature of the abrading process. In contrast to this, the height of the bumps following a diamond turning operation are determined by the position of the diamond tool relative to the surface being planarized. Thus, the surface being diamond turned will be brought very close to a uniform plane, identified as plane 22 in Figure 6. Using diamond turning techniques it is possible to planarize the surfaces of bumps 20 such that the maximum deviation from plane 22 is 0.5 micrometer. It is believed that it is possible to reduce the maximum deviation to 0.1 micrometer. If desired a different material may be applied to the planarized surfaces of bumps 20. For example, a thin layer of gold 28, as shown in Figure 7, may be applied. Because layer 28 is very thin, it will not significantly reduce the degree of planarization of the surfaces of bumps 20. If the material is gold, however, thin layer 28 will provide the desirable electrical contact properties of gold while minimizing the amount of gold required and thus the expense. The use of the process of the present invention makes possible the use of much thinner layers of gold than would be possible in the prior art. The prior art bumps would include thicker layers of gold in order to take advantage of the greater compressibility of gold as compared with copper in order to correct for the fact that the surfaces of the bumps are not coplanar. If greater precision is required, the diamond turning could be performed after gold layer 28 is applied instead of before although this increases the amount of gold required.
Following the application of thin layer 28, resin 16 is stripped away. Following that, all of layer 14, except that portion directly underlying bumps 20, is removed. The resulting structure is shown in Figure 8. When the structure of Figure 8 is produced, the device is ready for bonding using standard techniques of pressure and/or heat. Because the surfaces of the bumps conform much more closely to a plane than in the prior art, however, the amount of pressure required is reduced thus reducing the incidence of damage to the electronic circuits. In an alternative embodiment bumps 20 may be formed on a temporary substrate and later transferred to electrically conductive layers 10 as taught by the Gurler and Hatada patents discussed previously. If this procedure is used, the bumps should be surrounded by a protective resin prior to planarization by diamond turning.
Figure 9 is a flow chart of the process of the invention in its most basic form. As shown in Figure 9, a substrate having electrodes thereon has selected electrodes provided with electrically conductive bumps that are surrounded by a protective resin. In the second step the bumps and the resin layer are diamond turned in order to planarize their exposed surfaces. The resin is then removed to expose the bumps.
Figure 10 is a flow chart of a more specific embodiment of the invention. According to the process of Figure 10, a substrate having a plurality of electrodes has a layer of a metallic conductor material sputtered thereon. A layer of a radiation-sensitive resin is then applied to the substrate covering the sputtered metal. The resin is then exposed and developed leaving openings over selected ones of the electrodes. Electrically conductive bumps are formed in those openings by electroplating. The exposed surfaces of the resin and the bumps are then planarized by diamond turning. A thin layer of gold is then applied to the tops of the bumps. Finally the resin and sputtered metallic layer, except for that portion lying between the bumps and the electrodes, are removed.
In an alternative embodiment, shown in flow chart form in Figure 11, a plurality of bumps are formed on a temporary substrate preferably by electroplating. Those bumps are removed from the temporary substrate and bonded to electrodes on the permanent substrate. A layer of resin is then coated over the bumps. The resin and the bumps are planarized by diamond turning and the resin is removed.
The invention will provide significant advantages even in situations where it is not used to permanently bond two electrical or electronic devices to one another. One field where such advantages arise is that of the testing of integrated circuits. In order to test such circuits, there must be good electrical contact between the circuit under test and the test apparatus. One way to accomplish this is to install the integrated circuit into its packaging prior to conducting the test. In this way the integrated circuit communicates electrically with the test equipment in the same manner that it would in actual use. The disadvantage of this approach is that all chips, even those that will eventually be rejected, must incur the expense of packaging. Furthermore, in many currently used methods, the package is eliminated entirely, so package level testing is not an available option.
An alternative to packaging the chips prior to testing thep is to provide a system for physically contacting the conductor pads on the chip to the test apparatus without actually soldering anything to those conductor pads. One way to do this is to provide appropriate conductor traces on a test coupon and connect those traces to metal bumps corresponding to the contact pads on the chip. These metal bumps may then be pressed into contact with the contact pad on the chip in order to perform the tests. Due to the lack of coplanarity of the bumps manufactured according to the prior art, an undue amount of pressure must be exerted on the chip and the test coupon in order to insure good electrical contact to all of the conductor pads of the chip.
If one conductor pad does not make good electrical contact with the test coupon, the chip may well test as defective even though it is not. If all of the contact pads are in contact with the bumps on the test coupon, the force required may cause damage to the chip. Alternatively, as described previously, if the chip is of a piezoelectric material, the electric field caused by the pressure could cause the chip to test as defective.
A test coupon may be manufactured according to the present invention. This will provide a test coupon having bumps whose surfaces are highly coplanar. In this way the test coupon may be contacted to the chip to be tested using much less pressure than otherwise would be necessary, helping to eliminate the problems of prior art test coupons. Example 1 The following sequential steps were carried out: 1. A 0.5 mm thick silicon wafer, 10 cm in diameter, was primed with an adhesion layer to be used as a substrate. 2. A copper layer was sputter-deposited to a thickness of 0.3 μm.
3. The wafer thickness was measured with a digital micrometer to determine a baseline for later use in determining the level of planarization.
4. The backside of the wafer was spin-coated with American Hoechst AZP 4620 photoresist at 4000 rpm for 20 seconds, and baked at 85 °C for
15 minutes in a forced-air conveyer belt oven to produce a thin film approximately 15 μm thick. This commercially available liquid photoresist contains acetates, cresol novolak resin, and sulfonic esters. The backside photoresist coating was applied to prevent electroplating onto errant copper that had been sputtered directly onto the reverse side of the wafer.
5. The front side of the wafer was coated with the same photoresist, AZP 4620, which was spin-coated at 2200 rpm for 40 seconds and baked at 85 °C for 15 minutes to produce a film approximately 12 μm thick.
6. The photoresist-coated wafer was exposed through a lithographic plate (mask) to ultraviolet (UN) radiation of 405 nm wavelength and
40 mW/cm2 fluence for 15 seconds in a JBA brand exposer/aligner. The mask contained a chrome-on-glass lithographic pattern corresponding to an electronic circuit.
7. The photoresist was developed in 1:4 solution of AZ400K developer and deionized (DI) water for 2 minutes and 15 seconds, followed by a
45 minute rinse in DI water and drying under forced air. Regions of the photoresist layer corresponding to the circuit pattern were thereby opened for plating.
8. The circuit pattern was electroplated with copper to build bumps approximately 6 μm in height. 9. After plating, the photoresist was stripped using J.T. Baker PRS-1000, and the heights of the bumps were measured using the Alpha-Step 200 profilometer.
10. As in step 4, the backside of the wafer was coated again with a thin layer of photoresist to prevent the plating of stray copper.
11. The wafer was coated with AZP 4620 photoresist at a spin speed of 1600 rpm for 40 seconds and baked at 85 °C for 15 minutes. The spin-on and bake were again repeated to create a double layer of photoresist approximately 30 μm thick. 12. A photolithographic mask having features corresponding to the bumps was aligned with the circuit trace features on the wafer and the photoresist layer was exposed for 60 seconds to UV radiation as in Step 6. The photoresist layer was then developed in 1:4 AZ400K/DI water developing solution and then rinsed. 13. The bump pattern was electroplated with copper such that the height of each of the bumps plus underlying circuit trace was approximately 23 μm.
14. The photoresist was stripped to allow the bump + trace height to be measured. 15. A double layer of photoresist was spin coated onto the wafer surface as in Step 11, covering the bumps and the underlying copper traces. This step reinstated the support film removed in Step 15. In practice it would not be necessary to measure the bump height before planarization and therefore Steps 14 and 15 would not normally be required. 16. Planarization was performed with an Anorad diamond-turning machine; the diamond tool consisted of a steel shank on which was mounted a single crystal diamond with a face rounded to 0.75 mm and 0° rake angle. The wafer was mounted on the machine's vacuum chuck, and the diamond tool was set to cut the bump/photoresist composite to a nominal 20 μm above the wafer surface; a spindle speed 3000 rpm and 15 cm/min. feed rate were used. 17. The photoresist was stripped from the wafer. **
18. The heights of the planarized bumps + trace features were measured with respect to the surface of the silicon wafer over short distances in several places using an Alpha-Step 200 surface profilometer. The measured feature heights fell within a range of 19.5 - 20.6 μm, the average being 20.04 μm with a standard deviation of 0.2 μm.
Example 2 After repeating Steps 1 through 14 as described in Example 1, the following sequential steps were carried out: 15. A layer of Ciga-Geigy Probimide™ 412 polyimide was spin- coated onto the surface of the wafer at a spin speed of 600 rpm for 40 seconds and baked at 55 °C for 30 minutes and 110°C for 1 hour, covering the bumps and underlying copper traces.
16. Planarization was performed with an Anorad diamond-turning machine; the diamond tool consisted of a steel shank on which was mounted a single crystal diamond with a face rounded to 0.75 mm and 0° rake angle. The wafer was mounted on the machine's vacuum chuck, and the diamond tool was set to cut the bump/photoresist composite to a nominal 20 μm above the wafer surface; a spindle speed 3000 rpm and 15 cm/min. feed rate were used. 17. The polyimide was stripped using ethanolamine.
18. The heights of the planarized bumps were measured with respect to the surface of the silicon wafer over short distances in several places using an Alpha-Step 200 surface profilometer. The measured feature heights were within a range of 18.6 μm to 20.8 μm with an average height of 20.0 μm and standard deviation of 0.5 μm.

Claims

Claims:
1. A method of preparing an electronic device having a plurality of electrodes for forming electrical connections with another electronic device said method comprising the steps of: positioning metal bumps surrounded by resin on selected ones of said electrodes; diamond turning said bumps and said resin such that each of said bumps has an outer surface, all of said outer surfaces lying substantially in a plane; and removing said resin.
2. The method of Claim 1 wherein said bumps are formed by electroplating.
3. The method of Claim 2 further comprising the steps depositing said resin is as a uniform layer covering said electrodes prior to positioning said metal bumps on said electrodes; and patterning said layer of resin to expose said selected electrodes.
4. The method of Claim 3 wherein said patterning is accomplished by photolithography.
5. The method of Claim 1 wherein said bumps are formed on a temporary substrate and then transferred to said electrodes.
6. The method of Claim 5 wherein said resin is deposited after said bumps have been attached to said electrodes.
7. The method of Claim 1 wherein said metal bumps comprise gold.
8. The method of Claim 1 wherein said metal bumps comprise copper.
9. The method of Claim 8 further comprising the step of applying a layer of gold to said outer surfaces of said metal bumps.
10. The method of Claim 9 wherein said gold is applied after said metal bumps have been diamond turned and before said resin has been removed.
EP93917226A 1992-07-30 1993-07-16 Planarizing bumps for interconnecting matching arrays of electrodes Ceased EP0653105A1 (en)

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JPH07509588A (en) 1995-10-19
WO1994003921A2 (en) 1994-02-17
KR950702746A (en) 1995-07-29
WO1994003921A3 (en) 1994-04-14

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