EP0586558A1

EP0586558A1 - Multichip interconnect module including superconductive materials

Info

Publication number: EP0586558A1
Application number: EP92913021A
Authority: EP
Inventors: Timothy Walton James; Roger James Forse
Original assignee: Superconductor Technologies Inc
Current assignee: Clearday Inc
Priority date: 1991-05-08
Filing date: 1992-05-08
Publication date: 1994-03-16
Also published as: WO1992020108A1; EP0586558A4

Abstract

Un module d'interconnexion multipuce utilise des conducteurs supraconducteurs permettant une vitesse accrue et une dissipation de puissance réduite. Dans un mode de réalisation, des unités conductrices ayant un sens x et un sens y comprennent chacune un substrat (30, 32) présentant des conducteurs supraconducteurs alternés (20) ainsi que des lignes de plan de masse (22). Lesdites lignes de plan de masse (22) sont connectées par des interconnexions (24) analogues à des ponts, et les unités conductrices ayant un sens x et un sens y sont connectées électriquement de manière sélective. Dans un autre mode de réalisation, un agencement multipuce supraconducteur utilise au moins deux structures présentant un substrat (30, 32), un plan de masse (20), un isolant (46) et une structure empilée de conducteurs supraconducteurs (22). Des interconnexions électriques sélectives sont réalisées entre les structures.A multi-chip interconnect module uses superconducting conductors for increased speed and reduced power dissipation. In one embodiment, conductive units having an x direction and a y direction each include a substrate (30, 32) having alternating superconductive conductors (20) as well as ground plane lines (22). Said ground plane lines (22) are connected by bridge-like interconnections (24), and the conductive units having an x direction and a y direction are selectively connected electrically. In another embodiment, a superconducting multi-chip arrangement uses at least two structures having a substrate (30, 32), a ground plane (20), an insulator (46) and a stacked structure of superconductive conductors (22). Selective electrical interconnections are made between the structures.

Description

DESCRIPTION

Multichip Interconnect Module Including Superconductive Materials

Field of the Invention

This invention relates to the manufacture of useful devices from high-temperature superconducting thin films.

More particularly, the invention relates to the use of superconductive thin films to form multichip interconnect modules.

Background of the Invention

Multichip interconnect modules are devices for providing electrical connection between a number of integrated circuit chips. Most currently available multichip interconnect modules utilize electrical interconnects which have non-zero resistance. Typically, a multilayer structure is utilized in which electrical interconnections run in various directions at different levels to provide sufficient connection between the chips. In one structure utilized by the prior art, known as the N-chip process, a silicon substrate utilizes aluminum interconnections with a silicon dioxide (Si0₂) dielectric. Structurally, this microstrip wave guide structure consists of parallel aluminum interconnections separated by a Si0₂ dielectric, with the wave guide being disposed on a silicon substrate. In some devices, the amount of Si0₂ is reduced in order to reduce the overall dielectric constant of the device. It is expected that integrated circuit chips in the future may have an increased number of input/output pins or pads on them. It is further expected that the packing density of chips in multichip modules will increase. These two requirements will, in turn, require more complex interconnection boards as the number of possible points of interconnection increase. If electrical interconnections in multichip interconnect modules have non-zero resis¬ tance, increasing the number of interconnections will necessarily result in increased resistive heat generation in the module. This in turn will require more interconnect layers to avoid overheating by the resistive heating. This trend has the further disadvantage of requiring more power to drive the multichip interconnect module, and will result in slower devices as the length of propagation through multiple interconnect layers increases. In contrast with the foreseeable trend towards slower speeds in conventional resistive multichip interconnect modules, the clear trend in integrated circuit devices is towards faster devices. Accordingly, utilizing conventional resistive multichip interconnect module structures will fail to serve the future needs of high speed integrated circuit devices.

Starting in early 1986, with the announcement of a superconducting material having a critical temperature of 30°K, materials having successively higher transition temperatures have been announced. Currently, supercon¬ ducting materials exist which have critical temperatures well in excess of the boiling point of liquid nitrogen, a relatively inexpensive and simple to use coolant.

Initially, compounds which exhibited relatively high temperature superconductivity were based on the combina¬ tion of rare earth metals, such as barium and yttrium, and alkaline earth metals in conjunction with copper oxides, typically referred to YBCO compounds. Subsequently, compounds containing bismuth were discovered, some of which manifested higher transition temperatures than the YBCO compounds. Starting in early 1988, thallium based superconductors have been prepared, generally where the compositions have various stoichio etries of thallium, calcium, barium, copper and oxygen. To date, the highest transition temperatures for superconductors have been observed in the thallium based superconductors. Thallium containing superconducting films have been successfully grown on a variety of substrates such as lanthanum aluminate, magnesium oxide, yttria stabilized zirconia and sapphire, with the films being epitaxial in the first three cases. Widely recognized benefits of superconducting materials are their essentially zero resistance to electrical current flow, which in turn means virtually zero resistive power losses. Additionally, transmission speeds through superconducting conductors are higher than through resistive materials. There is a general expecta¬ tion that superconducting materials would be useful in connection with high speed computers and electronics. It is further expected that fast integrated circuit devices in the future will operate at low temperatures, on the order of those required for high temperature superconduc¬ tors.

However, use of the conventional multichip interconnect module structure is incompatible with high temperature superconductor materials. One principal problem is that the conventional design requires a relatively low dielectric constant. However, there is currently no known material with a dielectric constant low enough (generally < 5) for use in the conventional multichip interconnect module structure which is also compatible with growth of high quality high temperature superconducting materials. Further, to extend the conventional multichip interconnect module structure to superconductors would require a multilayer structure of superconductor/dielectric/superconductor, in which the bottom layer superconductor was patterned. Further, the interconnect layers would need to be epitaxial to one an other. Various multilayer structures have been reported in the art wherein one or more layers of superconductor are disposed upon one or more layers of substrate. See e.g. U. Poppe, et al, Epitaxial Multilayers of YBa₂Cu₃0₇ and

TlBa₂Cu₃0₇ as a Possible Basis For Superconducting Electron- ic Devices, Solid State Communications, Vol. 71, No. 7, pages 569-572, 1989.

Recent significant advances have been made in fabricating useful devices from superconducting thin films. Of particular importance here is the development by workers at applicant's assignee of a structure useful for transmission of high frequency signals. Particularly, a superconducting ground plane arrangement provides for wide bandwidth transmission of electrical signals. In one embodiment, a conductor is patterned from an epitaxial superconducting film on a substrate, with a ground plane which is formed coplanar with the conductor, and patterned from the same epitaxial superconducting film. The coplanar ground plane is further provided with electrical interconnections between various portions of the coplanar ground plane to assure maintenance of a true ground potential. A detailed disclosure of this structure is found in the application entitled Superconducting Delay Line, Serial No. 07/697,933 assigned to the common assign- ee of these applications, filed on the same date as this application. That application is incorporated herein by reference.

Significant process developments have been made which facilitate construction of useful devices from superconducting thin films. Of particular importance here are two developments by applicants assignee. First, a technique for providing good mechanical and electrical contact between metallization contacts and superconducting thin films is described in an application entitled Fabrication Process for Low Loss Metallizations On Superconducting Thin Film Devices Serial No. 07/697,960, filed on the same day as this application. Briefly, metallization contacts are successfully formed by deposi¬ tion of the metal on the cleaned superconducting material prior to its contamination with any photolithographic mask material or the like. The metallization material may be selectively deposited, such as through use of a shadow mask, and subsequently pattern using conventional tech¬ niques, such as photolithographic techniques. Metallization contacts having good mechanical adhesion and electrical properties may be formed utilizing this tech- nique. Second, a passivation coating has been developed which provides protection for the superconducting film from environmental contact, and provides a suitable dielectric material upon which further structure may be constructed. A polyimide material, preferably Proba ide 412™, has proved particularly useful for these purposes. A detailed disclosure of this coating is described in copending application entitled Passivation Coating for Superconducting Film Device Serial No. 07/697,660, filed on the same day as this application. Both of these applications are incorporated herein by reference.

Summary of the Invention

A hybrid multichip interconnect module successfully utilizes superconducting conductors. In this way, multiple interconnections may be made between a plurality of integrated circuit chips.

In one embodiment, two single layer epitaxial superconducting films are hybridized to create a multichip module having x-direction and y-direction interconnects. A coplanar wave guide structure is used in which the conductors alternate with coplanar ground plane strips. Metallized interconnections between portions of the ground plane may be formed over the conductors. Optionally, contact to the integrated circuit chip may be made through interconnect vias. Acceptable signal propagation speed is achieved through use of the coplanar ground plane arrangement.

In another embodiment, a plurality of trilayer films arranged in a microstrip arrangement are hybridized. Each trilayer film consists of a stacked arrangement of a superconductor, a dielectric and another superconductor disposed upon a substrate. The superconductor furthest from the substrate is patterned to provide a plurality of conductors. Acceptable propagation speed is achieved through use of a microstrip geometry. Preferably, the effective dielectric constant is lowered by removing dielectric from between the superconducting elements.

A principal object of this invention is to provide a superconducting multichip interconnect module.

It is yet a further object of this invention to provide a novel structure for a hybrid multichip interconnect module.

It is yet another object of this invention to provide a structure which successfully solves the problem of obtaining a sufficiently low dielectric constant, while permitting use of epitaxial superconducting films.

Brief Description of the Drawings

Fig. 1 is a plan view of a coplanar hybrid high temperature superconductor multichip interconnect module.

Fig. 2 is a cross-sectional view of Fig. 1 along A-A^«. Fig. 3 is a cross-sectional view of Fig. 1 along B-B*.

Fig. 4 is a plan view of a trilayer hybrid high temperature superconductor multichip interconnect module. Fig. 5 is a cross-sectional view of Fig. 4 along A-A¹.

Fig. 6 is a cross-sectional view of Fig. 4 along B-B¹.

Detailed Description

Figs. 1-3 show one embodiment of a coplanar hybrid high temperature superconductor multichip interconnect module. Fig. 1 shows a plan view of the electrical conductors which would be formed above a substrate (not shown) . Conductors 20 alternate with ground plane strips 22 to form a coplanar ground plane transmission arrangement. The ground plane lines 22 are preferably interconnected by conductive ground plane interconnects 24. Contact portions 26 provide mechanical and electrical contact between the interconnects 24 and the ground plane lines 22. The details of the interconnect structure and the preferred method of manufacturing them is provided in co-pending application entitled Fabrication Process For Low Loss Metallizations On Superconducting Thin Film Devices Serial No. 07/697,960, incorporated herein by reference. In the preferred embodiment of the hybrid multichip interconnect module, two structures such as shown in Fig. 1 would be combined. Typically, the structures would be mounted with their conductors in opposition to the conductors for the second set. The conductors 20 and ground plane strips 22 are preferably formed of the same epitaxial high temperature superconductor formed on a substrate. It is currently possible to form epitaxial films from high temperature superconducting materials, such as the YBCO compounds as well as thallium superconductors. These films are desirable as they have critical temperatures T_c which are higher than the boiling point of liquid nitrogen, thereby reducing the difficulty and expense of cooling the device to superconducting temperatures. The conductors 20 and ground plane lines 22 may be patterned with any conventional technique, such as lithography techniques utilizing a photo mask followed by an etching step. The structure of this invention is consistent with patterning of any size line width for the conductors 20 and ground plane lines 22. Generally, it is desirable to have smaller conductors 20 and ground plane lines 22, so as to permit a higher density of interconnect lines for a given area. As technology permits the patterning of lines having a smaller pitch, the structure of this invention may be utilized to provide acceptable interconnects with higher packing density.

The hybrid multichip interconnect module is arranged with the x-direction and y-direction conductors orthoganol. As shown in Fig. 2, the conductors 20 and ground plane lines 22 associated with substrate 30 are preferably orthoganol to the conductor 20 and ground plane lines 22 (not shown) associated with substrate 32. Since Fig. 2 is a cross-section of Fig. 1 on line A-A¹ the conductor 20 associated with the upper substrate 32 is shown having a portion removed. Interconnections between the x-conductors and the y-conductors is preferably accomplished by an indium bump technique. In this technique, indium bumps 34 are placed on the conductors 20 for each of the x-conductors and y- conductors to be interconnected. The two portions of the modules are aligned and compressed, matching the arrays of bumps on each circuit. Connection may be made from a chip 40 via a solder ball 42 through a die via 44 to connect with a y-conductor 20. The conductor 20 may then optionally connect to an x-conductor by the above described indium bump technique. The substrate dielectric material is optionally removed between the conductors and ground plane lines 22. In the preferred embodiment, a trench structure is used, being formed by any known technique such as trench etching or ion milling. Removal of the dielectric reduces the effective dielectric constant. In the preferred embodiment, a passivation layer 46 is disposed over the surface of the substrate, conductors 20 and ground plane lines 22. The dielectric constant with the trenches and with a passivation layer 46 comprised of a polyimide is less than 9, and is preferably on the order of 6. A detailed description of the preferred passivation coating may be found in copending application entitled Passivation Coating for Superconducting Thin Film Device, filed on the same date as this application, and assigned to the common ass.ignee of this application, incorporated by reference. Formation of the vias 44 may be performed by any technique compatible with the pitch size of the structure. Typically, a wet etch process will limit the pitch to the thickness of the substrate, which may be on the order of 50 to 100 microns. Dry etch processes are useful for smaller pitch structures. Reactive ion etching techniques are particularly useful as etching may be done at angles other than normal. Similarly, laser drilling techniques may be utilized to form die vias.

A trilayer hybrid high temperature superconducting multichip interconnect module structure is shown in Figs. 4-6. Generally, a microstrip structure comprising two conductors separated by a dielectric is utilized for electrical signal transmission. An x-direction structure 52 disposed on a substrate 54 is hybridized with a y- direction unit 56 disposed upon a substrate 58. Typically, the x-direction unit 52 is arranged orthoganolly to the y-direction unit 56. Structurally, the x-direction unit 52 and the y-direction unit 56 are similar.

As shown in Fig. 5, a trilayer structure is disposed on the substrate 54, having a superconductor ground plane 60, dielectric material 62 and patterned conductors 50. In this embodiment, the conductors 50 may be adjacent one another, without the need for intervening ground plane lines as is the case described above for the coplanar ground plane arrangement. As shown in plan view in Fig. 4, the conductors 50 are preferably parallel to one another, with separations in conductors adjacent the location where interconnects 70 are made.

Again, the dielectric material 62 between adjacent conductors 50 is preferably removed in order to reduce the dielectric constant. Similarly, a passivation coating 72, such as a polyimide coating, is disposed over the conductors 50 and dielectric layers 62, to provide environmental protection . Die vias 74 may be made utilizing the techniques described above in connection with the coplanar arrangement.

Though the invention has been described with respect to specific preferred embodiments, many variations and modifications may become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.

Claims

Claims:

1. A superconducting hybrid multichip interconnect module comprising: first and second modules, each module including; a substrate, superconducting conductors supported on the substrate, superconducting ground plane lines supported on the substrate, wherein the first and second modules are arranged with their conductors in facing opposition, and providing selective electrical interconnection between the conductors of the first module and the conductors of the second module.

2. The superconducting hybrid multichip intercon¬ nect module of claim 1 further including in each module: electrical interconnects between the ground plane lines.

3. The superconducting hybrid multichip intercon- nect module of claim 2 wherein the electrical intercon¬ nects are gold.

4. The superconducting hybrid multichip intercon¬ nect module of claim 1 wherein a passivation coating is disposed substantially over the substrate and conductors.

5. The superconducting hybrid multichip intercon¬ nect module of claim 2 wherein a portion of the electrical interconnects are disposed above a passivation coating.

6. The superconducting hybrid multichip intercon¬ nect module of claim 4 wherein the passivation coating includes a polyimide.

7. The superconducting hybrid multichip intercon¬ nect module of claim 1 wherein the conductors and ground plane lines alternate.

8. The superconducting hybrid multichip intercon- nect module of claim 1 wherein the substrate is lanthanium aluminate.

9. The superconducting hybrid multichip intercon¬ nect module of claim 1 wherein the superconducting conduc¬ tor is a thallium containing ceramic copper oxide super- conductor.

10. The superconducting hybrid multichip intercon¬ nect module of claim 9 wherein the thallium containing superconductor is in the 2122 phase.

11. The superconducting hybrid multichip intercon- nect module of claim 1 wherein the superconducting conduc¬ tor is a YBCO superconductor.

12. The superconducting hybrid multichip intercon¬ nect module of claim 1 wherein the substrate portions are removed between the superconducting conductors and superconducting ground plane lines.

13. The superconducting hybrid multichip intercon¬ nect module of claim 1 wherein the die vias are formed through a substrate of a module.

14. A superconducting hybrid multichip interconnect module comprising: two or more superconducting microstrip units, each unit including: a substrate, a superconducting ground plane on the substrate, a dielectric disposed on the superconducting ground plane, superconducting conductors on the dielectric, and selectively placable electrical connections between one microstrip unit and another microstrip unit.

15. The superconducting hybrid multichip intercon¬ nect module of claim 14 wherein a passivation coating is disposed substantially over the substrate and superconducting conductors on the dielectric.

16. The superconducting hybrid multichip intercon¬ nect module of claim 15 wherein the passivation coating includes a polyimide.

17. The superconducting hybrid multichip intercon¬ nect module of claim 14 wherein the substrate is lanthanium aluminate.

18. The superconducting hybrid multichip intercon¬ nect module of claim 14 wherein the superconducting conductor is a thallium containing ceramic copper oxide superconductor.

19. The superconducting hybrid multichip intercon¬ nect module of claim 18 wherein the thallium containing superconductor is in the 2122 phase.

20. The superconducting hybrid multichip intercon¬ nect module of claim 14 wherein the superconducting conductor is a YBCO superconductor.

21. The superconducting hybrid multichip intercon¬ nect module of claim 14 wherein die vias are formed through a substrate of a unit.