EP0438469A1

EP0438469A1 - Circuit arrangement for digitally recording analog information formed by the time interval between two consecutive states of a signal.

Info

Publication number: EP0438469A1
Application number: EP89911553A
Authority: EP
Inventors: Horst Ziegler; Gerald Riemer
Original assignee: Individual
Current assignee: Individual
Priority date: 1988-10-13
Filing date: 1989-10-12
Publication date: 1991-07-31
Anticipated expiration: 2009-10-12
Also published as: EP0438469B1; DE58901716D1; WO1990004219A1; DE3834938C1

Abstract

Circuit permettant l'enregistrement numérique d'une information analogique, notamment de l'intervalle entre deux états consécutifs d'au moins un signal ou de l'amplitude dudit signal. Ledit circuit comporte un condensateur d'intégration (23), qui est chargé pendant une phase de charge à une tension Uc1, représentant l'information analogique, par l'intermédiaire d'un circuit parallèle comprenant une première résistance (13) et une deuxième résistance (17). A la fin de cette phase de charge, un premier commutateur (15), lequel est commandé par un dispositif de commande (9) et relié en série à la première résistance (13), interrompt le passage du courant à travers la première résistance (13), de sorte que pendant la phase de modification de charge qui s'ensuit, le condensateur d'intégration (23) n'est chargé que par l'intermédiaire de la deuxième résistance (17) jusqu'à ce que la tension Uc du condensateur atteigne une valeur seuil prédéterminée Uc2 contrôlée par un comparateur (5). La deuxième résistance (17) présente une valeur R2 supérieure à la première résistance (13), de sorte que la constante de temps de charge (tau2) pendant la phase de modification de charge est supérieure à la constante de temps de charge tau1 pendant la phase de charge. Pendant la phase de modification de charge, laquelle est généralement plus longue que la phase de charge, un compteur (7) compte les impulsions périodiques de synchronisation d'un signal de synchronisation de référence. A la fin de la phase de modification de charge, le résultat indiqué par le compteur (7) est lu et traité ultérieurement par un dispositif d'évaluation en vue de l'obtention d'une valeur numérique pour l'information analogique.Circuit allowing the digital recording of analog information, in particular of the interval between two consecutive states of at least one signal or of the amplitude of said signal. Said circuit comprises an integration capacitor (23), which is charged during a charging phase at a voltage Uc1, representing the analog information, by means of a parallel circuit comprising a first resistor (13) and a second resistance (17). At the end of this charging phase, a first switch (15), which is controlled by a control device (9) and connected in series to the first resistor (13), interrupts the flow of current through the first resistor ( 13), so that during the subsequent charge change phase, the integrating capacitor (23) is charged only through the second resistor (17) until the voltage Uc of the capacitor reaches a predetermined threshold value Uc2 controlled by a comparator (5). The second resistor (17) has a higher R2 value than the first resistor (13), so that the charging time constant (tau2) during the load change phase is greater than the charging time constant tau1 during the charging phase. During the load change phase, which is generally longer than the load phase, a counter (7) counts the periodic synchronization pulses of a reference synchronization signal. At the end of the load modification phase, the result indicated by the counter (7) is read and subsequently processed by an evaluation device with a view to obtaining a digital value for the analog information.

Description

Circuit arrangement • for digital acquisition of analog information, in particular the time interval between two successive states of a signal.

description

The invention relates to a circuit arrangement for the digital acquisition of analog information, in particular the time interval between two successive states of at least one signal or the amplitude of the signal, according to the preamble of claim 1.

A circuit arrangement for the detection of time intervals, in particular for the measurement of small time intervals in the submillisecond range, which cannot be determined with conventional digital time interval measuring devices or only with insufficient resolution, comprises an integration capacitor which has a Charging circuit can be charged to a voltage representing the analog information, and a charge change circuit which changes the voltage of the integration capacitor at a rate of change less than that of the charging circuit. A comparator compares the voltage on the integration capacitor with a predetermined threshold. Furthermore, a counter is provided, which counts periodic clock pulses during the change in the voltage of the integration capacitor by means of the charge change circuit until the predetermined threshold value is reached.

After the integration capacitor has been charged to a voltage representing the analog information via the charging circuit, the charge change circuit changes the voltage at the integration capacitor until the threshold value monitored by the comparator is reached. The duration of this voltage change of the integration capacitor by means of the charge change circuit depends on the one hand on predetermined parameters of the circuit arrangement and on the other hand on the value of the integration capacitor voltage representing the analog information. After the voltage change at the integration capacitor has expired, the counter result of the counter represents digital information about the duration of the voltage change and thus also about the value of the analog information.

In the conventional digital measurement of time intervals on the basis of the counting of flanks of periodic clock pulses of a reference clock signal of known duration, the problem arises that the beginning or the end of the time interval generally does not coincide with an edge of the reference clock signal. The time interval between the start of the measurement time interval and the occurrence of the first one The edge of the reference clock signal which triggers the count event is not correctly recorded, since no complete reference clock period is not required for this time interval. A corresponding situation arises at the end of the measuring time interval. The resulting error in the digital measurement result is referred to as +/- 1 digitization uncertainty. The + / 1 digitization uncertainty limits the relative resolution of a time interval measurement, the greater the ratio of the period of the reference clock signal to the duration of the time interval to be measured. A high reference clock frequency is therefore necessary to achieve a high resolution of a conventional time interval measurement. A reference clock signal with a very high constant frequency, however, requires complex oscillator circuits and is susceptible to interference.

One possibility of improving the resolution in the time interval measurement without increasing the reference clock frequency is to determine the time intervals at the beginning and at the end of the measurement time interval, which cannot be precisely determined due to the asynchronism of the measurement and reference clock signals, with a circuit arrangement of the type described above.

Such an application of a circuit arrangement for digitally recording the time interval between two successive states of at least one signal is known from the magazine "Elektronik" volume 7-1988, number 14 pages 65 to 68. The known circuit arrangement works as an analog interpolator of a time interval measuring system and detects the time interval T .. between the beginning of a time interval T to be measured and a subsequent predetermined edge of a periodic reference clock signal. Another analog interpolator detects the time interval T_. between the End of the time interval to be measured and a subsequent predetermined edge of the reference clock signal. The edges of the predetermined Referenz¬ above taktsig ^J Nals include a time interval Tm, which

Length corresponds to an integer multiple of the period of the reference clock signal and thus by

Counting of the clock periods falling in this clock-synchronous time interval can be exactly determined with a counting device. From the information about the time periods / _n 1, T.1 determined with the analog interpolators and the counting device. and Tm calculates an off

Value device a digital measured value for the measurement time interval Tx to be determined, thereby making a high

Time resolution is achieved. The known circuit device comprises an integration capacitor arranged in an integrator circuit, a charging circuit for charging the integration capacitor with a constant current of a first charge source during the time interval T or T_ to be detected. , a charge change circuit for discharging the integration capacitor with the current of a second charge source, and a comparator which compares the voltage at the capacitor with a threshold value corresponding to the discharge state of the capacitor. The first and second charge sources have opposite polarities. The first charge source delivers a constant current that is a thousand times greater than the constant current of the second charge source. The voltage changes at the integration capacitor during the charging and discharging phase are linear, but with different signs. During the discharge phase, a counter counts periodic clock pulses of the reference clock signal. After the discharge phase has elapsed, the counting result of the counter represents information about the time interval T. or T .. to be recorded. The known circuit arrangement has in particular the disadvantage that charge sources with opposite polarity are required for charging and discharging the integration capacitor. In addition, the comparator requires a negative DC voltage to set the threshold value ÖV. Good constancy is required for the charging current and the discharging current. In the event of fluctuations in the charging current, the integration capacitor voltage represents the time interval to be detected only incorrectly after the charging phase has expired, while fluctuations in the discharge current have a disruptive influence on the discharge time and thus on the counting result of the counter. The required stabilization of the currents of different signs to respectively predetermined values, which also differ significantly, is associated with a high circuit complexity, which makes the circuit arrangement complicated and expensive. In order to achieve a high measuring accuracy of the known analog interpolator, a complex statistical calibration is necessary to determine the ratio of charging current to discharging current after each measuring process. Each of the interpolators is calibrated with the aid of reference pulses, which are fed to the inputs of the interpolators via a precision phase shifter. In addition to additional circuitry, this calibration method requires a comparatively large computing effort by the evaluation device.

From the specialist book: semiconductor circuit technology, author: Tietze-Schenk, third edition, Springer-Verlag, Heidelberg New York 1980, page 662, a circuit arrangement for digitally detecting the voltage amplitude of an analog signal is known. This known circuit arrangement works according to the "dual-slope" analog-digital converter method and comprises one Integration capacitor in an integrator circuit with operational amplifier. The input of the integrator circuit is electrically connected to the signal source via a charging circuit during a predetermined integration time interval, as a result of which the integration capacitor is charged to a voltage proportional to the signal voltage to be measured. After the integration time interval has expired, the input of the integrator circuit is connected to a reference voltage source with a constant reference voltage in order to discharge the integration capacitor. The capacitor voltage changes linearly with time. During the discharge process, a counter counts periodic clock pulses from a reference clock source. A comparator ends the counting process when the voltage on the capacitor has dropped to the value OV. After the discharge phase has expired, the counting result of the counter represents digital information about the signal voltage to be measured.

A disadvantage of this known analog-digital converter is that a very good constant reference voltage is required for the controlled discharge process of the integration capacitor and thus for a high accuracy of the voltage measurement, the sign of which is opposite to the sign of the measuring voltage. The known circuit arrangement therefore requires at least one positive and one negative voltage source, each with a very good constant output voltage, and a switching device which reverses the polarity of the reference voltage.

The invention is based on the object of specifying a circuit arrangement for the digital detection of analog information, in particular the time interval between two successive states of at least one signal or the amplitude of the signal, the circuit complexity and susceptibility to interference of which is low. This object is achieved in that the charging circuit and the charge change circuit change the voltage of the integration capacitor in the same direction and are connected to a common charge source.

The circuit arrangement according to the invention can be implemented with little circuit complexity and is almost insensitive to faults. In particular, only one charge source, for example a DC voltage source, is required to operate the circuit. Another advantage is that the circuit arrangement can be constructed from comparatively inexpensive components without reducing its reliability.

A further development of the invention for digitally recording the time interval between two successive states of at least one signal, according to claim 2, ensures that the charging circuit is only activated during the time interval to be detected, in order to set the integration capacitor to a voltage representing the time interval to be measured to load. Furthermore, it is ensured that the voltage change of the integration capacitor takes place immediately after the time interval to be detected by means of the charge change circuit, whereby the voltage at the integration capacitor representing the time interval can be evaluated in a fail-safe and comparatively fast manner without being falsified by leakage currents.

According to the development of the invention according to claim 3, different signal states of a signal can be selected as delimitation marks of a time interval to be measured. The signal states can be, for example, rising or falling edges of a measurement signal. According to the development of the invention according to claim 4, time intervals between signal states of signals from different sources can be recorded.

By using a DC voltage source as a charge source, in particular a DC supply voltage source of the circuit arrangement, the circuit outlay for power supply is kept to a minimum.

The development of the invention according to claim 6 for measuring the amplitude of the signal ensures a constant integration time interval for charging the integration capacitor to a voltage representing the amplitude of the analog signal. By counting periodic clock pulses that fall in the charge change phase that follows the integration time interval, digital information about the analog signal voltage to be detected is obtained.

A sample and hold circuit for temporarily storing signal amplitude values enables the digital detection of amplitude values of time-varying signals.

The charging circuit can be easily implemented by setting a first resistance value and the charge change circuit by setting a second resistance value of the resistance circuit according to claim 8, the charge and charge change circuit making do with a common charge source.

Claim 9 specifies a very simple possibility for changing the resistance value of the resistance circuit. A particular advantage of the resistance circuit according to claim 9 is that the charge flow to the capacitor during the charging phase and during the Charge change phase essentially depends on passive components which are susceptible to faults, namely ohmic resistors. The proposed resistance circuit, with a very simple structure, ensures that the analog information is recorded almost without interference. In addition, resistors with high precision, temperature independence and long-term stability of their resistance values can be produced with the technologies available today without difficulty and at the same time at low cost, which contributes to the inexpensive implementation of the circuit arrangement.

Due to the fact that the second resistance of the resistance circuit according to claim 9 has a substantially higher resistance value than the first resistance, the rate of change of the voltage of the integration capacitor during the voltage change by means of the charge change circuit is significantly smaller than the rate of change of the voltage change on the integration capacitor the charging phase by means of the charging circuit. This is particularly important if time intervals are to be recorded digitally which are approximately the same length or shorter than the period of the periodic clock signal ε. The duration of the charge change phase, which is dependent on the duration of the charge phase, can always be selected by selecting the resistance ratio of the first and second resistors so long that several periodic clock pulses occur during the charge change phase, so that counting these clock pulses provides digital information about the duration of the Loading phase is obtained.

In accordance with the development of the invention according to claim 11, the integration capacitor can be short-circuited by a second switch of the control device in order to establish the initial conditions for a new measuring process. Exemplary embodiments of the invention are shown in the drawings and are described in more detail below.

Show it

1 shows a schematic representation of a circuit arrangement according to the invention for digitally detecting a time interval between successive states of at least one signal,

2 is a signal flow diagram to explain the operation of the circuit arrangement of FIG. 1,

3 shows a schematic illustration of a time interval measuring device with an exemplary embodiment of the invention,

4 and FIG. 4a a signal flow diagram to explain the mode of operation of the time interval measuring device according to FIGS. 3 and

5 shows a schematic illustration of an exemplary embodiment of the invention for digitally detecting the amplitude of a signal.

The circuit arrangement designated by 1 in FIG. 1 comprises an analog circuit part 3, a comparator 5, a counter 7 and a control device 9. The analog circuit part 3 comprises a resistance circuit 11 connected to the positive pole 6 of a positive direct voltage source with a first resistor 13 in series with a first switch 15 in a first branch 16 and with a second resistor 17 in parallel with the first resistor 13 and the first Switch 15 in a second branch 18, further in series with the resistance circuit 11, a parallel circuit 21 connected to the reference potential 19 (ground) of the DC voltage source, comprising an integration capacitor 23 in a third branch 25 and a second switch 27 in a fourth branch 29.

The first switch 15 and the second switch 27 are controlled by the control device 9 and, depending on the switching state, switch a current through the first branch 16 or through the fourth branch 29 on or off. An input 31 of the comparator 5 is electrically connected to a first terminal 33 of the integration capacitor 23. The comparator 5 compares the voltage U at the integration capacitor 23 with a predetermined threshold value U, and changes the state of its comparator output signal when the capacitor voltage ü reaches the threshold value u ~. An output 35 of the comparator 5 carrying the comparator output signal is electrically connected to an input 37 of the control device 9. A signal state detector 8 of the control device 9 detects predetermined successive state changes of at least one measurement signal, for example the positive and negative flank of a rectangular pulse of a measurement signal, and the control device 9 controls the first switch 15 or second switch 27 depending on the occurrence of the predetermined state changes at least one measurement signal or depending on the occurrence of a change in state of the comparator output signal. The control device 9 is also electrically connected to a counting input 39 of the counter 7 in order to switch the counter readiness of the counter 7 on or off as a function of the occurrence of a predetermined change in state of at least one measurement signal or the comparator output signal. When switched on The counter counts 7 clock pulses of a periodic clock signal Tref constant clock period Tclk readiness for counting.

Using an example of a pulse length measurement with the exemplary embodiment of the invention, the time sequence of various steps in the digital detection of the time interval T .. between the positive and the subsequent negative flank of a rectangular signal pulse P is described below. For this purpose, reference is made to FIGS. 1 and 2. Before the occurrence of the pulse P, the second switch 27 is switched on and thus the integration capacitor 23 is short-circuited and discharged via the fourth branch 29 (initial state of the circuit). When the positive edge A .. of the rectangular pulse P occurs, the signal state detector 8 of the control device 9 detects the positive edge A. as the start signal of a measurement, and the control device 9 simultaneously switches off the second switch 27 by outputting a control signal, so that no current can flow past the integration capacitor 23 via the fourth branch 29. Thus, a charging phase for charging the integration capacitor 23 is based on a voltage U _ representing the time interval T .. between the pulse edges A .., A_ of the rectangular pulse P. on. During the charging phase, the first switch 15 is switched on, so that the integration capacitor 23 is charged via the first and second resistors 13, 17. In the configuration that the first switch 15 is switched on and the second switch 2.7 is switched off, the analog circuit 3 operates as a charging circuit 3 'with a charging time constant L. .

When the negative edge A _{2 of} the rectangular pulse P occurs, the signal state detector 8 of the control device 9 detects the negative edge A, as a stop signal for the charging phase, and the control device 9 ends the charging phase by switching off the first switch 15 Control device 9 with At the end of the charging phase, a signal is sent to the counter 7 in order to switch on the readiness of the counter 7 so that it counts clock pulses of the periodic clock signal Tref. Immediately after the charging phase is a charge change phase ΔT, in which the integration capacitor 23 is only charged via the second resistor 17. In the configuration present during the charge change phase ΔT, that the first and second switches 15, 27 are switched off, the analog circuit 3 works as a charge change circuit 3 "for changing the voltage U on the integration capacitor 23 until the comparator 5 reaches it monitored threshold value U - • ^D i ^e charging time constant ⁽ - 2 of the charge change circuit is significantly greater than the charge time constant i 1 of the charging circuit, so that the voltage U at the integrating capacitor 23 during the charge change phase ΔT with a significantly smaller rate of change than during the charging phase T .. The time constant T of the charge change circuit is greater than the time constant -1 of the charge circuit, since the total resistance of the resistance circuit 11 is greater during the charge change phase (charging of the integration capacitor 23 via the second resistor 17) than during that Charging phase (L charge of the integration capacitor 23 via a parallel connection of the first and second resistor 13, 17).

Charge and charge change circuit 3 ', 3 "change the voltage U at the integration capacitor 23 in the same direction. When the voltage U at the integration capacitor 23 reaches the predetermined threshold value u_, the comparator 5 changes the state of the comparator output signal, whereupon the control device 9 switches off the readiness of the counter 7 and switches on the second switch 27. The integration con- The capacitor 23 is then short-circuited and discharged via the second switch 27, as a result of which the circuit arrangement according to the invention is reset to its initial state. The counting result X of the counter 7 (not shown) after the Ladungsänderungεphaεe by an evaluation read and evaluated as digital information for calculating a measured value for the time interval T .. between the edges A _1, A, of the measurement signal.

The essential working principle of the exemplary embodiment of the invention has been described above with reference to the explanation of a pulse length measurement. However, the exemplary embodiment is not limited to the measurement of rectangular pulse durations.

The signal state detector 8 of the control device 9 can optionally also react to other predetermined signal states than those described above. In particular, the signal states for starting and stopping the charging phase of the integration capacitor and thus the measuring time interval can originate from different signal sources.

The circuit arrangement according to the invention is able to carry out self-calibration measurements. Before the start of the calibration measurement, the first switch 15 is switched off and the second switch 27 is switched on (initial switching state), so that the integration capacitor 23 is discharged. The control device 9 starts the calibration measurement by switching off the second switch 27 and switching on the readiness for counting of the counter 7. The integration capacitor 23 is then only charged via the second resistor 17 from its discharge state until the threshold value U_ _* £ is reached. When the threshold is reached The comparator 5 changes the state of its output signal, whereupon the control device 9 ends the calibration measurement by switching off the readiness of the counter 7 and switching on the second switch 27. During the calibration measurement, the counter 7 counts the clock pulses of the periodic clock signal Tref. After the calibration measurement, the evaluation result XT of the counter 7 is read out by the evaluation device and buffered. This counting result XT of the calibration measurement is included by the evaluation device in the evaluation of one or more time intervals T. to be measured.

In the following, mathematical foundations for the determination of a sought time interval T between successive states of at least one signal are presented.

At the end of the charging phase, the voltage U at the integration capacitor 23 has the value described by equation (1) below:

where U is the voltage of the direct voltage source,

T .. the duration of the charging phase and f ", the time constant of the charging circuit 3 *.

The time constant T \ of the charging circuit 3a can be determined by the relationship:

T _χ = C R- _^ R ₂ / (R ₁ + R ₂ ) (2)

describe in which R .. or R_ denotes the resistance value of the first or second resistor 13, 17 and C the capacitance of the integration capacitor 23. The duration ΔT of the charge change phase can be described by the following equation (3):

ΔT - T ₂ m (<u _o - u _cl ) / (u _o - u _c2 )) (3),

wherein

£ -. = R_. C denotes the charging time constant of the charge change circuit and U “denotes the threshold value of the integration capacitor voltage monitored by the comparator 5.

Solving equation (3) according to U leads to:

U Cl = DO - (üO - UC) exp ^~~ (Δτ / r, 2) (4)

Equating equations (1) and (4) and resolving the result according to T ₁ leads to a mathematical description of the duration of the charging phase or the time interval to be recorded between two successive states, which is independent of the unknown voltage U, at least of a signal:

l ^{= "R} l ^R ₂ ^{C / (R} 1 ^{+ R} 2> ^{ln ((U} o ^{" U} c2 ^{) U} o ⁾

- I ^ / CEt _j + R ₂ ) X Tclk (5)

In equation (5) the time constants L, and T are expressed by the resistance values R, and R ₂ and by the capacitance C of the integration capacitor 23. The symbol ΔT for the duration of the charge change phase in equation (5) has been replaced by the equivalent expression: X Tclk. X denotes the counting result of the counter 7 after the charge change phase has ended and Tclk the period of the periodic clock signal Tref. With equation (5) the time interval T to be determined from the counting result X and the otherwise known parameters of equation (5).

Equation (5) can be considerably simplified by including the count result XT of a calibration measurement. The voltage change U of the integration capacitor 2% from its discharge state to reaching the threshold value U takes place during a calibration measurement in the time T, which can be described by the product of the count result XT and the period Tclk of the periodic clock signal Tref:

T ₃ = XT ^• Tclk (6)

Using equation (6) and the exponential charging function of the integration capacitor 23 in accordance with equation (1), the threshold value U is given as a function of the counter reading of a calibration measurement:

^U c2 ^{= U} o ⁽¹ " ^ex P ⁽ - ^χτ - ^τ clk (R ₂ C ⁾ ) ⁾ (7)

Replacing U ₂ in Equation (5) with the expression of the right side of Equation (7) leads to Equation (8):

T _χ = ^R / ^" < ^R ι ^{+ R} 2 - ' ^Tclk '^{(X" X) (8)}

According to equation (8), the evaluation of the counter results X to determine a time interval T. of two successive states of at least one signal is considerably simplified by including the count result XT of a calibration measurement.

In the evaluation equation (8) for the digital acquisition εung of the time interval T. of two successive states of at least one signal, neither the value of the supply voltage U nor the threshold value U _? of the comparator 5, the capacitance value C of the integration capacitor 23. Long-term stability of the above-mentioned variables is therefore not necessary if a time interval measurement or a series of measurements of time interval measurements is carried out with the circuit arrangement according to the invention in each case in connection with a calibration measurement. It is then only necessary to require easy-to-meet short-term stability of the above-mentioned parameters for one measurement process. Expensive precision components with high long-term stability or complex stabilization circuits can therefore be dispensed with. Since the capacitance value C of the integration capacitor 23 is not included in the equation (8), even larger deviations from the nominal capacitance value, for example due to manufacturing tolerances, are irrelevant. The only device parameters included in the evaluation are the resistance values R, and R ₂ and the period Tclk of the clock signal. These values are very easy to determine and have good constancy.

In addition to these very important advantages of the circuit arrangement according to the invention, the calibration measurement is very easy to carry out and, instead of requiring additional computational effort, the computational evaluation for determining a measuring time interval is considerably simplified.

The control device can be made of electronic components known per se, such as flip-flops, digital gates, etc. being constructed.

The DC voltage source is preferably a supply DC voltage source for all components of the switching device, in particular a 5 V DC voltage source. By using only one voltage source for all components of the circuit device according to the invention, the circuit complexity for the power supply is low. MOS field-effect transistors with short switching times are preferably used as the first and second switches 15, 27. The comparator 5 should have an input resistance value that is significantly greater than the resistance values R_. "R" of the first and second resistors 13, 17 in order to keep the load on the analog circuit 3 by the comparator negligible.

In a preferred embodiment, the comparator threshold U _{2 is set} to a value of approximately 2/3 of the supply voltage U of the direct voltage source. It is thereby achieved that the integration capacitor voltage U does not rise during the measurement up to the flat-ended asymptotic range of the exponential charging function. For the detection of small time intervals, the resistance R should be at least a factor of the order of magnitude 100 greater than the resistance value R .. of the first resistor 13, so that the time constant 2 ^" _{2 of} the charge change circuit 3" is also large compared to the time constant T, the charging circuit 3 '.

A time interval measuring device 2 with a circuit arrangement according to the invention for digital detection of a time interval is described below.

With the time interval measuring device 2, for example, time intervals Tx between positive edges A, a measurement signal TCP with several successive pulses P are to be determined (FIG. 4). The ones to be determined Time intervals T are longer than the period Tclk of a reference clock signal Tref, so that several clock pulses of the reference clock signal fall in time in a time interval T _^ . As can be seen from FIG. 4, the length Tx of the time interval to be determined can be determined by the relationship:

to be discribed. In it Tm denotes a time interval which is made up of an integer multiple of the period Tclk of the reference clock signal Tref, T-. the error time interval at the beginning of the measuring time interval T and T, the error time interval at the beginning of the measuring time interval beginning with the next positive edge of the measuring signal TCP. The clock-synchronous time interval Tm is determined by counting the time in the

Time interval T falling reference clock periods determined with a counter 41, whereas the error time intervals T .., T _{1 are} detected with the circuit arrangement la.

In addition to a circuit arrangement according to the invention, the time interval measuring device 2 comprises a counting device 41 and a counter enable circuit 43. The circuit arrangement is constructed essentially like the circuit arrangement 1 of the exemplary embodiment described above. Components already described are identified by the letter a after the reference number. Deviations from the previous exemplary embodiment are explained below.

The counting device 41 comprises a pulse pause counter 45 for counting clock pulses of the reference clock signal Tref during a pulse pause between the pulses P of the measurement signal TCP and a pulse length counter 47 for Counting of clock pulses of the reference clock signal during the duration of a pulse P. Such a counting device 41 with pulse pause and pulse length counters 45, 47 is advantageous if both pulse durations and pulse pauses are longer than the period duration Tclk of the reference clock signal. The advantage is that the pulse length counter 47 or the pulse pause counter 45 can be read out alternately by an evaluation device (not shown), while the other counter 45, 47 counts clock pulses. No very high speed requirements with regard to reading out the counting results of the counters 45, 47 then have to be made to the evaluation device in order to register all counting events or clock pulses of the reference clock signal Tref falling within a time interval T 1.

The measurement signal is present at an input 49 of the control device 9a and at an input 50 of the counter release circuit 43. The counter enable circuit 43 controls the readiness of the counters 45, 47 as a function of the occurrence of pulse edges of the measurement signal TCP.

The periodic reference clock signal Tref is present at the counting inputs of the pulse length counter 47, the pulse interval counter 45 and the counter 7a of the switching device la. Furthermore, the reference clock signal Tref is fed to an input 55 of the control device 9a. A takeover signal of the pulse length counter 47 is fed to a control input 57 of the control device 9a.

If a positive edge A _{+ of the} measurement signal TCP occurs, the first switch 15a of the circuit arrangement la is switched on by the control device 9a and the second switch 27a is switched off. The charging phase thus begins, during which the integration capacitor 23a via the first resistor 13a and via the second resistor. εtand 17a is loaded. When the positive edge A of the measurement signal TCP occurs, the counter enable circuit 43 blocks the readiness for counting of the pulse pause counter 45 and switches on the readiness for counting of the pulse length counter 47. The loading phase of the integration capacitor 23a ends with the occurrence of a first negative edge of the reference clock signal Tref counted by the pulse length counter 47 and corresponds to an error time interval T- to be determined. or T,. When the charging phase T ends, the control device 9a switches the first switch 15a off, so that the integration capacitor 23a is forwarded during the charge change phase ΔT via the second resistor 17α to a voltage threshold value U ₂ monitored by the comparator 5a. The control device 9a monitors the takeover signal from the pulse length counter 47 in order to determine whether the pulse length counter 47 has actually counted the first negative edge of the periodic clock signal Tref after the start of the measuring time interval T ₁ and ends the charging phase T with the occurrence of a negative one Edge of the reference clock signal only when the edge has been registered by the counter 47. During the charge change phase T, the counter 7a counts clock pulses or negative edges of the periodic reference clock signal Tref.

The interaction of the control unit 9a with the counter 7a and the comparator 5a for ending the charge change phase and for controlling the readiness for counting (release) of the counter 7a has already been explained in connection with the previously described exemplary embodiment of the invention.

After the charge change phase has elapsed, the circuit arrangement 1 a is in its initial state and is thus for the detection of a next error time interval T .. or T-. ready. The readiness for counting (release) of the pulse length counter 47 is switched off when a negative edge A_ of the measurement signal TCP occurs and that of the pulse pause counter 45 is switched on. The counting results of the counters 7a, 45 and 47 are each read out by the evaluation device and temporarily stored after the corresponding counter has come to a standstill. The evaluation device calculates a digital value for the measurement time interval Tx to be determined from the temporarily stored count results.

In an advantageous variant of the above-described exemplary embodiment, the counter enable circuit (43) monitors both the measurement signal TCP and the reference signal Tref and switches the readiness for counting of the pulse length counter 47 or the pulse pause counter 45 on or off when the first is positive Edge of the reference signal Tref follows the positive or negative edge A of the measurement signal TCP (FIG. 4a). The negative edge of the reference clock signal Tref which triggers a first count event of the pulse length counter and which simultaneously ends the loading phase T. of the integration capacitor 23a then occurs at the earliest after half a clock period of the reference clock signal Tref has elapsed after the start of the measuring time interval T. The time interval T- or T to be detected with the circuit arrangement la can then be a minimum of half and a maximum of three half period periods Tclk of the reference signal Tref. The problem that a first edge of the reference clock signal Tref to be counted by the pulse length counter 47 follows the positive edge A of the measurement signal ε TCP too closely to be registered by the counter 47 is eliminated in this way. A typical time behavior of the circuit arrangement 1 a is discussed below on the basis of example values for the resistors R 1, R ₂ _ for the capacitance C of the integration capacitor 23a, for the period Tclk of the reference clock signal Tref and for the comparator threshold U.

It is:

U ₂ = 2/3 U, where U denotes the voltage of the DC voltage source.

According to the variant of the time interval measuring device according to the invention mentioned above, the duration of an error time interval T. can be between 100 ns and 300 ns if the reference clock period Tclk = 200 ns is used as a basis. With the above values for R_. , R ₂ and C, the time constant T .. = 813 ns results for the charging circuit 3a '. During the minimum duration of the time interval T .. = 100 ns, the integration capacitor 23a is charged to the voltage U, = 0.11 U with a charging time constant 7 .. = 813 ns. The change in charge circuit 3a "then requires a time of ΔTma ^'x = 98 / S to continue charging the Integ ^J rations¬ kondenεators 23a up to reaching the threshold Komparator¬ 2/3 U. During the charge phase change

ΔTmax = 98 / S, the counter 7a sums up Xmax = 487 counting events. During the maximum duration of the time interval T- = 300 ns, the integration capacitor 23a with the capacitance 1 nF becomes U __. = 0.3 U charged.

The charge change phase then lasts for ΔTmm. = 73 us long. This corresponds to a counter reading of 364 Events of the counter 7a, with a reference clock period of 200 ns.

The evaluation equation for calculating T is based on equation (9).

If in equation (9) T. and T .. are replaced by corresponding expressions of equation (8) and furthermore T by Tclk (V + W), the following results:

T = Tclk ^• (V + W) + R ₁ / (R ₁ + R ₂ ) ^• Tclk • (X ¹ - X) (10)

In it T denotes the measuring time interval to be determined between successive positive edges of the

Measurement signal,

V the count result of the pulse length counter after the pulse duration has expired,

W is the counting result of the pause counter after a

Pulse pause,

X the counting result of the counter lo

Error time interval T ..,

X 'the counting result of the counter 7α after the end of the Flehlleerrzzeeiittiinntteerrvvaallllss TT ₁₁ and TTcclk the period of the periodic clock signal Tref,

Equation (10) is a simple calculation rule for determining the measured value T from the counting results of the pulse length counter 47, the pulse pause counter 45 and the counter 7α of the circuit arrangement la.

Since only the counting results of the counters 7a, 45, 47, the known resistance values R- or R- and the known period duration value Tclk of the periodic clock signal are included in the equation (10), the time interval measurement of successive time intervals with the circuit device la is unnecessary according to the invention even a calibration measurement. In this application example of a circuit arrangement according to the invention, too, there are no high requirements for the short-term stability of the supply voltage U or the comparator threshold U ₂ .

The right side of equation (10) includes the summan Tclk. (V + W), which is measured as an integral multiple of the reference clock period Tclk, and the summand R, / (R, + R ₂ ) .Tclk (X'-X), which measures the detection of the error time intervals T .. or T. , describes. The error time intervals can be represented virtually as a multiple of a "virtual clock period" Tclk, with:

Tclkvirtual = 1 ^ / (1 ^ + R ₂ ) .Tclk (11)

Depending on the resistance values R, and R _2, the error time intervals T .., T. appear divided into substantially smaller time quanta than Tclk, as is illustrated in the example below:

It is:

Tclk = 200 ns, R, = 1 kOhm, R ₂ = 100 kOhm

With these values for the clock period Tclk and for the resistors R,, R ₂ , the error time intervals are scanned with a time pattern of 200 nε / 101, ie the virtual clock period in this example is approximately 2 ns with a real clock period of 200 ns.

From the above considerations it can be seen that with a circuit arrangement according to the invention for the digital detection of time intervals between two the following states of at least one signal, an extremely high-resolution digital time interval measurement is possible, even if the reference clock signal Tref has a period Tclk of only 200 nε. The reference clock signal Tref can originate, for example, from a system clock source which also clocks a microprocessor unit of the evaluation device.

A time interval measuring device with a switching device according to the invention requires only a single supply DC voltage source and also only a single reference clock source.

The form of the measurement signal required for the explanation of the working principle of the time interval measuring device 2 is not mandatory. In this exemplary embodiment of the invention, too, predetermined signal states other than the described delimitation marks of time intervals can be selected.

A further exemplary embodiment of the invention is described below with reference to FIG. 5. This further exemplary embodiment is a circuit arrangement for digitally detecting the amplitude of a signal and comprises an analog circuit part 3b, a comparator 5b, a counter 7b, a control device 9b, also a time control circuit 57 and a sample and hold circuit 59. The essential principle the analog circuit part 3b, the comparator 5b, the counter 7b and the control device 9b can be seen essentially from the description of the previous exemplary embodiments; Deviations from this are described below. The components already described in the preceding exemplary embodiments, those with the same or similar function also in the circuit arrangement 1b for digital detection the amplitude of a signal are used, are marked with a b after the corresponding reference number.

The analog circuit part 3b is connected to a sample-and-hold circuit 59 representing the charge source for the integration capacitor 23b. The sample and hold circuit 59 samples the unknown signal U, e.g. a voltage signal, and outputs a voltage U proportional to a respective current sample or hold value to the analog circuit 3b. The timing control circuit 57 is clocked with the reference clock signal Tref and outputs a timing control signal with signal edges successive at a predetermined time interval Tk to the control device 9b.

At the beginning of the predetermined time interval Tk, for example when a positive edge of the time control signal occurs, the control device 9b switches the first switch 15b on and the second switch 27b off and thus starts the charging phase of the integration capacitor 23b. The integration capacitor 23b is charged during the charging phase via the first and second resistors 13b, 17b to a voltage U - which represents the sample-hold value of the sample-and-hold circuit applied to the analog circuit. When the predetermined time interval Tk ends, for example when a negative flank of the time control signal occurs, the control device switches off the first switch 15b and the readiness of the counter 7b to count periodic reference clock pulses, which changes the charge phase to change the voltage at the integration. capacitor 23b begins until a predetermined threshold value U "C2 monitored by the comparator 5b is reached. The comparator 5b changes when the Voltage U -, its output signal at the integration capacitor 23b, whereupon the control device 9b switches on the second switch 27b and switches off the readiness for counting of the counter 7b. The control device 9b notifies the sample-and-hold circuit 59 of the readiness for a new measurement cycle via a readiness signal, so that the sample-and-hold circuit 59 outputs a new sample value U for a next measurement cycle.

After the measuring cycle, an evaluation device (not shown) reads the counting result of the counter 7b in order to thereby calculate a digital measured value for the signal voltage U or U to be detected.

An initial equation for the calculation of a value U can be derived from equation (5) by solving equation (5) for U and replacing U with U and T .. with Tk.

The embodiment of the invention described above shows a new way of analog-to-digital conversion. This embodiment is also not susceptible to faults and can be implemented inexpensively with little circuitry.

The invention is not limited to the exemplary embodiments described, but also includes modifications with changed or additional technical details if the inventive idea is not thereby abandoned. For example, the control device can be provided with delay compensation circuits which take into account different signal propagation times and switching times or preparation times of components. In addition, the control device, in particular include control circuits which ensure that a new measuring cycle can only begin when the previous measuring cycle has been completed. The dimensions of the first and second resistors, the integration capacitor, and the period Tclk of the reference clock signal essentially depend on the desired digital resolution of an analog information to be acquired and on the tolerated maximum duration of a measurement cycle.

The analog circuit 3, 3a, 3b for realizing the charge circuit and the charge change circuit can be replaced by equivalent circuits, for example by a parallel circuit fed by a constant current source, comprising an integration capacitor, a first and a second resistor with a first switch in series with the first Resist and a second switch in series with the second resistor.

Claims

Circuit arrangement for digital detection of analog information, in particular the time interval between two successive states of at least one signal or the amplitude of the signal, with an integration capacitor (23; 23a; 23b) which is connected via a charging circuit (3 ';3a'; 3b ') can be charged to a voltage representing the analog information, with a charge change circuit (3 ";3a"; 3b ") which changes the voltage of the integration capacitor (23; 23a; 23b) at a rate of change less than that of the charge circuit (3 ';3a'; 3b ') changes with a comparator (5; 5a; 5b) comparing the voltage at the integration capacitor (23; 23a; 23b) with a predetermined threshold value and with a counter (7; 7a; 7b), which counts periodic clock pulses during the change in the voltage of the integration capacitor (23; 23a; 23b) by means of the charge change circuit (3 ", 3a", 3b ") until the predetermined threshold value is reached indicates that the charging circuit (3 '; 3a '; 3b ') and the charge change circuit (3 ";3a"; 3b ") change the voltage of the integration capacitor (23; 23a; 23b) in the same direction and are connected to a common charge source.

2. Circuit arrangement according to claim 1, characterized in that for the digital detection of the time interval between two successive states of at least one signal, a signal state detector (8, 8a) of a control device (9, 9a), in particular an edge detector, detects the successive states , and that the control device switches the charging circuit (3 ', 3a ¹ ) effectively when the first time occurs, and switches the charge change circuit (3 ", 3a") effectively when the second state occurs.

3. Circuit arrangement according to claim 2, characterized in that the temporally first and the second signal state in each case optionally corresponds to the exceeding or falling below the predetermined amplitude level of a signal.

4. Circuit arrangement according to claim 2 or 3, characterized in that the temporally first signal state optionally corresponds to the exceeding or falling below predetermined amplitude levels of a first signal and that the second state corresponds either to exceeding or falling below predetermined amplitude levels of a second signal .

5. Circuit arrangement according to claim 2, 3 or 4, characterized in that the charge source is a direct voltage source, in particular a supply voltage source of the circuit arrangement.

6. Circuit arrangement according to claim 1, characterized in that an integration time interval for measuring the amplitude of a signal timer circuit (57) generating a predetermined length interacts with a control device (9b) which switches the charging circuit (3b ') effective at the start of the integration time interval and switches the charge change circuit (3b ") effective at the end of the integration time interval, and that the charge source is the source of the analog signal or a circuit which outputs a voltage proportional to the amplitude of the analog signal.

7. Circuit arrangement according to claim 6, characterized in that the charge source is a sample and sample values of the signal amplitude analog buffering sample-and-hold circuit (59) which during the integration time interval is an output voltage proportional to a sample value of the signal amplitude generates.

8. Circuit arrangement according to one of the preceding claims, characterized in that the integrating capacitor (23; 23a; 23b) via a resistance circuit (11; 11a; 11b) connected in series with the integrating capacitor (23; 23a; 23b) with controllable rem Total resistance value is connected to the charge source.

9. Circuit arrangement according to claim 8, characterized in that the resistance circuit (11; 11a; 11b) comprises a parallel circuit comprising a first resistor (13; 13a; 13b) and a second resistor (17; 17a; 17b) and that Current through the first resistor (13; 13a; 13b) can be switched on and off with a first switch (15; 15a; 15b) of the control device (9; 9a; 9b).

10. Circuit arrangement according to claim 9, characterized in that the value (R ₂ ) of the second resistor (17; 17a) exceeds the value (R ..) of the first resistor (13; 13a) by a multiple of the value of the first resistor.

11. Circuit arrangement according to one of the preceding claims, characterized in that for discharging the integration capacitor (23; 23a; 23b) the connections of the integration capacitor (23; 23a; 23b) via a second switch (27; 27a; 27b) of the control ¬ device (9; 9a; 9b) can be short-circuited.

12. Circuit arrangement according to one of claims 1, 2, 4, 5, 8, 9 and 11, characterized in that the circuit arrangement (la) is part of a time interval measuring device (2) for the digital detection of time intervals (Tx), the duration of which exceeds the duration of the periodic clock pulses by a multiple is that a counter (41) counts the periodic clock pulses during a period (Tm) of the duration of an integer multiple of the clock period duration (Tclk), and that the switching arrangement (la) the time intervals (T_., T ..) between the start of a measuring time interval (Tx) and the ^' beginning of the isochronous time period (Tm) and between the end of the measuring time interval (Tx) and the end of the isochronous time period (Tm) and that an evaluation device further processes the counting results of the counting device (41) and of the counter (7a) to calculate a digital measured value for the time interval (Tx).

13. Circuit arrangement according to claim 12, characterized in that the counting device

(41) comprises a pulse length counter (47) and a pulse pause counter (45), the pulse length counter (47) and the pulse pause counter (45) when counting the time-synchronous period

(Tm) falling periodic clock pulses replace each other.