EP0422550B1 - Device for evaluating the rate of virtual circuits in an asynchronous time multiplex transmission path - Google Patents

Abstract

The incoming cells of a input asynchronous time-division multiplex channel (mtr) are counted by a counter (FFB) assigned to each virtual circuit which is incremented on each incoming cell of the virtual circuit and decremented periodically. Clock signals define consecutively numbered cell times (ntc). Queue and chaining table (FAVE, FCVN) define a cell time queue (FAF, FAL, FAV) specific to each of the cell times, a virtual circuit being assignable to a cell time by writing its identifier into the corresponding cell time queue. A controller (MC) uses the content of the cell time queues (FAF, FAL, FAV) and, for each cell time, identifies a virtual circuit to be processed and decrements the counter (FFB) belonging to this virtual circuit. The controller further includes arrangements whereby any virtual circuit whose counter is not idle is assigned to one of the cell times to be decremented by virtue of the arrival of this cell time.

Description

The present invention relates to a device for evaluating the throughput of virtual circuits using an asynchronous time division multiplex transmission channel.

An asynchronous time division multiplex transmission path is a transmission path carrying data messages in digital data structures called cells. Each cell includes a header consisting, for example, of four eight-bit characters and a message body consisting of a defined number of characters, 32 for example. On the transmission path, such cells follow each other without interruption. If there is no message to transmit, the transmission channel carries an "empty" cell, that is to say a cell of the same format as a message cell and comprising easily recognizable conventional information. Arrangements are made to maintain a sufficient proportion of such empty cells in the flow of message cells; they are used, in particular, for synchronizing the reception end with the format of the cells.

The header of each message cell contains, for example two characters, information defining, for the reception end, the direction in which the message body should be retransmitted. The other two characters of the header contain service information and, in particular, code control and error detection information relating to the two preceding destination characters. The same information is found in the headers of irregularly spaced cells, which have the same destination. It thus identifies a kind of virtual circuit occupying part of the transmission capacity of the transmission channel. More generally, this virtual circuit will occupy the transmission channel by providing it with a certain bit rate, measured for example in cells per unit of time, and this bit rate is fluctuating. The object of the invention is more precisely to evaluate this flow rate, as precisely as possible.

The transmission channel supports several virtual circuits at all times, the cells of which intermittently intercalate in what is commonly called asynchronous time multiplexing. The varying rates of the different virtual circuits are different. The sum of these bit rates is limited by the maximum bit rate of the transmission channel. It also fluctuates. This leaves room for the transmission of empty cells.

Furthermore, the number of virtual circuits which can be separately identified depends on the number of bits allocated to this information in the header of the cells. The maximum number of virtual circuits is itself determined, among other things, by the number of virtual circuits which is obtained by dividing the maximum speed of the transmission channel by the minimum speed of a data source that can borrow a virtual circuit. It is very high and reaches for example 64 K.

However, asynchronous time division multiplex transmission is intended for the broadest fields of application and the bit rates to be expected for the sources which can borrow a virtual circuit are staged in a wide range of bit rates (for example from a few kilobits to a few hundred megabits per second). The number of active virtual circuits will therefore generally be much less than their maximum number.

The foregoing definition of asynchronous time division multiplex transmission should not, however, be limited to cases where the cells are all the same length. The use of cells of different lengths, all multiples of a base length is conceivable and the adaptations which result therefrom, as regards the present invention, are within the reach of those skilled in the art.

A time-division multiplex transmission channel asynchronous is therefore made to route the data supplied by sources with very varied and fluctuating bit rates. Downstream, switching and transmission equipment routes the messages contained in the cells to their destinations. It is therefore advisable, at the level of the transmission channel considered, to avoid the risk of bottlenecks downstream, to ensure that no source, by fraud or following a failure, brings, even temporarily, a flow higher than that which is globally attributed to it.

A known solution to this problem is repression. The routing by the transmission channel of any cell considered to be in excess of the bit rate globally allocated to the virtual circuit is prevented, or at least the excess cell is marked as such, so that it is rejected further, in engorgement.

The application of such a solution requires a measurement of the flow rate observed on the virtual circuit, such a measurement possibly leading to the marking of an excess cell.

Document FR-A-2 616 024 discloses a flow measurement device which comprises a counter incremented by one step upon receipt of a cell of the virtual circuit to which it is assigned and decremented by one step at each pulse of a clock. If the flow rate of the virtual circuit is low, this counter moves back more often than it advances and ends up blocking in a minimum position; on the other hand, if the frequency of the cells of the virtual circuit is durably higher than that of the clock pulses, the counter ends up blocking in a maximum position and can then cause the marking of the cell as excess indicated above.

The disadvantage of such a system is that it can only be applied to a limited number of virtual circuits, due to the time required to decrement the counters. It is not applicable in the case where the virtual circuits are very numerous as envisaged previously.

The present invention therefore proposes a device for evaluating the throughput of virtual circuits using an asynchronous time-division multiplex transmission channel, in which the incoming cells of an asynchronous time-division multiplex input channel, comprising a header containing information destination can be treated as a virtual circuit identity, are counted by a counter assigned to each virtual circuit, which is incremented at each incoming cell of the virtual circuit and which is periodically decremented, as long as it is not in a position rest, device not suffering from the mentioned limitation.

According to an essential characteristic of the invention, this device comprises clock means defining successively numbered cell times, corresponding to successive time intervals during which incoming cells are received on the asynchronous input time division multiplex transmission channel. , queue means defining a cell time queue specific to each of said cell times, a virtual circuit being able to be assigned to cell time by registering its identity in the cell time queue corresponding, control means using the content of said cell time queues and, at each cell time, being able to identify a virtual circuit to be processed and decrement the counter belonging to this virtual circuit, these control means further comprising provisions such that any virtual circuit whose counter is not in the rest position is assigned to a cell times so that the counter is decremented due to the occurrence of this cell time.

According to another characteristic of the invention, said control means are such that at each cell time, the content of the cell time queue associated with this cell time is transferred to a processing queue, each the virtual queue identity of the processing queue being used in turn to decrement the counter of the virtual circuit it designates.

According to another characteristic of the invention, said control means are such that after the counter of a virtual circuit has been decremented, and if this counter has not returned to the rest position, the identity of this virtual circuit is entered in a cell time queue which is selected taking into account a speed indication attached to the virtual circuit considered.

According to another characteristic of the invention, said control means are such that after the counter of a virtual circuit has been decremented, and if this counter has not returned to the rest position, the identity of this virtual circuit is entered in a cell time queue which is selected by taking into account an indication of speed attached to the virtual circuit considered, and a data item dependent on the observed bit rate of this virtual circuit.

According to another characteristic of the invention, said control means are such that on receipt of an incoming cell and if the counter of the virtual circuit is in its rest position, the identity of this virtual circuit is entered in a cell time queue which is selected taking into account a speed indication attached to the virtual circuit considered.

According to another characteristic of the invention, said control means are such that on reception of an incoming cell and if the counter of the virtual circuit is in its rest position, the identity of this cell time is entered in a cell time queue which is selected taking into account a speed indication attached to the virtual circuit considered, and a data item dependent on the observed bit rate of this virtual circuit.

According to another characteristic of the invention, said datum depending on the bit rate is the position occupied by the counter of the virtual circuit considered.

According to another characteristic of the invention, there is provided a count indication specific to each virtual circuit and said control means are such that this count indication is incremented during the decrementation of said counter of a virtual circuit, when this counter is in a determined position range, and decremented, if the counter is in a position lower than this position range.

According to another characteristic of the invention, said count indication has a maximum value, reached in the case where said range is reached in the majority, said control means further comprising provisions which then cause the implementation of a speed indication corresponding to a reduction in the speed of decrementation of said counter.

According to another characteristic of the invention, said control means are such that, when a virtual circuit counter is decremented, and if this counter has not thus returned to its rest position, the identity of the circuit to which it belongs is entered in a cell time queue which is selected from the current cell time.

According to another characteristic of the invention, said control means are such that, when a virtual circuit counter is decremented, and if this counter has not thus returned to its rest position, the identity of the virtual circuit to which it belongs is entered in a cell time queue which is selected from the cell time to which the virtual circuit in question had previously been assigned, whose identity had been registered for this purpose.

According to another characteristic of the invention, means are provided for detecting that the counter of a virtual circuit has reached a maximum position, for preventing it from exceeding it, as well as for causing the sending of a signal indicating that the speed of the virtual circuit is excessive.

The various objects and characteristics of the invention will appear in more detail in the description which follows, given by way of nonlimiting example, with reference to the appended figure which represents an embodiment of the device for evaluating flow of the present invention.

An asynchronous time multiplex input channel mtr is coupled to a reception logic LR. This multiplex channel is for example of the type mentioned in the preamble. It provides successive incoming cells with a header containing a virtual circuit number.

An asynchronous time division multiplex channel mte output is coupled to the reception logic LR. This channel is the same type as the input channel mtr. The LR reception logic provides it with outgoing cells which are the successive incoming cells possibly affected by a delay and modified as will be seen later.

The device of the invention comprises means which will now be described, for evaluating the spacing between the cells of each of the virtual circuits, that is to say the bit rate of each of the virtual circuits supported by the multiplex channels. mtr, mte.

These means essentially include a clock HG, a CTC cell counter, FAVE, FAVR, FCVC, FCVN, FCVR, FCVV memory areas, as well as MC control means.

The HG clock is a time base which is synchronized with the signals received from the incoming multiplex channel mtr, by means not shown, but well known in the art, and which provides inter alia a CV signal identifying the start of a repetitive time interval called cell time, the duration of which is that of reception, or transmission, of a cell.

The cell time counter CTC is a cyclic counter with N positions (N integer and preferably equal to a power of 2) which provides, at each cell time, a cell time number ntc successively taking the different values from 0 to N- 1.

Furthermore, the reception logic LR supplies, on an LLR link, the identity NCV of the virtual circuit to which each received cell belongs.

• une table de files d'attente de temps cellule FAVE comprenant N emplacements, un par numéro de temps cellule; chacun de ces emplacements sert à la constitution d'une file d'attente de temps cellule et contient à cet effet l'identité FAF d'un premier circuit virtuel demandant un traitement, l'identité FAL d'un dernier circuit virtuel demandant un traitement, ainsi qu'un bit FAV servant à marquer une file d'attente vide,
• une table de traitement FAVR comprenant l'identité FVF d'un premier circuit virtuel demandant un traitement et l'identité FVL d'un dernier circuit virtuel demandant un traitement.
• une table de compteurs de circuits virtuels FCVR comprenant un emplacement de mémoire par circuit virtuel, chacun d'eux contenant un compte FFB du nombre de cellules reçues sur ce circuit virtuel et demandant une évaluation (dans ce qui suit, sans que cela nuise à la clarté, on désignera souvent ces emplacements de mémoire comme des compteurs FFB),
• une table de vitesses FCVV comprenant un emplacement de mémoire par circuit virtuel, chacun d'eux contenant au moins deux indications de vitesse indv1 et indv2 à utiliser en relation avec ce circuit virtuel comme on le verra par la suite,
• une table de chaînage FCVN comprenant un emplacement de mémoire par circuit virtuel, chacun d'eux contenant l'identité FFN d'un autre circuit virtuel avec lequel le circuit virtuel considéré est chaîné.

The memory areas mentioned are more precisely:

• a FAVE cell time queue table comprising N locations, one per cell time number; each of these locations is used to constitute a cell time queue and for this purpose contains the FAF identity of a first virtual circuit requesting processing, the FAL identity of a last virtual circuit requesting processing , as well as a FAV bit used to mark an empty queue,
• a FAVR processing table comprising the FVF identity of a first virtual circuit requesting processing and the FVL identity of a last virtual circuit requesting processing.
• a table of FCVR virtual circuit counters comprising a memory location per virtual circuit, each of them containing an FFB count of the number of cells received on this virtual circuit and requesting an evaluation (in what follows, without this affecting clarity, these memory locations will often be designated as FFB counters),
• an FCVV speed table comprising a memory location per virtual circuit, each of them containing at least two speed indications indv1 and indv2 to be used in relation to this virtual circuit as will be seen below,
• an FCVN chaining table comprising a memory location per virtual circuit, each of them containing the identity FFN of another virtual circuit with which the considered virtual circuit is chained.

When a cell is received on the incoming channel mtr, the clock HG provides a signal CV, the reception logic LR provides, on the link LLR, the identity NCV of the virtual circuit to which the cell belongs, derived from the -head of the cell, while the CTC counter provides a cell time interval number ntc. In response, the device MC reads the table FCVR, according to the identity of the virtual circuit NCV, and obtains the number FFV of cells of the virtual circuit already received and not yet given rise to processing. This number is incremented, before being rewritten in the same location.

In addition, the FFB number is tested, before being incremented, for example. If it is non-zero, no specific action is required at this time. The number of cells received and required to undergo evaluation processing simply increases by one.

On the other hand, if the number FFB is zero, or, in other words, if the counter FFB is in a rest position, the virtual circuit to which the received cell belongs must be assigned to a cell time, for a evaluation treatment. For this, the device MC registers the identity of the virtual circuit NCV in the table of FAVE queues. More precisely, the device MC addresses the table FAVE with an indication of address NTC which is derived from the current cell time number, supplied by the counter CTC, for example by adding a constant value. At the location designated by this NTC address indication, in the FAVE table, the device MC reads the identities FAF of the first virtual circuit already assigned to this cell time, and that, FAL, of the last virtual circuit assigned to this cell time. , as well as the FAV bit. The device MC records, as a new identity FAL, the number NCV of the virtual circuit considered. In addition, the FAL identity is used to address the FCVN table and to enter the NCV identity there as an indication of FFN chaining. However, if the FAV bit indicates that the queue was empty, this last operation is omitted and the NCV identity is also registered as FAF identity, in the FAVE table, at the NTC address, while the FAV bit y is changed state to indicate now that the queue is not empty.

Thus, the number of the virtual circuit considered is chained in a queue associated with a cell time to come, the beginning of which is the FAF identity and the end of the FAL identity, the chaining being materialized by the registration of numbers virtual circuits in the FCVN table; this process is classic.

According to a variant, instead of chaining the identity of the virtual circuit in an upcoming cell time selected by adding a constant value to the current cell time number ntc, the FCVV table is also read and provides, coming from a location belonging to the virtual circuit considered, read in response in response to the virtual circuit number NCV, a speed indication indv1, which is added to the current cell time number ntc. The sum ntc + indv1 then provides the NTC address. The speed indication indv1, which can actually be a spacing value between cells to be taken into account when the flow rate of the virtual circuit is low, serves to adopt a low decrementation speed for the FFB counter.

Furthermore, still in the context of the test of the position of the FFB counter, provision will be made, according to the invention, for the detection of the extreme position reached by the FFB counter in the event of persistence of an excessive flow rate. The control means MC, detecting such an extreme position, are arranged to supply an exc signal, which is transmitted to the reception logic LR. It can be used to modify the next cell of this virtual circuit received from the incoming multiplex link, before it is transmitted on the outgoing link, in order to make it appear as excess in relation to the bit rate allowed for the virtual circuit considered.

All the cells received give rise to the operations which have just been described. A first cell of a virtual circuit, which occurs while the FFB counter of this virtual circuit is in the rest position, is chained as we have just seen. Subsequent cells, which appear when the counter is no longer at rest, are not chained in this way; they are later and in a different way, as we will see now, in the description of the evaluation process.

At each cell time, the control means MC carry out an evaluation processing, an essential element of which is to decrement the counter FFB of a virtual circuit. From the ntc number provided by the CTC counter, the MC device reads the FAVR table. The indication FVF designates a virtual circuit whose counter FFB is not in the rest position, that is to say having supplied a cell for which the evaluation processing has not yet been carried out. This indication is used to read the FCVR table and the FFB counter is decremented; his position can then become equal to zero and there is no need to chain the virtual circuit again in the cell time queue.

Furthermore, the same FVF indication is used to address the FCVN chaining table. This table provides, at the address indicated, the FFN identity of a next virtual circuit, in the transmission queue, which is then entered in the FAVR table, as a new FVF indication, for the processing of the next virtual tour. The combination of the FAVR and FCVN tables thus provides the list of virtual circuits to be subject to evaluation processing. If it happens to be empty, no processing is carried out.

On the other hand, the device MC addresses the queue table FAVE, from the number ntc, to read there the identity FAF which constitutes the start of the queue of virtual circuits associated with the cell time considered and the FAL identity which is the end of it, unless the FAV bit indicates that the queue is empty. In addition, the FVL identity from the FAVR table is used to address the FCVN table. At the address in question of the table FCVN is registered the identity FAF, while the identity FAL is registered in the table FAVR, as new indication FVL, and that the bit FAV is switched, in the location that the we just read from the FAVE table, to indicate that the queue is empty. This performs the chaining of the entire queue associated with the cell time considered, in the queue of virtual circuits to be evaluated. It should be noted that this chaining can also be carried out before using the processing queue.

Of course, if the FAV bit initially read in the FAVE table indicates that the cell time queue in question is empty, the chaining operations in the processing queue just described are omitted.

Finally, since we have just carried out an evaluation processing for the benefit of a virtual circuit, initializing a possible evaluation processing of this same virtual circuit. For this, it is appropriate, starting from the identity of this virtual circuit FVF, provided by the table FAVR, to interrogate the counter table FCVR and the speed table FCVV. The first provides an indication of the number of cells awaiting evaluation of the virtual circuit. The higher this number, the higher the speed of decrementation of the counter FFB of the virtual circuit, that is to say the more the interval between operations of decrementation must be reduced. As an example, the FCVV table provides two indications indv1 and indv2, each associated with a flow level of the virtual circuit. These indications can be the number of cell times which must elapse before the counter FFB of the virtual circuit is again decremented. If the flow is low, then the indication indv1 applies. The device MC performs the sum ntc + indv1 and uses it to address the FAVE table. The identity FAL of the last virtual circuit associated with this cell time is used to address the table FCVN and to write there, at this address, the identity of the virtual circuit considered, FAF, read in the table FAVE at the address ntc. This last identity is then entered in the FAVE table, at the address ntc + indv1, as a new FAL address, while the FAV bit, at the same address, is switched, if necessary, to indicate that the queue is not is not empty. These operations carry out the chaining of the virtual circuit at cell time ntc + indv1. Of course, if the speed of the virtual circuit is higher, the indication indv2 can apply and cause the chaining of this virtual circuit associating it with a cell time ntc + indv2 closer, and so on. In addition, the intervals specified by the indications indv1, indv2, etc., will take into account the transmission speed of the virtual circuit. It will be noted that this interval is at most equal to N, which is not a problem, even for virtual circuits with low bit rate.

An additional arrangement of the regulation device of the invention, as just described, is shown in dotted lines in FIG. 2. It is an FCVC table having a location by virtual circuit containing at least one count indication such as CPT1, CPT2 ... This memory is addressed to the processing of a cell, by the FVF indication provided by the processing queue (table FAVR). The count indication CPT1 is decremented, or incremented, as a function of the number of cells received from the virtual circuit and not yet evaluated, indicated by the counter FFV of the table FCVR. The counter CPT1 is thus decremented (up to zero only) if the number supplied by the counter FFB is low and results, for example, in the use of the indication of spacing indv1. It is incremented, if this number is higher. Other similar metering positions may be associated with higher flow rates. Each additional count indication will have a reduced capacity compared to the previous ones. These different metering indications will thus each evaluate an average presence of the flow of the incoming circuit at a given level, all of these metering indications defining a flow-time template. If the flow rate of the virtual circuit remains too long at a given level, the corresponding count indication will reach its maximum. It is then easy to authoritatively limit the time during which the flow rate can, on average, remain at any given level by accordingly defining the counting capacity of the corresponding count indication and by providing that, when the count indication of this level reaches its maximum, instead of applying the spacing indication which normally applies for this level, indv2 for example, we will choose instead an indication of spacing leading to a lower decrementation speed, indv1 for example. The result will be a rapid progression of the FFB counter of the virtual circuit, if the input rate is not reduced and, consequently, the subsequent refusal of supernumerary cells.

To summarize, each incoming cell is counted by incrementing the counter FFB of the virtual circuit to which it belongs. A cell time queue is associated with each cell time. An evaluation queue is associated with the entire multiplex link. It is supplied by cell time queues.

A first incoming cell of a virtual circuit first gives rise to registration of the virtual circuit in the queue for a cell time following that in which it arrives. When this cell time is reached, the corresponding cell time queue is incorporated at the end of the evaluation queue. When there is a turn in the evaluation queue, the virtual circuit undergoes evaluation processing consisting mainly in decrementing the FFB counter of this virtual circuit and in incrementing or decrementing the counting indication (s) appropriate from this virtual tour.

If the flow rates of the virtual circuits are low, each incoming cell of a virtual circuit gives rise to evaluation processing before the next cell occurs, so that the counter FFB of the virtual circuit remains in the rest position.

A management device, not shown, may become aware from time to time of the position of the counters of the table FCVR. For any counter in the rest position, it can conclude that the flow rate of the virtual circuit is lower than the minimum flow rate associated with the circuit virtual in the form of the speed indication indv1.

For a virtual circuit providing a higher flow rate, the FFB counter leaves its rest position. If no other speed indication is used, the position of the FFB counter is simply the measurement of the excess, in number of cells, of the speed of the virtual circuit compared to a speed defined by the speed indication indv1. The capacity of the meter characterizes the extent of the tolerance in this regard. When this is exceeded, an incoming cell finds the FFB counter in the extreme position. This causes the supply of the signal exc in order to characterize this last cell as surplus.

The use of several speed indications, as a function of the observed speed of the virtual circuit, for example as a function of the range of positions reached by the FFB counter of this virtual circuit, makes it possible to evaluate the exceeding, not of a threshold of flow, but several. The number of remaining counter positions being lower at each new flow threshold crossed, the extent of the permitted exceeding of this threshold, in number of cells is each time smaller, which amounts to assigning to the virtual circuit flow couples -exceeding expressing the fact that the virtual circuit is allowed to provide increasing bit rates, each of them with a remaining tolerance more reduced than the previous ones. The reading of the meter by the management device is always an evaluation of the flow rate of the virtual circuit above the minimum flow rate mentioned, but it requires an interpretation as a function of the speed indications of this virtual circuit which act on the evolution of the meter.

The addition of the counting indications CPT1, CPT2, etc. allows the persistence of the flow rate of the virtual circuit at a given level to be included in the flow evaluation.

Furthermore, we will now examine a variant in the evaluation of the flow, compared to what has just been described. It is recalled that, as soon as a cell presents itself before the previous one has given rise to the evaluation processing, this second cell is simply counted. When the processing requested by the first cell is completed, the presence of a second cell in the account held by the FFB counter gives rise to the virtual circuit being registered in a queue for an upcoming cell time determined from the current cell time and a speed indication specific to the virtual circuit. The second cell will thus give rise to an evaluation processing with a minimum spacing determined with respect to the first. It will possibly be the same for the following cells, until we return to the treatment initially summarized. It will be noted that it is possible, in a simple manner, to give the processing operations of the received cells a defined average spacing and not a minimum spacing. It is enough to determine the cell time with which a virtual circuit is associated for the processing of a next cell, at the time of the current cell processing, not by an expression such as ntc + indv1 or ntc + indv2, as indicated above, in which ntc denotes the current cell time, but by an expression such as NTC (i + 1) = NTCi + indv1 or NTCi + indv2, in which NTCi is the cell time to which the virtual circuit had been previously assigned. For this, it suffices to keep the information NTCi in an additional table similar to the table FCVF and to read it when calculating NTC (i + 1). Thus, the consecutive cells of the same virtual circuit would give rise to assignment to cell times regularly spaced from indv1 or indv2 and would therefore be treated with real spacing based on average on such regular spacing and affected only by the inequalities of the queues d waiting for cell times. Of course, the expression of NTC (i + 1) indicated above is only applicable as long as it provides a value designating a cell time after the current cell time ntc. For this reason, it is possible to provide means for correcting the NTC value (i + 1) such that this is the case in all cases.

The reception logic LR, and the control device MC are essentially logic data processing devices. It is not necessary to give a detailed description. In the current state of the art, their realization poses no difficulty to the specialist; it will be based on the use of programmed processors having performances adapted to the durations available to accomplish the listed operations, taking into account the speed of the multiplex links. Depending on requirements, in terms of performance, a greater or lesser number of processors sharing the described operations can be provided. Furthermore, one can conceive of such a device operating for the benefit of several incoming channels and several outgoing channels. One can even consider associating or incorporating it into a channel switch with asynchronous time division multiplexing.

Likewise, no mention has been made of initialization operations, the necessity of which is obvious and the realization of which belongs to the conventional technique in this field.

In general, it is quite obvious that the foregoing descriptions have been given only by way of nonlimiting example and that numerous variants can be imagined, without thereby departing from the scope of the invention.

Claims (12)

1. Device for evaluating the throughput of virtual circuits carried by an asynchronous time-division multiplex transmission channel in which the incoming cells of an input asynchronous time-division multiplex channel (mtr) including a header containing a destination indicator that can be treated as a virtual circuit identifier are counted by a counter (FFB) assigned to each virtual circuit which is incremented for each incoming cell of the virtual circuit and which is periodically decremented if it is not in a rest condition, characterised in that it comprises clock means (HG, CV, CTC) defining consecutively numbered cell times (ntc) corresponding to successive time intervals during which incoming cells are received on the input asynchronous time-division multiplex transmission channel, queue means (FAVE, FCVN) defining a cell time queue (FAF, FAL, FAV) specific to each of said cell times, a virtual circuit being assignable to a cell time by writing its identifier into the corresponding cell time queue, control means (MC) using the content of said cell time queues (FAF, FAL, FAV) and, for each cell time, being able to identify a virtual circuit to be processed and to decrement the counter (FFB) belonging to this virtual circuit, these control means further comprising arrangements whereby any virtual circuit whose counter (FFB) is not idle is assigned (FAVE) to one of the cell times in order for the counter (FFB) to be decremented by virtue of the arrival of this cell time.
2. Virtual circuit throughput evaluation device according to claim 1 characterised in that said control means (MC) are such that in each cell time the content of the cell time queue associated with the cell time is transferred into a processing queue (FAVR, FCVN), each virtual circuit identifier (FVF, FVL, FFN) of the processing queue being used in turn to decrement the counter (FFB) of the virtual circuit that it designates.
3. Virtual circuit throughput evaluation device according to claim 2 characterised in that said control means (MC) are such that after the counter (FFB) of a virtual circuit is decremented and if the counter has not reached its idle state the identifier of this virtual circuit is written into a cell time queue (FAVE, FCVN) which is selected allowing for a speed indicator (FCVV, indv1) attached to the virtual circuit in question.
4. Virtual circuit throughput evaluation device according to claim 3 characterised in that said control means (MC) are such that after the counter (FFB) of a virtual circuit is decremented and if the counter has not reached its idle state the identifier of this virtual circuit is written into a cell time queue (FAVE, FCVN) which is selected allowing for a speed indicator (FCVV, indv1) attached to the virtual circuit in question and data (FCVR, FFB) dependent on the observed throughput of this virtual circuit.
5. Virtual circuit throughput evaluation device according to claim 3 or claim 4 characterised in that said control means (MC) are such that when an incoming cell is received and if the counter of the virtual circuit is idle the identifier of this virtual circuit is written into a cell time queue (FAVE, FCVN) which is selected allowing for a speed indicator (FCVV, indv1) attached to the virtual circuit in question.
6. Virtual circuit throughput evaluation device according to claim 3 or claim 4 characterised in that said control means (MC) are such that when an incoming cell is received and if the counter of the virtual circuit is idle the identifier of this cell time is written into a cell time queue (FAVE, FCVN) which is selected allowing for a speed indicator (FCVV, indv1) attached to the virtual circuit in question and data (FCVR, FFB) dependent on the observed throughput of this virtual circuit.
7. Virtual circuit throughput evaluation device according to claim 4 or claim 5 or claim 6 characterised in that said data dependent on the throughput is the position occupied by the counter (FFB) of the virtual circuit in question.
8. Virtual circuit throughput evaluation device according to claim 7 characterised in that a count indicator (CPT1, CPT2) is provided for each virtual circuit and in that said control means (MC) are such that this count indicator is incremented when said counter (FFB) of a virtual circuit is decremented if said counter state is in a predetermined range of states and decremented if said counter state is below this range of states.
9. Virtual circuit throughput evaluation device according to claim 8 characterised in that said count indicator (CPT1, CPT2) has a maximal value reached if said range of states is reached on a majority basis, said control means further comprising means which then cause the use of a speed indicator (indv1) corresponding to a reduction in the speed at which said counter is decremented.
10. Virtual circuit throughput evaluation device according to any one of claims 3 to 9 characterised in that said control means (MC) are such that when a virtual circuit counter (FFB) is decremented and if this counter has not then returned to its rest state the identifier of the virtual circuit to which it belongs is written into a cell time queue (FAVE, FCVN) which is selected on the basis of the current cell time (ntc).
11. Virtual circuit throughput evaluation device according to any one of claims 3 to 9 characterised in that said control means (MC) are such that when a virtual circuit counter (FFB) is decremented and if this counter has not then reached its rest condition the identifier of the virtual circuit to which it belongs is written into a cell time queue (FAVE, FCVN) which is selected on the basis of the cell time to which the virtual circuit in question has previously been assigned, the identifier of which has been stored for this purpose.
12. Virtual circuit throughput evaluation device according to claim 9 characterised in that means are provided for detecting when the counter of a virtual circuit has reached an extreme position to prevent it overshooting the latter and to cause the transmission of a signal indicating that the throughput of the virtual circuit is excessive.

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