EP0485889A1 - Procédé de fabrication d'éléments métalliques en forme de fourche, comme des éléments fixés à la tige de piston d'un vérin hydraulique ou pneumatique, et système pour la réalisation du procédé - Google Patents
Procédé de fabrication d'éléments métalliques en forme de fourche, comme des éléments fixés à la tige de piston d'un vérin hydraulique ou pneumatique, et système pour la réalisation du procédé Download PDFInfo
- Publication number
- EP0485889A1 EP0485889A1 EP91118983A EP91118983A EP0485889A1 EP 0485889 A1 EP0485889 A1 EP 0485889A1 EP 91118983 A EP91118983 A EP 91118983A EP 91118983 A EP91118983 A EP 91118983A EP 0485889 A1 EP0485889 A1 EP 0485889A1
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- European Patent Office
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- output
- terminal
- threshold
- voltage
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- 238000000034 method Methods 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 title 1
- 230000009467 reduction Effects 0.000 abstract description 6
- 238000007599 discharging Methods 0.000 abstract description 4
- 230000001276 controlling effect Effects 0.000 abstract description 2
- 230000002596 correlated effect Effects 0.000 abstract description 2
- 230000001419 dependent effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B21—MECHANICAL METAL-WORKING WITHOUT ESSENTIALLY REMOVING MATERIAL; PUNCHING METAL
- B21K—MAKING FORGED OR PRESSED METAL PRODUCTS, e.g. HORSE-SHOES, RIVETS, BOLTS OR WHEELS
- B21K1/00—Making machine elements
- B21K1/74—Making machine elements forked members or members with two or more limbs, e.g. U-bolts, anchors
Definitions
- the present invention relates to a reset device for microprocessor, particularly for automotive applications.
- Cars are receptacles for an enormous amount of disturbance, much of which originating in the electrical equipment on the car itself, and caused, for example, by on-off operation of various types of inductive loads (ignition coils, injectors, relays) or resistive loads (lights). Nor are they immune to additional external disturbance, such as that caused by radio and television transmitters and repeaters.
- the purpose behind such control of the supply voltage is to disable operation of the microprocessor in conditions in which it cannot operate reliably.
- the information for disabling the microprocessor is supplied to it in the form of a reset signal supplied by what is known as a reset device.
- reset circuits consist of two comparators and a capacitance, as shown in Fig.3.
- the input voltage V IN from the voltage regulator is supplied to one input of comparator 1, the other input of which is connected to a threshold voltage Th 1 usually close to the nominal value of V IN (e.g. 4.6 V).
- Comparator 1 provides for monitoring voltage V IN and, upon this falling below threshold Thi, closes switch 2 for grounding condenser 4, which is thus discharged via resistor 3. If voltage V IN remains below threshold Th 1 , after a time depending on time constant RC (where R is the resistance of resistor 3, and C the capacitance of condenser 4), the voltage of condenser 4 falls below a second threshold Th 2 , e.g. 4 V, thus switching a second comparator 5, the output of which constitutes the reset signal. Downward switching of the reset signal provides for disabling the microprocessor connected downstream from second comparator 5.
- switch 2 opens and condenser 4 is charged to voltage V cc by current I supplied by current source 6. After a given time (proportional to Th 2 * C/I, if the condenser is fully discharged), the voltage of condenser 4 gradually exceeds Th 2 , and the output of comparator 5 again switches to high for enabling normal operation of the microprocessor.
- the purpose of the delay in disabling the reset signal is to give the microprocessor time to stabilize its internal circuits upon the supply voltage being restored.
- the above known circuit presents a number of drawbacks, foremost of which is that the reset signal is enabled solely on the basis of how long the input voltage remains below the first threshold.
- the capacity of a microprocessor to withstand a fall in voltage depends not only on the duration but also on the amount by which the voltage falls in relation to the nominal value.
- a further drawback of the above known circuit is that it lacks precision as regards the delay with which the reset signal is disabled.
- the condenser in fact, continues discharging as long as the input voltage V lN remains below first threshold Thi.
- the time required for charging the condenser to second threshold Th 2 obviously depends on the voltage of the condenser when charging commences, which voltage may be zero or anywhere between zero and Th 2 , depending on whether the fall in voltage is of long or short duration respectively. This obviously results in imprecision as regards the time required for charging the condenser to threshold Th 2 and disabling the reset signal.
- a reset device for microprocessor particularly for automotive applications, defining an input terminal and an output terminal, and comprising a first comparing stage input-connected to said input terminal and to a first source of a first threshold signal; a switch controlled by said first comparing stage, for switching between a closed and an open state; a capacitive element charged and discharged depending on the state of said switch; and a second comparing stage input-connected to said capacitive element and to a second source of a second threshold signal, for generating a reset signal having two different logic states and supplied to said output terminal; characterised by an adding element input-connected to said input terminal and to said capacitive element, and output-connected to said second comparing stage.
- the reset device comprises an input comparator 1 having a non-inverting input supplied with input voltage V 1N ,and an inverting input connected to a voltage source 9 supplying a first threshold voltage Th 1 of, for example, 4.6 V.
- the output of comparator 1, at which logic signal x o is present, is connected to the input of a sequential logic network 10 with a memory, the O c signal output of which is connected to the control terminal of a switch 2 located between a reference potential line (ground) and a first terminal of a resistor 3.
- resistor 3 The other terminal of resistor 3 is connected, at point 11, to one terminal of a condenser 4, the other terminal of which is grounded.
- a current source 6 is located between point 11 and a second reference potential line of, say, 5V; and a switch 12 is located between point 11 and a voltage source 13 (generating voltage V R of, say, 1.2 V) with the interposition of a resistor 14.
- Input voltage V IN is also supplied over line 25 to one input of an adder 15, the other input of which is connected to point 11 over line 26 and therefore receives voltage V c of condenser 4.
- comparator 5 at which reset signal x R supplied to output terminal 52 of the device is present, is connected over line 27 to one input of logic network 10 and, over line 28, to one input of an AND circuit 16, the other input of which is connected over line 29 to the output of first comparator 1, and therefore receives signal x o .
- the output of AND circuit 16 is connected to the control terminal of switch 12 for opening and closing the switch.
- the Fig.1 device also comprises a third comparator 17, the non-inverting input of which is connected to point 11 and receives voltage V c ; and the inverting input of which is connected to a further voltage source 19 supplying a third threshold voltage Th 3 of, say, 20 mV.
- the x c signal output of comparator 17 is connected to one input of logic network 10.
- the Fig.1 device operates as follows.
- Input voltage V IN is monitored by comparator 1, which compares it with first threshold Thi. As long as the input voltage remains above the first threshold, signal x o remains high, thus keeping switch 2 open and switch 12 closed via circuit 16; condenser 4 is charged to the voltage of source 13 (1.2 V); the output of comparator 5 is high; and signal x R is disabled (high).
- comparator 5 is only switched by very low V c values, i.e. after a relatively long time; whereas, for a substantial fall in input voltage in relation to the nominal value, comparator 5 is switched by a smaller V c voltage value, i.e. a substantial fall in input voltage for a relatively short time is sufficient to enable reset signal V R .
- the linear combination of the input and condenser voltages obviously provides for taking into account all the intermediate situations.
- Logic network 10 is informed of the low (enabled) state of reset signal x R over line 27, and keeps switch 2 closed as long as condenser voltage V c remains above third threshold Th 3 . In this way, even if the input voltage falls rapidly, enough to cause a reset, and then moves back up over threshold Thi, the condenser continues discharging until voltage V c reaches threshold Th 3 , as detected by comparator 17, which informs logic network 10 by switching signal x c to low. At this point, logic network 10 opens switch 2, and condenser 4 begins charging, via current source 6, from a known starting voltage corresponding to third threshold Th 3 and very close to zero (20 mV).
- Fig.2 shows a more detailed diagram of the Fig.1 circuit, and will be described only as to the parts which are more detailed with respect to Fig. 1.
- logic network 10 comprises a flip-flop 35 consisting of two NAND circuits 36, 37 and controlling a further two NAND circuits 38, 39.
- Circuit 36 presents three inputs: a first connected to the output of comparator 1 for receiving signal x o ; a second connected to line 40 extending from the output of comparator 5 and on which the inverted signal of the reset signal is present; and a third connected to the output of NAND circuit 37.
- NAND circuit 37 in turn presents two inputs, one connected to output Q of NAND circuit 36, and the other to the output of comparator 17 for receiving signal x c .
- NAND circuit 36 The output of NAND circuit 36 is connected to one input of NAND circuit 38, the other input of which is also connected to line 40.
- the output of NAND circuit 38 is connected to one input of NAND circuit 39, the other input of which is connected to the output of comparator 1.
- Adder 15 consists of a double voltage divider comprising three resistors 41-43.
- Resistor 41 is connected by one terminal to a common point 45 and, by the other terminal, to the device input via a switch 44, e.g. a MOS transistor, the control terminal of which is connected to line 40.
- Resistor 42 is connected between points 11 and 45, and resistor 43 between point 45 and ground, via a switch 46, e.g. a MOS transistor, the control terminal of which is connected to the output of NAND circuit 36.
- Comparator 5 comprises a comparing element 48 with its inverting input connected to point 45, and its non-inverting input connected to voltage source 49, which simultaneously implements sources 13 and 18 in Fig.1.
- the output of comparing element 48 controls a transistor 50, e.g. a bipolar transistor, having its emitter grounded and its collector connected to the input of a buffer element 51, the output of which constitutes the output terminal 52 of the device and supplies reset signal x R .
- Output terminal 52 is also connected to an inverting element 53, the output of which is connected to line 40 and to the control terminal of a switch 54 consisting, for example, of a MOS transistor and connected between the input of buffer 51 and ground via a further switch 55, the control terminal of which is connected to the output of logic network 10.
- a current source 56 is also provided between the input of buffer 51 and a supply line.
- Switch 12 here consists of a voltage-follower operational amplifier having a non-inverting terminal connected to source 49, and an enabling input connected to the output of circuit 16.
- the Fig.2 circuit operates as described with reference to Fig.1, with circuits 36-39 implementing the above logic function, and adder 15 consisting of a double voltage divider.
- adder 15 consisting of a double voltage divider.
- switches 44 and 46 provide for maintaining constant the time interval required for disabling reset signal x R when the input voltage rises above the first threshold and the condenser is fully discharged.
- comparing element 48 may switch to low as soon as condenser 4 reaches threshold Th 2 .
- the output signal of comparing element 48 is inverted by transistor 50 and buffered by component 51 for supplying the actual reset signal.
- Switches 54 and 55 provide a hysteresis of the reset signal by grounding the input of buffer 51 when the reset signal is enabled (low) and the output of logic network 10 is high, for enabling discharge of the condenser and so ensuring greater reliability of the device.
- the device is insensitive to reductions in input voltage for varying lengths of time depending on the amount of reduction, by virtue of the signal by which the reset signal is switched being correlated to both the absolute value of and the duration of the reduction in the input voltage.
- the reset signal is practically always disabled within a given period after the input signal rises above a given threshold, by virtue of comparator 17 and logic network 10 ensuring that the condenser is always practically fully discharged, and always commences charging from a practically constant value.
- the condenser After each fall in voltage, regardless of whether or not the reset signal is switched, the condenser is always charged fully by means of switch 12 controlled by circuit 16, thus enabling the device, at all times, to measure the duration of each fall in input voltage and so provide for greater reliability and correct switching of the reset signal.
- the circuit may be implemented and integrated easily, is flexible, and reasonably cheap to produce.
- adder 15 may consist of components other than those described herein; the switches may be implemented in any appropriate manner; and the logic network may be substituted by other units, e.g. programmable devices, providing they are capable of implementing the logic function described.
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- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Fluid-Damping Devices (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT373690 | 1990-11-15 | ||
| IT00373690A IT1244386B (it) | 1990-11-15 | 1990-11-15 | Procedimento per la realizzazione di elementi metallici a forcella per esempio del tipo da accoppiare allo stelo di un cilindro fluidodinamico ed impianto che attua tale procedimento. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0485889A1 true EP0485889A1 (fr) | 1992-05-20 |
Family
ID=11111585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP91118983A Withdrawn EP0485889A1 (fr) | 1990-11-15 | 1991-11-07 | Procédé de fabrication d'éléments métalliques en forme de fourche, comme des éléments fixés à la tige de piston d'un vérin hydraulique ou pneumatique, et système pour la réalisation du procédé |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP0485889A1 (fr) |
| IT (1) | IT1244386B (fr) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010142069A1 (fr) * | 2009-06-09 | 2010-12-16 | 上海昌强电站配件有限公司 | Procédé de façonnage d'une charnière de jonction par forgeage à chaud |
| CN102189142A (zh) * | 2011-03-08 | 2011-09-21 | 玉环县兴隆机械厂 | 一种万向节叉的加工工艺 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US1656930A (en) * | 1924-01-09 | 1928-01-24 | American Steel Foundries | Method for forging brake-beam fulcrums |
| US3101534A (en) * | 1958-06-30 | 1963-08-27 | Textron Inc | Method of producing wrist pins or similar articles |
| US3167859A (en) * | 1958-12-15 | 1965-02-02 | Textron Inc | Method of producing shouldered sleeves and similar articles |
| FR2335283A1 (fr) * | 1975-12-19 | 1977-07-15 | Press Und Stanzwerk Ag | Procede de fabrication d'une piece en forme de u et dispositif pour la mise en oeuvre du procede |
-
1990
- 1990-11-15 IT IT00373690A patent/IT1244386B/it active IP Right Grant
-
1991
- 1991-11-07 EP EP91118983A patent/EP0485889A1/fr not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US1656930A (en) * | 1924-01-09 | 1928-01-24 | American Steel Foundries | Method for forging brake-beam fulcrums |
| US3101534A (en) * | 1958-06-30 | 1963-08-27 | Textron Inc | Method of producing wrist pins or similar articles |
| US3167859A (en) * | 1958-12-15 | 1965-02-02 | Textron Inc | Method of producing shouldered sleeves and similar articles |
| FR2335283A1 (fr) * | 1975-12-19 | 1977-07-15 | Press Und Stanzwerk Ag | Procede de fabrication d'une piece en forme de u et dispositif pour la mise en oeuvre du procede |
Non-Patent Citations (2)
| Title |
|---|
| PATENT ABSTRACTS OF JAPAN vol. 10, no. 187 (M-493)(2243) 2 July 1986 & JP-A-61 030 252 ( TOYOTA MOTOR CORP. ) 12 February 1986 * |
| PATENT ABSTRACTS OF JAPAN vol. 7, no. 221 (M-246)(1366) 30 September 1983 & JP-A-58 113 633 ( YAMADA SEISAKUSHO K.K. ) 6 July 1983 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010142069A1 (fr) * | 2009-06-09 | 2010-12-16 | 上海昌强电站配件有限公司 | Procédé de façonnage d'une charnière de jonction par forgeage à chaud |
| CN102189142A (zh) * | 2011-03-08 | 2011-09-21 | 玉环县兴隆机械厂 | 一种万向节叉的加工工艺 |
Also Published As
| Publication number | Publication date |
|---|---|
| IT9003736A0 (it) | 1990-11-15 |
| IT9003736A1 (it) | 1992-05-15 |
| IT1244386B (it) | 1994-07-11 |
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| Date | Code | Title | Description |
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| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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| AK | Designated contracting states |
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| 17P | Request for examination filed |
Effective date: 19921029 |
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| K1C3 | Correction of patent application (complete document) published |
Effective date: 19920520 |
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| 17Q | First examination report despatched |
Effective date: 19940705 |
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| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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| 18D | Application deemed to be withdrawn |
Effective date: 19941116 |