EP0304363A1 - Power regulator, in particular for airport lighting - Google Patents

Abstract

A power current regulator, in particular for the marking of airports, comprises transformers in series with secondary sockets intermediate staggered according to digital weights. These intermediate sockets are each time selected by switches controlled by demultiplexers (DMX) preceded by memory-locks (MV) preceded by up-down counters (CD). These are actuated by a control circuit according to the current detected by a current transformer (TIC) put in series on the load (C).

Description

The invention relates to an electronic power regulating device, capable of operating at constant current, or at constant voltage.

It applies more particularly, but not exclusively, to a current regulator for the marking of airports.

In this field, ferroresonance regulators are known. They allow the load current to be kept constant when the load's current demand varies, provided that the supply voltage remains constant. This advantage is paid for by different counterparts: an overvoltage appears at the output terminals when the loop is accidentally opened while the load impedance becomes infinite; the cosine phi degrades strongly at low values of the charge and at low glosses; finally the yield is acceptable only for the full load intensity.

Magnetic amplifier regulators are also known. They have a high reliability even in difficult climatic conditions. However, their cosine phi is strongly degrades at low gloss. There is also an open circuit overvoltage, less significant than for ferro-resonance regulators. Finally, the efficiency is only acceptable for the nominal current at full load.

Finally, there are known the sine wave regulators cut by controlled switches such as thyristors. They have the advantage of great simplicity of construction and good performance. It is however necessary to adapt the output of the regulator to the value of the load, which can take amplitudes of four quarters, three quarters, half, a quarter and an eighth, in the particular case of an airport beacon. The drawback of these regulators lies in the creation of electromagnetic parasites which pollute the supply network, and also in the presence of rapid intensity variations which make the design of the protection circuits difficult.

The present invention aims to improve these latter types of regulators, in order to reduce the drawbacks.

One of the aims of the invention is thus to ensure that the efficiency and the power factor (cosine phi) practically do not degrade when passing from maximum brightness to lower gloss, in the case of airport signs, or when the load is reduced to its lowest value.

Another object of the invention is to obtain an absence of overvoltage at the opening of the charging circuit, on the one hand, as well as an absence of overcurrent harmful to lighting lamps, on the other hand.

The invention also aims to provide a regulator which is independent of the precise value of the mains supply voltage.

The invention also seeks to avoid any unnecessary fatigue lamps, thanks to a gradual rise in current.

The invention finally makes it possible to avoid the creation of parasites due to the steep current front, thanks to a sinusoidal shape as full as possible of the latter.

The subject of the present invention is a power current regulating device, of the type comprising:

- an AC power supply input,

- a first transformer whose primary is connected to this input and the secondary has staggered sockets,

- at least one intermediate transformer similar to the first transformer,

- a last transformer, the secondary of which is to be connected to the load to be regulated, through a device for measuring the load current or voltage,

- a series of controlled switches suitable for connecting one of the taps of each transformer to the next, and

means for controlling the conduction of these switches, one at a time per series,
characterized in that these control means include:

a comparator stage of the value measured by said member to a set value,

- a generator of a clock signal controlled at start-up by the zero crossing of the mains voltage, and then by the zero crossing of the current in the load,

- an up-down counting circuit capable of defining a count likely to evolve step by step according to the result of comparison, at the rate of the clock signal, and comprising as many up-down counters as there are taped transformers,

- lock memories linked to the parallel outputs of the up-down counters,

means capable of actuating the lock memories with at least one predetermined delay with respect to the clock signal,

- a delay circuit triggered with another predetermined delay, relative to the clock signal and for a chosen delay time,

- decoder means connected to the parallel outputs of the lock memories for actuating said series of switches during said time delay.

Advantageously, the taps of the different transformers are chosen to obtain a given precision, substantially constant throughout the extent of the variation of the current value in measured voltage, and the digital base of the up-down counting and decoding circuit are chosen from preferably according to the distribution of the sockets of the different transformers.

Advantageously, when the weight of an up-down counter increases, the updating of the corresponding lock memory takes place during the actuation phase of said series of corresponding switches by the corresponding decoder means.

Each controlled switch preferably comprises two thyristors mounted head to tail and controlled one relative to its secondary socket, the other relative to the thyristor output common; these two thyristors are advantageously each associated with a control transistor, with an individual supply for those on the socket side and a common supply for those on the common side; the two transistors are preferably isolated by respective opto-couplers from the decoder means, these optocouplers being validated by respective square-wave signals of opposite polarity, synchronous with the supply current passing through zero.

The predetermined delay can normally have a low or zero value, and a higher value in the case where the control of a new thyristor is deferred, and this predetermined delay can have increasing values when going from the memory-lock of the high weights to those of lower weights.

The device according to the invention advantageously includes monitoring means to prohibit, in particular at the level of the decoder means, the taking into account of a modified command for the state of the thyristors in the event of a thyristor short-circuited, or of load in short circuit.

The monitoring means can be sensitive to the existence of a reverse voltage across the terminals of each thyristor.

A short-circuit state of two thyristors can lead to the use of a circuit breaker capable of protecting at least this series.

Advantageously, the device according to the invention comprises an auxiliary contactor, disposed between a determined socket of a transformer and the corresponding pair of thyristors, said contact being closed when the circuit breaker is open so as to ensure degraded operation of the device.

A state of under intensity can lead to the use of a main contactor, preferably after a time delay.

An overcurrent state can cause the up-downcounting circuit to be reset to zero, and, in the event of a persistent overcurrent, the main contactor can be activated.

The pulses of the clock signal are preferably eliminated when they lie outside a window of selected duration, of a few milliseconds, relative to the zero crossings of the voltage.

• - la figure 1 est un schéma général d'un dispositif selon l'invention;
• - la figure 2 est un schéma électrique partiellement détaillé correspondant à l'ensemble logique de commandes de gachettes de la figure 1;
• - les figures 3a et 3b sont des schémas électriques partiel­lement détaillés correspondant au circuit de commandes séquen­tielles de la figure 1;
• - les figures 4, 5 et 6 sont des schémas électriques qui pré­cisent respectivement les circuits de mesure échantillonnés, les circuits de surveillance des thyristors et l'ensemble de commande gachettes de la figure 1; et
• - les figures 7 et 8 sont deux diagrammes temporels permet­tant de mieux comprendre l'invention.

Other characteristics and advantages of the invention will appear on examining the detailed description below, and the appended drawings, in which:

• - Figure 1 is a general diagram of a device according to the invention;
• - Figure 2 is a partially detailed electrical diagram corresponding to the logic set of trigger controls of Figure 1;
• - Figures 3a and 3b are circuit diagrams partially detailed corresponding to the sequential control circuit of Figure 1;
• - Figures 4, 5 and 6 are electrical diagrams which respectively specify the sampled measurement circuits, the thyristor monitoring circuits and the trigger control assembly of Figure 1; and
• - Figures 7 and 8 are two time diagrams to better understand the invention.

The appended drawings essentially provide certain information. Consequently, they can be used not only to improve understanding of the detailed description below, but also to contribute to the definition of the invention, if necessary.

In FIG. 1, an AC mains supply at 220 Volts is available between the phase PH and neutral N terminals. It supplies all of the ETCP power transformers and switches via a contactor main CP under the control of a CCP circuit.

Downstream of the contactor is a first transformer T2, which can be an autotransformer, the secondary winding of which has five sockets, for example. These five sockets are respectively connected, from the lowest voltages to the highest voltages, to controlled switches IC0-2 to IC4-2, via a respective circuit breaker (DS0-2 to DS4-2). The outputs of the controlled switches are connected to a common, to be applied to a resistance-capacitance filtering network noted RCP2, as well as to the primary of an autotransformer T1. This one is mounted like the previous one with five controlled switches IC0-1 to IC4-1, a circuit breaker (DS0-1 to DS4-1) and a capacity resistance circuit RCP1, and a third autotransformer T0. It is mounted like the previous ones with controlled switches IC0-0 to IC4-0, a circuit breaker (DS0-0 to DS4-0) and a resistance-capacity network RCP0.

The staggering of the taps on the different transformers are defined to allow digital control, for example as follows: let e be the relative precision desired for regulation; we denote by K the difference between 1 and this precision (doubled if it is counted more and less).

U0 denotes the full nominal secondary voltage of transformer T0. The intermediate sockets will then be chosen to supply the voltage U0xK, U0xK², U0xK³ and U0xK⁴ in addition.

Doing the same for the secondary voltage U1 of the transformer T1, it supplies the voltages U1x1, U1xK⁵, U1xK¹⁰, U1xK¹⁵ and U1xK²⁰.

Finally, with regard to the transformer T2 and its secondary voltage U2, the sockets U2, U2xK²⁵, U2xK⁵⁰, U2xK⁷⁵ and U2xK¹⁰⁰ will be established.

Figure 1 also shows the TAC load matching transformer, the primary of which is supplied by the previous assembly, and the secondary of which supplies the load through an ICT current transformer, the secondary of which supplies, in series with a current ammeter. table MA, a second TIM measurement intensity transformer with two secondary.

• a) le circuit de mesure échantillonnée CME alimenté par le premier des deux secondaires IM1 et contrôlé par le cir­cuit de commande de brillance CCB. L'homme de l'art com­prendra que l'on peut en effet ajuster la brillance en agissant sur la valeur mesurée plutôt que sur la valeur de consigne.
• b) le circuit de commandes séquentielles CCS, alimenté par le deuxième secondaire IM2 et par un transformateur de tension TU, fournissant en particulier le signal d'horloge SH ayant lieu, au démarrage, au passage à zéro de la ten­sion secteur et ensuite, au passage à zéro du courant dans la charge.
• c) le circuit de surveillance des thyristors CST qui vérifie avant chaque commande qu'il n'y a pas de thyristors en court-circuit.

The lower right half of Figure 1 shows:

• a) the sampled measurement circuit CME supplied by the first of the two secondary IM1 and controlled by the brightness control circuit CCB. Those skilled in the art will understand that the brightness can in fact be adjusted by acting on the measured value rather than on the set value.
• b) the sequential control circuit CCS, supplied by the second secondary IM2 and by a voltage transformer TU, supplying in particular the clock signal SH taking place, at start-up, at the zero crossing of the mains voltage and then, at zero current crossing in the load.
• c) the thyristor monitoring circuit CST which checks before each command that there are no thyristors in short circuit.

And the lower left half of Figure 1 shows the ELCG trigger control logic assembly consisting of:

a CCD up-down circuit capable of defining a count capable of evolving step by step at the rate of the clock signal SH and according to the change CH and up / down U / D signals,

- a CMV memory-lock circuit connected to the parallel outputs of the up-down counters and whose updating is effected by the action of an updating control signal ("strobe") ST. This ST signal to take place:

- either immediately after the clock signal if there is no change in counting or if the change corresponds to a reduction in voltage on the tap transformer,

- either with a predetermined delay R if there is a change in metering and if this change corresponds to an increase in voltage on the tap transformer,

a circuit of DMX demultiplexers (decoding means) connected to the outputs of the lock memories and whose own outputs are conditioned by inhibition signals INH whose delay time t starts immediately after the clock signal SH,

- a CCG trigger control circuit connected to the outputs of the demultiplexers by means of opto-couplers and whose function is to actuate said series of switches.

The sampled measurement circuit CME, the brightness control circuit CCB, the sequential control circuit CCS, the thyristor monitoring circuit CST and the logic trigger control assembly ELCG constitute control means MC of the switches.

According to a preferred embodiment, the predetermined delay R has a value of the order of 1 to 2 milliseconds and the duration of the time delay t of the trigger control signal, a value of the order of 5 milliseconds.

Figure 2 specifies this logic trigger control assembly by highlighting the three up-down counters CD-2, CD-1 and CD-0, as well as their upstream link with the comparison circuits and their downstream link with the lock memories MV-2, MV-1 and MV-0 respectively updated by the update control signals ST2, ST1 and ST0.

The count values are decoded by the DMX2, DMX1 and DMX0 demultiplexers under the respective control of the inhibition signals INH-2, INH-1, INH-0.

The decoded values X0 to X4 of each of the three counting groups are applied to the trigger control circuits of each series of controlled switches.

In this figure 2, the composition of the logic control circuit shows:

- a thyristor control logic under the control of signals 0K2, 0K1 and 0K0 coming from the thyristor monitoring circuits,

- an update command MD of the lock memories under the control of the direction of counting change,

- comparison circuits which generate the CH change, U / D rise / fall, RST reset signals, as well as other signals not mentioned in FIG. 2, such as overcurrent, undercurrent, immediate stop , especially.

Figures 3 a and 3 b give details of the CCS sequential control circuits.

From the voltage signal SU, emitted by the secondary of the voltage transformer TU, the voltage zero detection circuit DZT supplies the two signals A and B in slots of opposite phase respectively which will also be used in the control assembly triggers (defined during the explanation of Figure 6). The sum of signals A and B controls a time window of 1 to 2 milliseconds starting at zero voltage.

The clock signal SH is the logic output of a monostable circuit with forcing at zero MT1. The triggering of this monostable is ensured by the zero crossing of the voltage (start of the window). It drops out after 1 to 2 milliseconds (system initialization), or before, as soon as a zero crossing of the current is indicated by the signal Io (steady state).

The filtering of the clock pulses by a window of selected duration has the advantage of eliminating the parasitic pulses likely to cause the unwanted control of another pair of thyristors by risking creating a short circuit between taps of the same transformer .

The signal SH supplies the down-counters on the one hand and, on the other hand, a series of staggered timers intended to produce the signals SAMV-2, SAMV-1 and SAMV-0, as well as the signals SCG-2, SCG -1 and SCG-0, as shown in Figure 3a. This series of staggered timers is produced by a timer circuit D2.

FIG. 3b represents the simplification introduced in the production of the preceding signals when the thyristor monitoring is removed.

Figure 4 gives the details of the CME sampled measurement circuits.

From the current signal IM1, the current measurement circuit CMC provides a proportional DC voltage signal which will be divided into a brightness selection circuit CSB under the control of the brightness control circuit CCB; the effective value of this resulting signal will be worked out in the effective value circuit CVE. At each clock signal, the new value of the sampled measurement signal SME will be available for the comparison circuits.

CMC, CSB, CCB, CVE circuits constitute a compa rator (CN0).

Figure 5 gives details of the CST thyristor monitoring circuits.

The principle is as follows: if the thyristor which has just operated has not short-circuited during its operation during the alternation which has just ended, it occurs when the load current is interrupted a overvoltage across the next transformer. These overvoltage signals SST-2, SST-1 and SST-0 are standardized by dividing them respectively by coefficients K2, K1 and K0 specific to each of the three attenuation stages. Each of these standardized signals is compared to an adjustable setpoint in comparators whose outputs 0K2, 0K1 and 0K0 are introduced into the control logic circuit to authorize or not the command of the next alternation. In practice, as illustrated in FIG. 5, it suffices for a common division by the product K2 K1 K0, which is little different from K2.

Figure 6 gives the detail of the set of ECG trigger commands:

At the bottom of Figure 6, we find one of the demultiplexers denoted DMX-i. The upper part therefore concerns the thyristors connected to the output of only one of the transformers; the suffix preceded by a dash is therefore ignored in Figure 6.

The secondary P4 socket of the transformer concerned is assumed to be the one providing the highest voltage. The taps are then considered in descending order until the tap P0 which provides the lowest voltage, the other terminal of the secondary being noted C.

Between socket P4 and common C is first a thyristor T4 + mounted conductor between P4 and C, and conversely a thyristor T4- mounted conductor between C and P4. In series on the triggers of thyristors T4 + and T4- are res Pectively the resistance R4 + to the common and the resistance R4- to the P4 socket. The triggers of these two thyristors are moreover connected to the emitters of the transistors Q4 + and Q4-, and these transistors, of the NPN type, are respectively controlled between bases and emitters by optocouplers 0C4 + and 0C4-. The whole of this command constitutes the controlled switch IC4.

The same assembly is repeated for the switches controlled IC3 to IC0 and will therefore not be described again.

It will simply be observed that the transistors Q4-, Q3-, Q2-, Q1 and Q0- have respective supplies AL4, AL3, AL2, AL1 and AL0, these supplies being referred to the voltages of the sockets P4 to P0. On the other hand, the other transistors can have a common supply ALC compared to common C.

The 0C optocouplers are validated by a voltage A if they have the suffix + or by a voltage B if they have the suffix -. These voltages A and B, generated as described above, are sector synchronous and of opposite polarity.

Finally, each pair of opto-couplers like 0C4 is supplied by a respective output from the DMX demultiplexer.

In order to improve the operation of the device, in the event of an overcurrent, a reset of the up-down counters is carried out with execution of this order by the thyristors; and if the overcurrent state persists, the main contactor CP opens.

0n protects the thyristors of the same series against internal short circuits by using local circuit breakers placed between the taps of each transformer and the thyristors. However, to allow degraded operation in the event of a thyristor short circuit, a direct connection is reserved between a determined tap of the transformer T2 and the corresponding thyristor pair (for example IC2-2), whose trigger control is automatically performed by an auxiliary contact linked to the circuit breaker group. This auxiliary contact is closed when the circuit breaker group is open. This arrangement allows degraded operation at three levels (because there are three transformers T2, T1, T0), the last level corresponding to the supply of the output transformer by a fraction of the supply voltage of the network.

Furthermore, to protect the thyristors, the device includes monitoring means to prohibit, in particular at the level of the decoder means, the taking into account of a modified thyristor control, if the thyristor which has just operated is in short -circuit.

The monitoring means used for this purpose may be of a different nature to characterize the absence of a short-circuit of the last thyristor having led: either the existence of a reverse voltage at the terminals of the thyristor, or the cancellation of the current at the end of time Tq, i.e. the presence of an overvoltage across the load when the current is canceled. The latter is preferable.

At this point in the description of the different parts of the device, the operation of the regulator can be summarized as follows:

When the device is switched on, all functions are reset to zero, in particular the up-counters and there is no current in the load yet. The clock signal SH is obtained from the zero crossing of the line voltage signal and triggers all the sequential commands which authorize the updating of the lock memories by the update command signal and the trigger control via the demultiplexers. for the entire duration of the reverse inhibition signal. The thyristors connected to the lowest taps of the transformers are conducting and the smallest voltage is applied to the transformer adaptation of TAC loads: this results in a generally very low current in the load but nevertheless sufficient to supply current measurement signals IM1 and IM2. In particular IM2 will make it possible to control the clock signal SH at the zero crossing of the current and from there the incrementation of the up-counters will occur at each alternation of the current until the moment when the value of the current has reached the setpoint value. At this stage of operation, the regulator stabilizes unless the value of the mains voltage changes enough to vary the load current outside its margin of precision, or if the load changes enough to produce the same effects, or finally if the selected brightness selection is changed.

A more detailed operation of the device will be described on the basis of the time diagrams represented in FIGS. 7 and 8, these figures being respectively characteristic of the operation "with" or "without" monitoring of the thyristors.

In these figures, three configurations of the regulator are shown. The left-hand side illustrates a configuration in which the up-down counter 0 has increased by one unit while the other two are not modified. The middle part of the figures illustrates a configuration in which the up-down counter 0 decreases by one unit, while the up-down counter 1 increases by one and the up-down counter 2 is not modified. Finally, the right-hand part illustrates a configuration in which the up-down counter 0 has decreased by one unit, the up-down counter 1 decreases by a unit and the up-down counter 2 increases by a unit.

The direction of variation of each up-down counter is determined from the overall value of the up-down counting circuit after the change, knowing that the overall direction of variation (increase or decrease) is known and no change is made. than one unit at a time.

On each part of Figure 7, the top diagram illustrates (very schematically) the current through the load. The three lines below illustrate the three change signals CH-2, CH-1, CH-0 respectively. The next line illustrates the SH clock signal. The following three groups of three lines respectively illustrate, for the three up-downcounters i the signal 0Ki, the muting signal INH-i and the update control signal ST-i.

We find an identical arrangement in FIG. 8, but the 0Ki signals no longer exist because there is no monitoring of the thyristors.

If we now refer to FIG. 7, and more particularly to the left part, we therefore see that there is no modification of counting on up-down counters 1 and 2 and modification on up-down counting down 0 illustrated by signal CH-0.

The clock signal SH appeared at the zero crossing of the current.

The 0K2 signal is sent to signal that there are no thyristors short-circuited (DV off-hook on the first line in Figure 7) and that one could control.

The INH-2 trigger control order takes place 50 microseconds after the end of the 0K2 signal. The update control signal ST-2 takes place immediately after the rise of the signal SH because there is no change in counting.

The same configuration is found for up-down counter 1 because there is no change in counting.

On the other hand, as regards the up-down counter 0, since there is an increase in unit, the update control signal ST-0 will be emitted, during the actuation phase series of switches by demultiplexers (DMX), that is to say during the low state phase of the signal INH-0. Thus the ST-0 signal is shifted by half a millisecond relative to the fall of the INH-0 signal, which ensures better voltage continuity in the regulator. In all diagrams, the low state phase of the INH-i signal lasts 5 ms. The rise in signal ST-0 corresponds to a small current fault across the load.

The same operating principles are observed in the middle and right parts of FIG. 7. The update control signal is not shifted when the value of the corresponding up-down counter is stationary or decreases.

FIG. 8 illustrates the unattended operation of the thyristors, and is simplified compared with FIG. 7. The interpretation of the signals represented is identical to that of FIG. 7.

Those skilled in the art will understand that the circuit which has just been described satisfies the aims of the invention particularly well.

This invention can be the subject of various variants.

For example, the extinction state of the thyristors (not short-circuited) can also be detected by the cancellation of the voltage between the common output C and the neutral, or by the cancellation of the current in each thyristor concerned.

Claims (12)

1. Power current regulating device, of the type comprising:

- an AC power supply input,

- a first transformer (T2) whose primary is connected to this input and the secondary has staggered sockets,

- at least one intermediate transformer (T1, T0) similar to the first transformer,

- a last transformer (TAC) whose secondary is to be connected to the load to be regulated, through a measuring device (TIC) of the load current or voltage,

- a series of controlled switches (IC) capable of connecting one of the taps of each transformer to the next, and

- control means (MC) for the conduction of these switches, one per series,
characterized in that these control means include:

- a comparator stage (CN0) of the value measured by said member to a set value,

- a generator of a clock signal (SH) controlled at start-up by the zero crossing of the mains voltage, and then by the zero crossing of the current in the load,

- an up-down counting-down circuit (CCD) capable of defining a counting capable of evolving step by step according to the result of the comparison, at the rate of the clock signal, and comprising as many up-down counters (CD) as it there are plug transformers,

- lock memories (MV) connected to the parallel outputs of the up-down counters,

means (MD) capable of actuating the lock memories with at least one predetermined delay with respect to the clock signal, according to the direction of variation of the counters,

- a delay circuit (D2) triggered, with another predetermined delay, relative to the clock signal, and for a chosen delay duration,

- decoder means (DMX) connected to the parallel outputs of the lock memories for actuating said series of switches during said time delay. 2. Device according to claim 1, characterized in that the taps of the various transformers are chosen to obtain a given precision, substantially constant throughout the extent of the variation of the measured current or voltage value, and
in that the digital base of the up-down counting and decoding circuit are chosen according to the distribution of the taps of the different transformers. 3. Device according to one of claims 1 or 2, characterized in that, when the weight of an up-down counter increases, the updating of the corresponding memory-lock takes place during the actuation phase of said series of corresponding switches by the corresponding decoder means. 4. Device according to one of claims 1 to 3, characterized in that each controlled switch (IC) comprises two thyristors (T +, T-) mounted head to tail and controlled one relative to its secondary socket, l other with respect to the thyristor output common, in that these two thyristors are each associated with a control transistor (Q +, Q-), with an individual supply for those on the side sockets and a common power supply for those on the common side, in that the two transistors are isolated by respective opto-couplers (0C +, 0C-) from the decoder means, these opto-couplers being validated by niche signals respective opposite polarity, synchronous zero crossings of the supply current. 5. Device according to one of claims 1 to 4, characterized in that the predetermined delay normally has a low or zero value and a higher value in the case where the control of a new thyristor is deferred, and

in that this predetermined delay has increasing values when one goes from the memory lock of the most significant to those of the least significant. 6. Device according to one of claims 1 to 5, characterized in that it comprises monitoring means to prohibit, in particular at the level of the decoder means, the taking into account of a modified command for the state of the thyristors in the event of a thyristor short-circuited, or of a load short-circuited. 7. Device according to claim 6, characterized in that the monitoring means are sensitive to the existence of a reverse voltage at the terminals of each thyristor. 8. Device according to one of claims 6 and 7, characterized in that a short-circuit state of two thyristors leads to the use of a circuit breaker capable of protecting at least this series. 9. Device according to claim 8, characterized in that it comprises an auxiliary contactor, disposed between a determined socket of a transformer and the corresponding thyristor pair, said contact being closed when the circuit breaker is open so as to ensure operation of graded device. 10. Device according to one of claims 1 to 9, characterized in that a state of under intensity causes the implementation of a main contactor (CP), preferably after time delay. 11. Device according to one of claims 1 to 10, characterized in that an overcurrent state results in the reset of the up-downcounting circuit, and, in the event of persistent overcurrent, the operation of the main contactor ( CP). 12. Device according to one of claims 1 to 11, characterized in that the pulses of the clock signal are eliminated when they are outside a window of selected duration, of a few milliseconds, relative to the passages by zero voltage.

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