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EP0360887A1 - CMOS voltage reference - Google Patents

CMOS voltage reference Download PDF

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Publication number
EP0360887A1
EP0360887A1 EP88115839A EP88115839A EP0360887A1 EP 0360887 A1 EP0360887 A1 EP 0360887A1 EP 88115839 A EP88115839 A EP 88115839A EP 88115839 A EP88115839 A EP 88115839A EP 0360887 A1 EP0360887 A1 EP 0360887A1
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EP
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Prior art keywords
circuit
output
field effect
bipolar
transistor
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EP88115839A
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German (de)
French (fr)
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EP0360887B1 (en
Inventor
Heinz Zitta
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Siemens AG
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Siemens AG
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Priority to EP88115839A priority Critical patent/EP0360887B1/en
Priority to AT88115839T priority patent/ATE93634T1/en
Priority to DE88115839T priority patent/DE3883536D1/en
Priority to JP1243254A priority patent/JP2759905B2/en
Priority to US07/412,894 priority patent/US4931718A/en
Publication of EP0360887A1 publication Critical patent/EP0360887A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement in complementary MOS technology according to the preamble of claim 1.
  • Bandgap resp. Bandgap circuits are known and are described, for example, in the book "Semiconductor Circuit Technology” by U. Tietze and Ch. Schenk, 7th edition, Springer-Verlag, Berlin, Heidelberg, New York 1985, pages 534 ff.
  • bandgap circuits can be used to generate reference voltages which, independently of the temperature coefficients of the components used in them, provide a temperature-independent reference voltage.
  • the principle of such circuits is to compensate for the negative temperature coefficient of the base-emitter diode voltage of a bipolar transistor by adding a voltage with a correspondingly positive temperature coefficient by using a second transistor with a different base-emitter voltage and an emitter resistor.
  • CMOS complementary metal-oxide-semiconductor
  • the different base-emitter voltages of the bipolar transistors are generated, for example, by different area ratios of the emitter zones.
  • the circuit relates to a p-well CMOS technology, as can be implemented, for example, on an n ⁇ -conductive substrate or a correspondingly conductive epitaxial layer.
  • N-channel field effect transistors are produced by introducing p+ zones for the source and drain into the substrate.
  • Bipolar transistors can be produced in this technique by introducing a p-type well on the n-type substrate and in turn a n-type connection zone. This creates a substrate-npn transistor, in which the n+-zone is the emitter, the p ⁇ -well is the base and the substrate is the collector. The collector or the substrate must be connected to the positive operating voltage in order to reliably block parasitic diodes between the p-wells and the substrate.
  • the CMOS bandgap circuit known from the aforementioned prior publication has the base connections of the two npn transistors as a reference point for the bandgap voltage. Usually this point is applied to the reference potential, i. H. to ground.
  • the output connection of the bandgap voltage is at the connection point of the drain connection of a MOS transistor with a resistor, both of which are arranged in the emitter circuit of a bipolar transistor.
  • the known CMOS bandgap circuit requires a positive and a negative supply voltage with respect to the reference potential.
  • bandgap circuits which manage with only an unipolar supply voltage, but which have to do without bipolar transistors.
  • these circuits do not achieve the temperature stability of bipolar bandgap circuits.
  • the invention has for its object to provide a CMOS voltage reference circuit that manages with an only unipolar supply voltage and achieves the temperature stability of bipolar bandgap circuits.
  • the circuit arrangement according to the invention has the advantage that it can be operated with a low and unipolar voltage with respect to the reference potential and that it can also be used to implement higher reference voltages than the bandgap voltage of the semiconductor material.
  • Embodiments of the invention are characterized in the subclaims.
  • the bandgap circuit contains two bipolar transistors T1 and T2 with different base-emitter voltages. Both collector connections are connected to the VDD terminal, which has a positive potential compared to the reference voltage.
  • a resistor R3 and in series the output circuit of a field effect transistor M1 is arranged in the emitter circuit of transistor T1, the source of which is connected to terminal VSS.
  • the VSS terminal is at reference potential, i. H. grounded.
  • the series circuit of two resistors R1 and R2 and the output circuit of another field effect transistor M2 is arranged in the output circuit of transistor T2.
  • the source connection of M2 is also at the VSS terminal.
  • the bandgap voltage UG must be tapped at the drain terminal of the transistor M2, to which the terminal VG1 corresponds, based on the base terminals of the bipolar transistors T1 and T2, to which the terminal VG2 corresponds.
  • the output of the bandgap circuit VG1 is now fed back to the reference point VG2.
  • the connection VG1 is connected to an input of a second operational amplifier OP2, the other input of which lies at the dividing point of an ohmic voltage divider consisting of the resistors R4 and R5.
  • the ohmic voltage divider is between the connection VG2 and the terminal VSS, i. H. Ground, switched.
  • the output of the operational amplifier OP2 is on the connection VG2, i. H. fed back to the base connections of the bipolar transistors T1 and T2.
  • the output of the second operational amplifier OP2 is connected to the terminal VR, at which the temperature-independent reference voltage UR can be tapped with respect to the reference potential at the terminal VSS.
  • the relationship between the temperature-independent reference voltage UR and the bandgap voltage UG is established by the ohmic voltage divider from the resistors R4 and R5.
  • the temperature-independent reference voltage UR is thus calculated from the product of the bandgap voltage UG on the one hand and the sum of the two resistors R4 and R5 in relation to the resistor R4 on the other hand.
  • An embodiment of the invention according to the figure contains a startup circuit IA, which is connected between the output terminal VR of the second operational amplifier OP2 and the terminal VDD with the relatively positive supply voltage potential.
  • This start-up circuit IA is drawn as a current source and can be implemented, for example, by a current source transistor or a resistor.
  • the starting circuit IA enables the reference voltage UR to be used as the operating voltage of the bandgap circuit, so that the actual reference voltage source can be operated from the two bipolar transistors T1 and T2 with the stabilized output reference voltage. This results in excellent suppression of input voltage fluctuations at the VDD terminal.
  • the start-up circuit IA is necessary since the operating voltage derived from the temperature-independent reference voltage UR must first be built up when a voltage is applied to the VDD terminal.
  • the circuit according to the embodiment of the figure makes it possible to dispense with a separate connection terminal VR, so that the CMOS voltage reference according to the invention has only the two connection terminals VDD and VSS to the outside.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
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Abstract

A circuit configuration in complementary MOS technology for generating a reference voltage independent of temperature with the aid of a bandgap circuit includes first and second bipolar transistors having first and second base-to-emitter threshold voltages and interconnected base connections, and first and second field effect transistors. A first series circuit includes the output circuit of the first bipolar transistor, a first resistor being connected to the first bipolar transistor and defining a first connecting point therebetween, and the output circuit of the first field effect transistor being connected between terminals of a supply voltage source. A second series circuit which is parallel to the first includes the output circuit of the second bipolar transistor, series-connected second and third resistors defining a second connecting point therebetween, and the output circuit of the second field effect transistor. An operational amplifier has inputs connected to the first and second connecting points and an output controlling the field effect transistors. A bandgap circuit has an output at the drain connection of the second field effect transistor being fed back to the base connections of the bipolar transistors.

Description

Die Erfindung betrifft eine Schaltungsanordnung im komplementärer MOS-Technik nach dem Oberbegriff des Patentanspruchs 1.The invention relates to a circuit arrangement in complementary MOS technology according to the preamble of claim 1.

Bandgap-bzw. Bandabstands-Schaltungen sind bekannt und bei­spielsweise in dem Buch "Halbleiter-Schaltungstechnik" von U. Tietze und Ch. Schenk, 7. Auflage, Springer-Verlag, Berlin, Heidelberg, New York 1985, Seiten 534 ff. beschrieben.Bandgap resp. Bandgap circuits are known and are described, for example, in the book "Semiconductor Circuit Technology" by U. Tietze and Ch. Schenk, 7th edition, Springer-Verlag, Berlin, Heidelberg, New York 1985, pages 534 ff.

In der vorgenannten Veröffentlichung ist ausgeführt, daß mit derartigen Bandgap-Schaltungen Referenzspannungen erzeugt werden können, die unabhängig von Temperaturkoeffizienten der in ihr verwendeten Bauelemente eine temperaturunabhängige Re­ferenzspannung liefern. Das Prinzip derartiger Schaltungen be­steht darin, den negativen Temperaturkoeffizienten der Basis-­Emitter-Diodenspannung eines Bipolartransistors durch Addition einer Spannung mit entsprechend positivem Temperaturkoeffi­zienten zu kompensieren, indem ein zweiter Transistor mit an­derer Basis-Emitter-Spannung und einem Emitterwiderstand be­nutzt wird.In the aforementioned publication it is stated that such bandgap circuits can be used to generate reference voltages which, independently of the temperature coefficients of the components used in them, provide a temperature-independent reference voltage. The principle of such circuits is to compensate for the negative temperature coefficient of the base-emitter diode voltage of a bipolar transistor by adding a voltage with a correspondingly positive temperature coefficient by using a second transistor with a different base-emitter voltage and an emitter resistor.

Aus der Veröffentlichung IEEE ISSC Vol.SC-20, No. 6, Dec. 1985, pp. 1151-1157 ist eine Bandgap-Schaltung in komplementärer CMOS-Technik gemäß dem Oberbegriff des Patentanspruchs 1 be­kannt. Die unterschiedlichen Basis-Emitter-Spannungen der Bipolartransistoren werden beispielsweise durch unterschied­liche Flächenverhältnisse der Emitterzonen erzeugt. Die Schaltung bezieht sich auf eine p-Wannen-CMOS-Technik, wie sie beispielsweise auf einem n⁻-leitenden Substrat oder einer ent­sprechend leitfähigen epitaktischen Schicht realisiert werden kann. n-Kanal-Feldeffekttransistoren werden erzeugt, indem p⁺-Zonen für Source und Drain in das Substrat eingebracht werden. Zur Herstellung von p-Kanal-Feldeffekttransistoren ist ist eine p⁻-leitende Wanne erforderlich, in die für die Source-­und Drainanschlüsse n⁺-leitende Zonen eingebracht werden. Bipo­lartransistoren lassen sich in dieser Technik erzeugen, indem auf dem n⁻-leitenden Substrat eine p⁻-leitende Wanne und in die­se wiederum eine n⁺-leitende Anschlußzone eingebracht wird. Auf diese Weise entsteht ein Substrat-npn-Transistor, bei dem die n⁺-Zone den Emitter, die p⁻-Wanne die Basis und das Substrat den Kollektor darstellt. Der Kollektor bzw. das Substrat müssen an die positive Betriebsspannung angeschlossen werden, um parasitä­re Dioden zwischen den p-Wannen und dem Substrat sicher zu sper­ren.From the publication IEEE ISSC Vol.SC-20, No. 6, Dec. 1985, pp. 1151-1157 a bandgap circuit in complementary CMOS technology according to the preamble of claim 1 is known. The different base-emitter voltages of the bipolar transistors are generated, for example, by different area ratios of the emitter zones. The circuit relates to a p-well CMOS technology, as can be implemented, for example, on an n⁻-conductive substrate or a correspondingly conductive epitaxial layer. N-channel field effect transistors are produced by introducing p⁺ zones for the source and drain into the substrate. For the production of p-channel field effect transistors a p⁻-conducting trough is required, into which n⁺-conducting zones are introduced for the source and drain connections. Bipolar transistors can be produced in this technique by introducing a p-type well on the n-type substrate and in turn a n-type connection zone. This creates a substrate-npn transistor, in which the n⁺-zone is the emitter, the p⁻-well is the base and the substrate is the collector. The collector or the substrate must be connected to the positive operating voltage in order to reliably block parasitic diodes between the p-wells and the substrate.

Die aus der genannten Vorveröffentlichung bekannte CMOS-Bandgap-­Schaltung hat als Bezugspunkt für die Bandgap-Spannung die Basis­anschlüsse der beiden npn-Transistoren. Üblicherweise legt man diesen Punkt an das Bezugspotential, d. h. an Masse. Der Ausgangs­anschluß der Bandgap-Spannung liegt am Verbindungspunkt des Drainanschlusses eines MOS-Transistors mit einem Widerstand, die beide im Emitterkreis eines Bipolartransistors angeordnet sind. In jedem Fall ist für die bekannte CMOS-Bandgap-Schaltung eine bezüglich des Bezugspotentials positive und eine negative Ver­sorgungsspannung erforderlich.The CMOS bandgap circuit known from the aforementioned prior publication has the base connections of the two npn transistors as a reference point for the bandgap voltage. Usually this point is applied to the reference potential, i. H. to ground. The output connection of the bandgap voltage is at the connection point of the drain connection of a MOS transistor with a resistor, both of which are arranged in the emitter circuit of a bipolar transistor. In any case, the known CMOS bandgap circuit requires a positive and a negative supply voltage with respect to the reference potential.

Andererseits sind Bandgap-Schaltungen bekannt, die mit einer nur unipolaren Versorgungsspannung auskommen, dafür jedoch auf bipolare Transistoren verzichten müssen. Diese Schaltungen erreichen jedoch nicht die Temperaturstabilität von bipolaren Bandgap-Schaltungen.On the other hand, bandgap circuits are known which manage with only an unipolar supply voltage, but which have to do without bipolar transistors. However, these circuits do not achieve the temperature stability of bipolar bandgap circuits.

Der Erfindung liegt die Aufgabe zugrunde, eine CMOS-Spannungs-­Referenzschaltung anzugeben, die mit einer nur unipolaren Versorgungsspannung auskommt und die Temperaturstabilität bipolarer Bandgap-Schaltungen erreicht.The invention has for its object to provide a CMOS voltage reference circuit that manages with an only unipolar supply voltage and achieves the temperature stability of bipolar bandgap circuits.

Diese Aufgabe wird bei einer Schaltungsanordnung der eingangs genannten Art erfindungsgemäß durch die Merkmale des kenn­zeichnenden Teils des Patentanspruchs 1 gelöst.This object is achieved according to the invention in a circuit arrangement of the type mentioned at the outset by the features of the characterizing part of patent claim 1.

Die erfindungsgemäße Schaltungsanordnung besitzt den Vorteil, daß sie sich mit einer niedrigen und dazu unipolaren Spannung bezüglich des Bezugspotentials betreiben läßt und daß sich mit ihr auch höhere Referenzspannungen als die Bandgap-Spannung des Halbleitermaterials realisieren läßt.The circuit arrangement according to the invention has the advantage that it can be operated with a low and unipolar voltage with respect to the reference potential and that it can also be used to implement higher reference voltages than the bandgap voltage of the semiconductor material.

Ausgestaltungen der Erfindung sind in Unteransprüchen gekenn­zeichnet.Embodiments of the invention are characterized in the subclaims.

Die Erfindung wird im folgenden anhand eines in der Figur der Zeichnung dargestellten Ausführungsbeispiels näher erläutert.The invention is explained below with reference to an embodiment shown in the figure of the drawing.

Gemäß der Figur enthält die Bandgap-Schaltung zwei bipolare Transistoren T1 und T2 mit unterschiedlichen Basis-Emitter-­Spannungen. Beide Kollektoranschlüsse sind an die Klemme VDD angeschlossen, die gegenüber der Bezugsspannung ein positives Potential führt. Im Emitterkreis des Transistors T1 ist ein Widerstand R3 und in Reihe dazu der Ausgangskreis eines Feld­effekttransistors M1 angeordnet, dessen Source an der Klemme VSS liegt. Die Klemme VSS ist an Bezugspotential, d. h. an Masse gelegt. Im Ausgangskreis des Transistors T2 ist die Reihenschaltung zweier Widerstände R1 und R2 sowie des Aus­gangskreises eines anderen Feldeffekttransistors M2 ange­ordnet. Der Sourceanschluß von M2 liegt ebenfalls an der Klemme VSS. Die Verbindungspunkte des Emitters von T1 mit dem Wider­stand R3 einerseits und der beiden Widerstände R1 und R2 andererseits führen auf die Eingänge eines Operationsverstär­kers OP1, dessen Ausgang die Transistoren M1 und M2 steuert. Am Drainanschluß des Transistors M2, dem der Anschluß VG1 ent­spricht, ist bezogen auf die Basisanschlüsse der Bipolartran­sistoren T1 und T2, denen der Anschluß VG2 entspricht, die Bandgap-Spannung UG abzugreifen.According to the figure, the bandgap circuit contains two bipolar transistors T1 and T2 with different base-emitter voltages. Both collector connections are connected to the VDD terminal, which has a positive potential compared to the reference voltage. A resistor R3 and in series the output circuit of a field effect transistor M1 is arranged in the emitter circuit of transistor T1, the source of which is connected to terminal VSS. The VSS terminal is at reference potential, i. H. grounded. The series circuit of two resistors R1 and R2 and the output circuit of another field effect transistor M2 is arranged in the output circuit of transistor T2. The source connection of M2 is also at the VSS terminal. The connection points of the emitter of T1 with the resistor R3 on the one hand and the two resistors R1 and R2 on the other hand lead to the inputs of an operational amplifier OP1, the output of which controls the transistors M1 and M2. The bandgap voltage UG must be tapped at the drain terminal of the transistor M2, to which the terminal VG1 corresponds, based on the base terminals of the bipolar transistors T1 and T2, to which the terminal VG2 corresponds.

Erfindungsgemäß ist nun der Ausgang der Bandgap-Schaltung VG1 auf den Bezugspunkt VG2 rückgekoppelt. Dazu ist der Anschluß VG1 auf einen Eingang eines zweiten Operationsverstärkers OP2 geschaltet, dessen anderer Eingang am Teilerpunkt eines ohm­schen Spannungsteilers aus den Widerständen R4 und R5 liegt.According to the invention, the output of the bandgap circuit VG1 is now fed back to the reference point VG2. For this purpose, the connection VG1 is connected to an input of a second operational amplifier OP2, the other input of which lies at the dividing point of an ohmic voltage divider consisting of the resistors R4 and R5.

Der ohmsche Spannungsteiler ist zwischen den Anschluß VG2 und die Klemme VSS, d. h. Masse, geschaltet. Der Ausgang des Ope­rationsverstärkers OP2 ist auf den Anschluß VG2, d. h. auf die Basisanschlüsse der Bipolartransistoren T1 und T2 rückgeführt.The ohmic voltage divider is between the connection VG2 and the terminal VSS, i. H. Ground, switched. The output of the operational amplifier OP2 is on the connection VG2, i. H. fed back to the base connections of the bipolar transistors T1 and T2.

Gleichzeitig ist der Ausgang des zweiten Operationsverstärkers OP2 an die Klemme VR gelegt, an der bezüglich des an der Klemme VSS liegenden Bezugspotentials die temperaturunabhängige Referenzspannung UR abgegriffen werden kann. Die Beziehung zwischen der temperaturunabhängigen Referenzspannung UR und der Bandgap-Spannung UG wird durch den ohmschen Spannungsteiler aus den Widerständen R4 und R5 hergestellt. So berechnet sich die temperaturunabhängige Referenzspannung UR aus dem Produkt der Bandgap-Spannung UG einerseits und der Summe der beiden Widerstände R4 und R5 bezogen auf den Widerstand R4 anderer­seits.At the same time, the output of the second operational amplifier OP2 is connected to the terminal VR, at which the temperature-independent reference voltage UR can be tapped with respect to the reference potential at the terminal VSS. The relationship between the temperature-independent reference voltage UR and the bandgap voltage UG is established by the ohmic voltage divider from the resistors R4 and R5. The temperature-independent reference voltage UR is thus calculated from the product of the bandgap voltage UG on the one hand and the sum of the two resistors R4 and R5 in relation to the resistor R4 on the other hand.

Eine Ausgestaltung der Erfindung gemäß der Figur enthält eine Anlaufschaltung IA, die zwischen dem Ausgangsanschluß VR des zweiten Operationsverstärkers OP2 und der Klemme VDD mit dem relativ positiven Versorgungsspannungspotential angeschlossen ist. Diese Anlaufschaltung IA ist als Stromquelle gezeichnet und kann beispielsweise durch einen Stromquellentransistor oder einen Widerstand realisiert werden. Die Anlaufschaltung IA er­möglicht es, daß die Referenzspannung UR als Betriebsspannung der Bandgap-Schaltung verwendet wird, so daß sich die eigentliche Referenzspannungsquelle aus den beiden Bipolartransistoren T1 und T2 mit der stabilisierten Ausgangsreferenzspannung betreiben läßt. Auf diese Weise ergibt sich eine ausgezeichnete Unter­drückung von Eingangsspannungsschwankungen an der Klemme VDD. Die Anlaufschaltung IA ist erforderlich, da sich bei Anlegen einer Spannung an die Klemme VDD die aus der temperaturunab­hängigen Referenzspannung UR abgeleitete Betriebsspannung erst aufbauen muß. Die Schaltung gemäß dem Ausführungsbeispiel der Figur ermöglicht es, auf eine separate Anschlußklemme VR zu verzichten, so daß die erfindungsgemäße CMOS-Spannungsreferenz nach außen nur die beiden Anschlußklemmen VDD und VSS besitzt.An embodiment of the invention according to the figure contains a startup circuit IA, which is connected between the output terminal VR of the second operational amplifier OP2 and the terminal VDD with the relatively positive supply voltage potential. This start-up circuit IA is drawn as a current source and can be implemented, for example, by a current source transistor or a resistor. The starting circuit IA enables the reference voltage UR to be used as the operating voltage of the bandgap circuit, so that the actual reference voltage source can be operated from the two bipolar transistors T1 and T2 with the stabilized output reference voltage. This results in excellent suppression of input voltage fluctuations at the VDD terminal. The start-up circuit IA is necessary since the operating voltage derived from the temperature-independent reference voltage UR must first be built up when a voltage is applied to the VDD terminal. The circuit according to the embodiment of the figure makes it possible to dispense with a separate connection terminal VR, so that the CMOS voltage reference according to the invention has only the two connection terminals VDD and VSS to the outside.

Claims (5)

1. Schaltungsanordnung in komplementärer MOS-Technik zur Erzeugung einer von der Temperatur unabhängigen Referenzspannung mit Hilfe einer Bandgap-Schaltung, bei der die Reihenschaltung aus dem Ausgangskreis eines ersten Bipolartransistors (T1) mit einer ersten Basis-Emitter-Schwellspannung, einem ersten Wider­stand (R3) und dem Ausgangskreis eines ersten Feldeffekttran­sistors (M1) zwischen den Klemmen (VDD, VSS) einer Versorgungs­spannungsquelle liegt und entsprechend parallel dazu die Reihen­schaltung aus dem Ausgangskreis eines zweiten Bipolartransistors (T2) mit einer zweiten Basis-Emitter-Schwellspannung, zwei in Reihe geschalteten Widerständen (R1, R2) und dem Ausgangskreis eines zweiten Feldeffekttransistors (M2) vorgesehen ist, und bei der die Basisanschlüsse der Bipolartransistoren (T1, T2) miteinander verbunden sind und die Verbindungspunkte des ersten Bipolartransistors (T1) mit dem ersten Widerstand (R3) einer­seits und der zwei in Reihe geschalteten Widerstände (R1, R2) andererseits an die Eingänge (-, +) eines ersten Operations­verstärkers (OP1) gelegt sind, dessen Ausgang die beiden Feldeffekttransistoren (M1, M2) steuert, dadurch gekennzeichnet, daß der Ausgang der Bandgap-­Schaltung (VG1) am Drainanschluß des zweiten Feldeffekttran­sistors (M2) auf die Basisanschlüsse der Bipolartransistoren (T1, T2) rückgekoppelt ist.1. Circuit arrangement in complementary MOS technology for generating a temperature-independent reference voltage using a bandgap circuit, in which the series circuit from the output circuit of a first bipolar transistor (T1) with a first base-emitter threshold voltage, a first resistor (R3 ) and the output circuit of a first field effect transistor (M1) between the terminals (VDD, VSS) of a supply voltage source and, accordingly, the series circuit from the output circuit of a second bipolar transistor (T2) with a second base-emitter threshold voltage, two resistors connected in series (R1, R2) and the output circuit of a second field effect transistor (M2) is provided, and in which the base connections of the bipolar transistors (T1, T2) are connected to one another and the connection points of the first bipolar transistor (T1) to the first resistor (R3) on the one hand and of the two resistors (R1, R2) connected in series are in turn connected to the inputs (-, +) of a first operational amplifier (OP1), the output of which controls the two field effect transistors (M1, M2), characterized in that the output of the bandgap circuit (VG1) is connected to the drain of the second field effect transistor (M2 ) is fed back to the base connections of the bipolar transistors (T1, T2). 2. Anordnung nach Anspruch 1, dadurch gekenn­zeichnet, daß im Rückkoppelzweig ein zweiter Opera­tionsverstärker (OP2) eingangsseitig (-, +) einerseits am Ausgang der Bandgap-Schaltung (VG1) und andererseits am Teilerpunkt eines zwischen den Basisanschlüssen der Bipolar­transistoren (T1, T2) und der Klemme (VSS) mit relativ ne­gativem Versorgungsspannungspotential liegenden ohmschen Spannungsteilers (R3, R4) angeschlossen ist und ausgangs­seitig (VR) mit den Basisanschlüssen (VG2) der Bipolar­transistoren (T1, T2) verbunden ist.2. Arrangement according to claim 1, characterized in that in the feedback branch a second operational amplifier (OP2) on the input side (-, +) on the one hand at the output of the bandgap circuit (VG1) and on the other hand at the dividing point one between the base connections of the bipolar transistors (T1, T2) and the terminal (VSS) with a relatively negative supply voltage potential of the ohmic voltage divider (R3, R4) is connected and the output side (VR) is connected to the base connections (VG2) of the bipolar transistors (T1, T2). 3. Anordnung nach Anspruch 1 oder 2, dadurch ge­ kennzeichnet, daß zwischen dem Ausgangsanschluß (VR) des zweiten Operationsverstärkers (OP2) und der Klemme (VDD) mit relativ positivem Versorgungspotential eine Anlauf­schaltung (IA) angeschlossen ist.3. Arrangement according to claim 1 or 2, characterized ge indicates that a start-up circuit (IA) is connected between the output terminal (VR) of the second operational amplifier (OP2) and the terminal (VDD) with a relatively positive supply potential. 4. Anordnung nach Anspruch 3, dadurch gekenn­zeichnet, daß die Anlaufschaltung (IA) aus einer Stromquelle besteht.4. Arrangement according to claim 3, characterized in that the starting circuit (IA) consists of a current source. 5. Anordnung nach Anspruch 3, dadurch gekenn­zeichnet, daß die Anlaufschaltung (IA) aus einem Widerstand besteht.5. Arrangement according to claim 3, characterized in that the starting circuit (IA) consists of a resistor.
EP88115839A 1988-09-26 1988-09-26 Cmos voltage reference Expired - Lifetime EP0360887B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP88115839A EP0360887B1 (en) 1988-09-26 1988-09-26 Cmos voltage reference
AT88115839T ATE93634T1 (en) 1988-09-26 1988-09-26 CMOS VOLTAGE REFERENCE.
DE88115839T DE3883536D1 (en) 1988-09-26 1988-09-26 CMOS voltage reference.
JP1243254A JP2759905B2 (en) 1988-09-26 1989-09-18 Circuit device using complementary MOS technology
US07/412,894 US4931718A (en) 1988-09-26 1989-09-26 CMOS voltage reference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP88115839A EP0360887B1 (en) 1988-09-26 1988-09-26 Cmos voltage reference

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EP0360887A1 true EP0360887A1 (en) 1990-04-04
EP0360887B1 EP0360887B1 (en) 1993-08-25

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JP (1) JP2759905B2 (en)
AT (1) ATE93634T1 (en)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0913756A2 (en) * 1997-10-30 1999-05-06 Xerox Corporation A voltage regulator

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0782404B2 (en) * 1989-07-11 1995-09-06 日本電気株式会社 Reference voltage generation circuit
US5027053A (en) * 1990-08-29 1991-06-25 Micron Technology, Inc. Low power VCC /2 generator
JPH06175742A (en) * 1992-12-09 1994-06-24 Nec Corp Reference voltage generating circuit
US5545978A (en) * 1994-06-27 1996-08-13 International Business Machines Corporation Bandgap reference generator having regulation and kick-start circuits
US5889394A (en) * 1997-06-02 1999-03-30 Motorola Inc. Temperature independent current reference
US6150872A (en) * 1998-08-28 2000-11-21 Lucent Technologies Inc. CMOS bandgap voltage reference
US6411158B1 (en) * 1999-09-03 2002-06-25 Conexant Systems, Inc. Bandgap reference voltage with low noise sensitivity
FR2802316B1 (en) * 1999-12-08 2003-10-24 Mhs LOW CURRENT SOURCE CONTROL CONSUMPTION BY DUAL LOW VOLTAGE REGULATED SUPPLY
US6724176B1 (en) * 2002-10-29 2004-04-20 National Semiconductor Corporation Low power, low noise band-gap circuit using second order curvature correction
US6844772B2 (en) * 2002-12-11 2005-01-18 Texas Instruments Incorporated Threshold voltage extraction circuit
US6815941B2 (en) * 2003-02-05 2004-11-09 United Memories, Inc. Bandgap reference circuit
KR100588339B1 (en) * 2004-01-07 2006-06-09 삼성전자주식회사 Current reference circuit with voltage-current converter having auto-tuning function
US7728574B2 (en) * 2006-02-17 2010-06-01 Micron Technology, Inc. Reference circuit with start-up control, generator, device, system and method including same
EP1884856B1 (en) * 2006-07-26 2016-04-06 ams AG Voltage/current converter circuit and method for providing a ramp current
EP1885061B1 (en) * 2006-07-26 2012-02-29 austriamicrosystems AG Amplifier arrangement and method for amplification

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983002342A1 (en) * 1981-12-21 1983-07-07 Motorola Inc Precision current source
EP0217225A1 (en) * 1985-09-30 1987-04-08 Siemens Aktiengesellschaft Trimmable circuit generating a temperature-dependent reference voltage

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317054A (en) * 1980-02-07 1982-02-23 Mostek Corporation Bandgap voltage reference employing sub-surface current using a standard CMOS process
US4602207A (en) * 1984-03-26 1986-07-22 At&T Bell Laboratories Temperature and power supply stable current source
US4590419A (en) * 1984-11-05 1986-05-20 General Motors Corporation Circuit for generating a temperature-stabilized reference voltage
US4590418A (en) * 1984-11-05 1986-05-20 General Motors Corporation Circuit for generating a temperature stabilized reference voltage
US4622512A (en) * 1985-02-11 1986-11-11 Analog Devices, Inc. Band-gap reference circuit for use with CMOS IC chips
US4588941A (en) * 1985-02-11 1986-05-13 At&T Bell Laboratories Cascode CMOS bandgap reference
US4626770A (en) * 1985-07-31 1986-12-02 Motorola, Inc. NPN band gap voltage reference
GB8630980D0 (en) * 1986-12-29 1987-02-04 Motorola Inc Bandgap reference circuit
US4857823A (en) * 1988-09-22 1989-08-15 Ncr Corporation Bandgap voltage reference including a process and temperature insensitive start-up circuit and power-down capability

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983002342A1 (en) * 1981-12-21 1983-07-07 Motorola Inc Precision current source
EP0217225A1 (en) * 1985-09-30 1987-04-08 Siemens Aktiengesellschaft Trimmable circuit generating a temperature-dependent reference voltage

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Band SC-20, Nr. 6, Dezember 1985, Seiten 1283-1285, IEEE, New York, US; S.L. LIN et al.: "A Vbe(T) model with application to bandgap reference design" *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0913756A2 (en) * 1997-10-30 1999-05-06 Xerox Corporation A voltage regulator
EP0913756A3 (en) * 1997-10-30 1999-05-19 Xerox Corporation A voltage regulator

Also Published As

Publication number Publication date
JP2759905B2 (en) 1998-05-28
EP0360887B1 (en) 1993-08-25
ATE93634T1 (en) 1993-09-15
JPH02121012A (en) 1990-05-08
US4931718A (en) 1990-06-05
DE3883536D1 (en) 1993-09-30

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