EP0000545A1 - Method for forming a semiconducter device with self-alignment - Google Patents

Abstract

In a method for producing a semiconductor arrangement with improved self-alignment, in particular an insulating layer field-effect transistor structure with a self-aligned gate electrode, the doping areas are first of all achieved by means of ion implantation as buried areas (18, 19) in the semiconductor body by means of ion implantation in order to achieve doping areas that are as precisely self-adjusted as possible but nevertheless have a relatively large penetration depth (10) formed in the mutual arrangement determined by masking. The desired expansion of the buried regions thus formed is brought about by subsequent heat treatment until the semiconductor surface is reached.

Description

The invention relates to a method for producing a semiconductor arrangement of the type specified in the preamble of claim 1. A preferred field of application of this method is the production of insulating layer field-effect transistor structures which are equipped with so-called self-aligned gate electrodes.

Such field effect transistors with a self-aligned gate are already known per se. The associated conventional manufacturing methods use a mask made of a high temperature-resistant material, ie a material that is able to withstand high temperatures in the order of magnitude of 1000 ° C. and higher, for masking during the formation of the source and drain regions. This masking layer may, for example, be made of silicon, as described for the processes described in US Pat. Nos. 3,475,234 and 3,544,399, using polycrystalline silicon as the masking material which remains in the gate area for the final formation of the gate electrode. Since such structures are insulated-layer field-effect transistors, is still a layer of an insulating material, e.g. B. from silicon dioxide, be present under the silicon-containing masking layer.

On the other hand, the high temperature resistant material itself can already be an insulating material, e.g. B. silicon nitride, which remains as a gate dielectric in the gate region. Associated methods of this type are discussed in U.S. Patent No. 3,444,858. The high temperature resistant material, z. B. silicon nitride or a double layer of silicon nitride over silicon dioxide, for edge definition of the source and drain regions adjacent to the gate region; it remains as a thin gate dielectric in the final field effect transistor structure. For this purpose, a thick oxide layer is thermally grown over the source and drain, the silicon nitride layer present in the gate region serving as an oxidation-inhibiting mask to prevent the thickness of the thin gate insulating layer from increasing. Finally, a conductive gate electrode is formed in the gate area, the thin silicon nitride layer or, after its removal, another thin insulating layer also serving to delimit the area provided as the gate area.

The major advance in such a self-aligned gate structure has been that it has improved the positioning of the gate electrode and gate insulating layer relative to the source and drain regions. Before the self-aligned gate structures were used, the gate electrode had to be made larger relative to the channel length effective between the source and drain, ie there was a considerable overlap between the gate electrode and the source and drain regions in front. This resulted in undesired stray capacitances in the form of gate overlap capacitances, which led to a deterioration in the frequency properties or the switching speed of such field-effect transistor components in integrated circuits.

Although the self-aligned gate structures described above and the associated methods have already led to a considerable reduction in the gate overlap and thus to faster switching times, the problem of gate overlap of the source and drain regions has still not been completely eliminated. This was primarily due to the procedural design according to which the source and drain regions were formed by means of a diffusion step despite the provision of a self-aligned gate. Conventionally, this diffusion step can be carried out directly by introducing dopants for the source and drain into the semiconductor body in the presence of the self-adjusting gate masking. Alternatively, the dopants can first be introduced by diffusion or ion implantation in such a way that very flat surface areas of the appropriate conductivity type form, which is followed by a so-called driving-in step to be carried out at high temperatures, through which the source and drain are driven deeper into the semiconductor body. In the course of these diffusion or driving-in steps, of course, the doping atoms migrate to a certain extent below the gate masking layer. As a result, there was nevertheless an overlap of the gate with the source and drain and the resulting disadvantageous consequences.

It has also been used in the prior art, e.g. In US Pat. No. 3,472,712, for example, it is possible to produce such self-aligned insulating layer field-effect transistors by avoiding any diffusion step simply by using an ion implantation. Such structures certainly do not have any gate overlap problems. The structures produced by such methods are, however, subject to a restriction in that their source and drain regions only extend into the semiconductor body or the substrate with a depth of 200 to 300 nm or less. As a result, high resistance values result for the source and drain regions, i.e. Sheet resistances in the order of 50 Ω / □. Although such high layer resistance values can be quite acceptable for some discrete field effect transistor functions as well as for simpler integrated circuits, in the case of more complex integrated circuits constructed with field effect transistors, in which the source and drain regions or their extensions are used as part of the connection network, the layer resistances in the circuit are considerably lower The order of 8 to 10 Ω / □ is required. According to the prior art, source and drain regions with such a low sheet resistance were produced by one of the diffusion methods described above to form the source and drain regions with a depth extension in the substrate in the order of magnitude of 1000 nm. The formation of, for example, 1000 nm deep source and drain areas only by ion implantation without subsequent diffusion treatment would, as far as possible, require a considerably more complicated process design which is more complex in terms of the number of individual ion implantation steps and the associated choice of energy and dosage values.

The invention, as characterized in the claims, achieves the object of specifying a method for producing a semiconductor arrangement, in particular an insulating layer field-effect transistor structure, which is improved with respect to the overlap-free self-adjustment of doping regions relative to a surface layer, in which the overlap-free self-adjustment also occurs at relatively deep in doping regions reaching the semiconductor body can be achieved. In summary, buried areas completely enclosed by the material of the semiconductor body are first formed in the mutual arrangement defined by the masking layer on the semiconductor surface by means of ion implantation, whereupon a subsequent heat treatment brings about a targeted expansion of the dopants present in the buried areas until the semiconductor surface is reached. In the case of an insulating layer field-effect transistor structure, this means that the source and drain are first doped as buried regions by means of ion implantation within the semiconductor body and the subsequent heat treatment for diffusing out the dopants is carried out to such an extent that the upper edge zone of the initially buried region ultimately just the semiconductor surface reached. In this case, it is ensured on the one hand that the channel region is always exactly and completely covered by the gate electrode, but on the other hand that there is no gate overlap with the source and drain regions formed in this way.

The invention is explained in more detail below with the aid of drawings which illustrate only one embodiment.

• Fign. 1 - 7 schematische Querschnittsdarstellungen durch eine Feldeffekttransistorstruktur zur Erläuterung der Verfahrensabfolge im Rahmen vorliegender Erfindung, und
• Fign. 8A - 8C verschiedene Dotierungsprofile über die Tiefe des Draingebietes, wie sie sich zu verschiedenen Verfahrenszeitpunkten ergeben.

Show it:

• Fig. 1-7 are schematic cross-sectional representations through a field effect transistor structure to explain the process sequence within the scope of the present invention, and
• Fig. 8A-8C different doping profiles over the depth of the drain region, as result at different times of the process.

1 shows a semiconductor body or a substrate 10 of the P conductivity type, the specific resistance value of which is approximately 0.1 to 10 cm and on which an approximately 900 nm thick silicon dioxide layer 11 is formed. This layer 11 can be produced in a conventional manner by thermal oxidation or deposited in another way, e.g. B. by vapor deposition or sputtering. An opening 12 is produced in the layer 11 using conventional photolithography and etching methods, so that the structure shown in FIG. 1 results.

According to FIG. 2, a thin layer 13 of silicon dioxide with a thickness of approximately 50 nm is then allowed to grow in the area of the opening 12, preferably thermally. A silicon layer 14 is applied over this by means of conventional methods for depositing silicon, for example described in US Pat. No. 3,424,629. This process step is carried out at a temperature on the order of 500 to 900 ° C and usually at atmospheric pressure. The silicon layer 14 is a polycrystalline structure since it is based on the Silicon dioxide layers 11 and 13 is formed. The thickness of the layer 14 is approximately 900 nm. Finally, an approximately 80 nm thick silicon dioxide layer 15 is produced in a conventional manner per se, but preferably by thermal oxidation of a part of the surface of the silicon layer 14.

3, using conventional photolithography and Xtz techniques; and using a masking layer 15 'made of silicon dioxide on the area of the silicon layer 14 which is intended for the later gate electrode of the field effect transistor, a selective etching process is carried out in order to remove the silicon layer areas going beyond the area 14'. All conventional chemical etching methods are available for the removal of the silicon layer 14, by means of which silicon can be etched, as opposed to silicon dioxide. For example, a dilute nitric acid / hydrofluoric acid solution is suitable for this purpose. As a result, a pair of openings 16 and 17 in FIG. 3 are obtained which are located at the locations intended for the later source and drain regions.

The regions 18 and 19 buried in the semiconductor body 10 are then formed by means of ion implantation in accordance with FIG. 4. For this purpose, N-type dopants, e.g. B. phosphorus, implanted in the substrate. The implantation step can be carried out either directly through the unmasked, relatively thin silicon dioxide layer 13 or, as shown in FIG. 4, after the silicon dioxide layer 13 not covered by the silicon layer 14 'has been removed beforehand. In Fig. 4, the one below the mask is in the form of silicon layer 14 'arranged silicon dioxide layer designated 13'. To remove the silicon dioxide layer, a conventional etching process, e.g. B. can be used using a buffered hydrofluoric acid. In this case, the silicon dioxide layer 15 'will also be removed, while the layer 11, which is considerably thicker in comparison, remains essentially unchanged. The ion implantation must be carried out with sufficient beam dosing and energy that the concentration distribution for the buried regions 18 and 19 results in the following aspects. In the subsequent high-temperature step at about 1000 ° C. or higher for the outward diffusion of regions 18 and 19 down to the transitions 20 and 21 shown in FIG. 5, the same heat treatment is intended to ensure that regions 18 and 19 also move upwards expand in the direction of the surface of the semiconductor body 10 so that they just adjoin the silicon gate electrode laterally on the semiconductor surface. In order to obtain source and drain regions with relatively low sheet resistance values in the order of 8 to 10 2 / m, penetration depths of the lower semiconductor junctions 20 and 21 in the order of 1 μm are desirable. In order to arrive at such resulting penetration depths, the regions 18 and 19 initially implanted in FIG. 4 should be generated with such beam energy and dosage that a concentration profile corresponding to FIG. 8A results. FIG. 8A shows the concentration distribution of the N-doping impurities for the regions 18 and 19 along the section line 8A-8A shown in FIG. 4. As can be seen from FIG. 8A, the regions 18 and 19 are originally regions which are completely enclosed in the P-conducting semiconductor body 10 generated, with a peak concentration at about 0.5 pm from the semiconductor surface. The implantation step that can be used to form these areas 18 and 19 with the concentration profile shown can be carried out using conventional devices and methods, such as are described, for example, in US Pat. No. 3,756,862. For example, ^{taking 31p +} ions, an energy value of 400 keV and a dosage of approximately ₁₀ ¹⁶ ions / cm ^{2 is} appropriate. The relatively thick layers 11 and 14 'prevent the implanted ions from being installed in the semiconductor body 10 below these layers. The implantation also forms a dopant distribution similar to the shape shown in FIG. 8A in the silicon layer region 14 ′. As a result, the layer 14 'is desirably provided with a low sheet resistance.

Following the implantation step, a so-called diffusion or driving-in step is carried out at a temperature of approximately 950 ° C. in a conventional oxidizing atmosphere, such as, for example, B. steam, performed to bring the source and drain regions 18 and 19 into the form shown in FIG. 5. In particular, the area boundaries should thereby expand towards the semiconductor surface. The final dopant distribution for the source and drain regions 18 and 19 along the section line 8B-8B shown in FIG. 5 is shown in FIG. 8B. As a result of the oxidation process, a silicon dioxide layer 40 is formed over the semiconductor body 10 as well as over the polycrystalline silicon gate electrode 14 '.

In this context, it should be noted that if the peak concentration of the ion treatment is provided at a depth of penetration which is approximately half of the ultimately desired depth of penetration for the lower region limits of the source and drain, the source and drain region edges next to it due to the subsequent diffusion or heat treatment step their downward expansion to the same extent can also be extended upward so that their intersections 22 and 23 (in FIG. 5) are practically exactly aligned with the corresponding edges 24 and 25 of the silicon gate electrode 14 'with regard to their lateral adjustment. To ensure that the intersections 22 and 23 coincide at least with the corners 24 and 25, or in other words that the silicon electrode 14 'and the underlying thin layer 13' of silicon dioxide extend to the intersections 22 and 23 the preliminary ion implantation step according to FIG. 8A has such a distribution that, following the diffusion or heat treatment, the final impurity concentration on the surface of regions 18 and 19 (point 26 in FIG. 8B) is somewhat higher than the basic doping (point 27 8B) of the silicon semiconductor body 10.

In the further course of the method, openings 31, 32 and 28 are then produced in the silicon dioxide layer 40 as contact openings for source, drain and the gate electrode. As can be seen from Figure 8B, the source and drain regions have a relatively low surface concentration of phosphorus. It is therefore advantageous to in each case in these contact openings a flat implantation of the dopants causing N-type conduction, z. As phosphorus, the areas designated in Fig. 6 with 29, 30 and 34 be formed. These areas have a high surface concentration of the N conductivity type in the order of 10 ²¹ atoms / cm 3, cf. in addition the concentration profile shown in FIG. 8C for the relationships shown in FIG. 6, and in particular the point 33 in FIG. 8C. These N + conductive connection regions 29, 30 and 34 can be produced in a conventional manner by introducing dopants. However, it is preferable to implant these areas by implanting N-type ions, e.g. B. phosphorus, using the method described above with an energy of about 40 keV and a dosage of about 10 ¹⁶ ions / cm ² . 7, the contact and connection metallization in the form of the connections 35, 36 and 37 for the source, drain and the silicon gate is formed in a conventional manner. This metallization can be completely conventional in the usual way with such integrated FET circuits, e.g. B. made of aluminum.

Insofar as a structure with a self-aligned silicon gate was used in the exemplary embodiment described, it should be noted that the invention is not restricted to this but can also be applied to other self-aligned gate designs. It should only be noted here that the masking layer required to ensure the self-alignment of the thin gate insulating layer consists of a material which does not melt or decompose in any other way at the diffusion temperatures of the order of 1000 ° C. or greater that are used. Such other possibilities include, for example, self-aligned field effect transistors with a silicon nitride gate technology, in which a thin layer made of silicon nitride for self-aligning formation of the source and drain regions relative to the thin gate insulating layer. Furthermore, high-temperature-resistant metals, eg. B. use molybdenum, tungsten or tantalum instead of the silicon described in the present embodiment.

Claims (8)

1. A method for producing a semiconductor arrangement with improved self-alignment of doping regions relative to surface layers, in particular an insulating layer field-effect transistor structure, in which, using an ion implantation step in a semiconductor body of a first conductivity type, at least two doping regions of a second conductivity type, in particular source and drain regions, at a distance voneinder are formed, a masking layer effective against ion radiation being applied to the semiconductor body at least in the region of this distance, characterized in that a beam of ions generating the second conductivity type with sufficient radiation energy and dosage is allowed to act on the semiconductor body in such a way that Initially, buried areas (18, 19) completely enclosed by the material of the semiconductor body (10) and doped in opposite directions in the area through the masking layer (14 ') agreed mutual arrangement are formed (Fig. 4), and that in the presence of the masking layer (14 ') present at least in the region of the distance, an expansion of the buried regions (18, 19) formed in this way are brought about until the semiconductor surface is reached (FIG. 5). 2. The method according to claim 1, characterized by a semiconductor body made of silicon and a masking layer defining the distance between the doping regions from the composition of an electrically insulating layer on the semiconductor body and a layer of silicon formed thereover. 3. The method according to claim 2, characterized in. that the electrically insulating layer comprises silicon dioxide. 4. The method according to any one of the preceding claims, characterized in
that the masking layer comprises a layer of silicon nitride at least in the region of the distance between the doping regions to be created. 5. The method according to any one of the preceding claims, characterized in that _'
that the heat treatment is carried out in such a way that the semiconductor junctions (20, 21 in FIG. 5B) belonging to the doping regions, in the course of their expansion due to the heat treatment, the semiconductor surface at the edge points (22, 23) of the masking layer (14 ') to cut. 6. The method according to any one of the preceding claims, characterized in that
that the surface concentration of the doping substances determining the doping regions of the second conductivity type is up to a factor of 3 greater than the basic doping of the semiconductor body of the first conductivity type. 7. The method according to any one of the preceding claims, characterized in that
that the ion implantation step is carried out through a layer covering the semiconductor surface in the region of the openings in the masking layer, preferably made of silicon dioxide. 8. The method according to any one of the preceding claims, characterized in
that after the formation of connection openings to the doping regions and before the production of the associated metallization in the areas exposed in the region of the connection openings (28, 31, 32 in FIG. 6), additional doping substances of the second conductivity type to increase the surface concentration, preferably also by means of an ion implantation step , are introduced.

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