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DK1414066T3 - Method for monitoring power semiconductor components - Google Patents

Method for monitoring power semiconductor components

Info

Publication number
DK1414066T3
DK1414066T3 DK03023086T DK03023086T DK1414066T3 DK 1414066 T3 DK1414066 T3 DK 1414066T3 DK 03023086 T DK03023086 T DK 03023086T DK 03023086 T DK03023086 T DK 03023086T DK 1414066 T3 DK1414066 T3 DK 1414066T3
Authority
DK
Denmark
Prior art keywords
power semiconductor
contact areas
semiconductor components
electrically separated
monitoring power
Prior art date
Application number
DK03023086T
Other languages
Danish (da)
Inventor
Reinhrad Dr Herzer
Mario Dr Netzel
Jan Lehmann
Sascha Pawel
Original Assignee
Semikron Elektronik Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10249712A external-priority patent/DE10249712B3/en
Application filed by Semikron Elektronik Gmbh filed Critical Semikron Elektronik Gmbh
Application granted granted Critical
Publication of DK1414066T3 publication Critical patent/DK1414066T3/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
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    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70—Testing of connections between components and printed circuit boards
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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Conversion In General (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The circuit arrangement includes at least two electrically separated groups of contact areas (10) with the same functionality. The contact areas are provided on a power semiconductor. Each electrically separated group of contact areas are connected with the neutral point of a star connection (18) via an active and/or a passive component (17). All electrically separated groups of contact areas are connected with at least a further contact area (16) provided outside the power semiconductor. An Independent claim is also provided for a method for monitoring the circuit arrangement.
DK03023086T 2002-10-25 2003-10-15 Method for monitoring power semiconductor components DK1414066T3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10249712A DE10249712B3 (en) 2002-10-25 2002-10-25 Circuit for monitoring power semiconducting components has each isolated contact surface/group connected via active and/or passive component(s) to star circuit(s) star point, external contact surface
DE10316357A DE10316357B4 (en) 2002-10-25 2003-04-10 Method for monitoring power semiconductor components

Publications (1)

Publication Number Publication Date
DK1414066T3 true DK1414066T3 (en) 2009-10-05

Family

ID=32070728

Family Applications (1)

Application Number Title Priority Date Filing Date
DK03023086T DK1414066T3 (en) 2002-10-25 2003-10-15 Method for monitoring power semiconductor components

Country Status (5)

Country Link
EP (1) EP1414066B1 (en)
AT (1) ATE438199T1 (en)
DE (2) DE10316357B4 (en)
DK (1) DK1414066T3 (en)
ES (1) ES2328124T3 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010030317B4 (en) * 2010-06-21 2016-09-01 Infineon Technologies Ag Circuit arrangement with shunt resistor
FI20125191L (en) * 2012-02-20 2013-08-21 Tellabs Oy Assembly equipped with condition monitoring and a method for monitoring condition
US8853835B2 (en) 2012-10-05 2014-10-07 Infineon Technologies Ag Chip arrangements, a chip package and a method for manufacturing a chip arrangement
EP3121612A1 (en) * 2015-07-21 2017-01-25 ABB Technology AG Failure prediction of power semiconductor modules

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3508670B2 (en) * 1999-02-05 2004-03-22 株式会社豊田自動織機 Semiconductor module
DE10005754C2 (en) * 1999-08-12 2002-02-07 Semikron Elektronik Gmbh Power semiconductor circuit arrangement with vibration-damped parallel connection
IT1311277B1 (en) * 1999-12-23 2002-03-12 St Microelectronics Srl ELECTRONIC DEVICE WITH DOUBLE WIRE CONNECTIONS, METHOD FOR MANUFACTURING SUCH ELECTRONIC DEVICE AND VERIFICATION METHOD
US6552429B2 (en) * 2000-08-28 2003-04-22 Mitsubishi Denki Kabushiki Kaisha Power switching semiconductor device with suppressed oscillation

Also Published As

Publication number Publication date
ATE438199T1 (en) 2009-08-15
EP1414066A1 (en) 2004-04-28
ES2328124T3 (en) 2009-11-10
DE50311749D1 (en) 2009-09-10
DE10316357B4 (en) 2005-02-10
DE10316357A1 (en) 2004-11-04
EP1414066B1 (en) 2009-07-29

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