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DE69220818D1 - Method and device for error detection in computer memories provided with multi-bit outputs - Google Patents

Method and device for error detection in computer memories provided with multi-bit outputs

Info

Publication number
DE69220818D1
DE69220818D1 DE69220818T DE69220818T DE69220818D1 DE 69220818 D1 DE69220818 D1 DE 69220818D1 DE 69220818 T DE69220818 T DE 69220818T DE 69220818 T DE69220818 T DE 69220818T DE 69220818 D1 DE69220818 D1 DE 69220818D1
Authority
DE
Germany
Prior art keywords
bit
stored
error
data word
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69220818T
Other languages
German (de)
Other versions
DE69220818T2 (en
Inventor
James A Jackson
Kevin M Lowderman
Marc A Quattromani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69220818D1 publication Critical patent/DE69220818D1/en
Application granted granted Critical
Publication of DE69220818T2 publication Critical patent/DE69220818T2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/102—Error in check bits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

An error correcting code and apparatus is used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or data bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome. The check bit syndrome is decoded to produce an output that is input to an error generator circuit together with a parity syndrome for producing error signals indicating occurrence of a single bit error, a multi-bit error, a triple bit error, or a check bit error. <IMAGE>
DE69220818T 1991-01-29 1992-01-10 Method and device for error detection in computer memories provided with multi-bit outputs Expired - Lifetime DE69220818T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/647,408 US5291498A (en) 1991-01-29 1991-01-29 Error detecting method and apparatus for computer memory having multi-bit output memory circuits

Publications (2)

Publication Number Publication Date
DE69220818D1 true DE69220818D1 (en) 1997-08-21
DE69220818T2 DE69220818T2 (en) 1998-02-19

Family

ID=24596873

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69220818T Expired - Lifetime DE69220818T2 (en) 1991-01-29 1992-01-10 Method and device for error detection in computer memories provided with multi-bit outputs

Country Status (4)

Country Link
US (1) US5291498A (en)
EP (1) EP0497110B1 (en)
JP (1) JP3325914B2 (en)
DE (1) DE69220818T2 (en)

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US5922080A (en) * 1996-05-29 1999-07-13 Compaq Computer Corporation, Inc. Method and apparatus for performing error detection and correction with memory devices
CN1073724C (en) * 1997-02-19 2001-10-24 华为技术有限公司 Method for maintaining memory of computer
JP3184129B2 (en) * 1997-09-29 2001-07-09 甲府日本電気株式会社 Storage device
US6282686B1 (en) * 1998-09-24 2001-08-28 Sun Microsystems, Inc. Technique for sharing parity over multiple single-error correcting code words
US6304992B1 (en) 1998-09-24 2001-10-16 Sun Microsystems, Inc. Technique for correcting single-bit errors in caches with sub-block parity bits
US6233716B1 (en) 1998-09-24 2001-05-15 Sun Microsystems, Inc. Technique for partitioning data to correct memory part failures
US6301680B1 (en) 1998-09-24 2001-10-09 Sun Microsystems, Inc. Technique for correcting single-bit errors and detecting paired double-bit errors
US6574746B1 (en) 1999-07-02 2003-06-03 Sun Microsystems, Inc. System and method for improving multi-bit error protection in computer memory systems
US6662333B1 (en) * 2000-02-04 2003-12-09 Hewlett-Packard Development Company, L.P. Shared error correction for memory design
US6785837B1 (en) * 2000-11-20 2004-08-31 International Business Machines Corporation Fault tolerant memory system utilizing memory arrays with hard error detection
US6732291B1 (en) * 2000-11-20 2004-05-04 International Business Machines Corporation High performance fault tolerant memory system utilizing greater than four-bit data word memory arrays
US6691042B2 (en) * 2001-07-02 2004-02-10 Rosetta Inpharmatics Llc Methods for generating differential profiles by combining data obtained in separate measurements
JP4056488B2 (en) * 2004-03-30 2008-03-05 エルピーダメモリ株式会社 Semiconductor device testing method and manufacturing method
US7099221B2 (en) * 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US7398449B1 (en) 2004-06-16 2008-07-08 Azul Systems, Inc. Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) * 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) * 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US6965537B1 (en) 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US7353437B2 (en) * 2004-10-29 2008-04-01 Micron Technology, Inc. System and method for testing a memory for a memory failure exhibited by a failing memory
US7607071B2 (en) * 2005-01-28 2009-10-20 Intel Corporation Error correction using iterating generation of data syndrome
US20060242537A1 (en) * 2005-03-30 2006-10-26 Dang Lich X Error detection in a logic device without performance impact
US7478307B1 (en) 2005-05-19 2009-01-13 Sun Microsystems, Inc. Method for improving un-correctable errors in a computer system
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) * 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
TW200929237A (en) * 2007-12-21 2009-07-01 Winbond Electronics Corp Memory architecture and configuration method thereof
JP5353655B2 (en) * 2009-11-18 2013-11-27 富士通株式会社 Error detection / correction code generation circuit and control method thereof
US8589762B2 (en) 2011-07-05 2013-11-19 International Business Machines Corporation Adaptive multi-bit error correction in endurance limited memories
US9037943B2 (en) * 2012-10-26 2015-05-19 Intel Corporation Identification of non-volatile memory die for use in remedial action
US9450614B2 (en) * 2013-09-13 2016-09-20 Rambus Inc. Memory module with integrated error correction
US10559351B2 (en) * 2017-02-20 2020-02-11 Texas Instruments Incorporated Methods and apparatus for reduced area control register circuit
KR20180138394A (en) * 2017-06-21 2018-12-31 에스케이하이닉스 주식회사 Memory system and operating method thereof
WO2023067367A1 (en) * 2021-10-18 2023-04-27 Micron Technology, Inc. Ecc power consumption optimization in memories
US11955989B2 (en) * 2022-08-21 2024-04-09 Nanya Technology Corporation Memory device and test method thereof

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US4030067A (en) * 1975-12-29 1977-06-14 Honeywell Information Systems, Inc. Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
US4077028A (en) * 1976-06-14 1978-02-28 Ncr Corporation Error checking and correcting device
US4209846A (en) * 1977-12-02 1980-06-24 Sperry Corporation Memory error logger which sorts transient errors from solid errors
US4168486A (en) * 1978-06-30 1979-09-18 Burroughs Corporation Segmented error-correction system
GB2136248A (en) * 1983-02-25 1984-09-12 Philips Electronic Associated Text error correction in digital data transmission systems
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Also Published As

Publication number Publication date
EP0497110A1 (en) 1992-08-05
JPH05108495A (en) 1993-04-30
JP3325914B2 (en) 2002-09-17
EP0497110B1 (en) 1997-07-16
US5291498A (en) 1994-03-01
DE69220818T2 (en) 1998-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE