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DE69130448D1 - Adressenerzeugungsschaltung - Google Patents

Adressenerzeugungsschaltung

Info

Publication number
DE69130448D1
DE69130448D1 DE69130448T DE69130448T DE69130448D1 DE 69130448 D1 DE69130448 D1 DE 69130448D1 DE 69130448 T DE69130448 T DE 69130448T DE 69130448 T DE69130448 T DE 69130448T DE 69130448 D1 DE69130448 D1 DE 69130448D1
Authority
DE
Germany
Prior art keywords
generation circuit
address generation
address
circuit
generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130448T
Other languages
English (en)
Other versions
DE69130448T2 (de
Inventor
Takashi Nakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69130448D1 publication Critical patent/DE69130448D1/de
Publication of DE69130448T2 publication Critical patent/DE69130448T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3552—Indexed addressing using wraparound, e.g. modulo or circular addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2101/00—Indexing scheme relating to the type of digital function generated
    • G06F2101/02—Linear multivariable functions, i.e. sum of products

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
DE69130448T 1990-12-29 1991-12-30 Adressenerzeugungsschaltung Expired - Fee Related DE69130448T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP41719890A JP2692384B2 (ja) 1990-12-29 1990-12-29 アドレス生成回路

Publications (2)

Publication Number Publication Date
DE69130448D1 true DE69130448D1 (de) 1998-12-10
DE69130448T2 DE69130448T2 (de) 1999-07-15

Family

ID=18525324

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130448T Expired - Fee Related DE69130448T2 (de) 1990-12-29 1991-12-30 Adressenerzeugungsschaltung

Country Status (4)

Country Link
US (1) US5471600A (de)
EP (1) EP0493834B1 (de)
JP (1) JP2692384B2 (de)
DE (1) DE69130448T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390304A (en) * 1990-09-28 1995-02-14 Texas Instruments, Incorporated Method and apparatus for processing block instructions in a data processor
JPH064458A (ja) * 1992-06-18 1994-01-14 Fuji Xerox Co Ltd Ｄｍａ制御装置
US5960212A (en) * 1996-04-03 1999-09-28 Telefonaktiebolaget Lm Ericsson (Publ) Universal input/output controller having a unique coprocessor architecture
US5790782A (en) * 1996-11-15 1998-08-04 Digital Equipment Corporation Automatic disk drive shelf address assignment and error detection method and apparatus
US5956665A (en) 1996-11-15 1999-09-21 Digital Equipment Corporation Automatic mapping, monitoring, and control of computer room components
EP0893755B1 (de) * 1997-07-21 2004-05-06 Infineon Technologies AG Pufferspeicheranordnung
US6782447B2 (en) 1999-12-17 2004-08-24 Koninklijke Philips Electronics N.V. Circular address register
US6643744B1 (en) * 2000-08-23 2003-11-04 Nintendo Co., Ltd. Method and apparatus for pre-fetching audio data
US6760830B2 (en) * 2000-12-29 2004-07-06 Intel Corporation Modulo addressing
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
KR20160011015A (ko) * 2014-07-21 2016-01-29 에스케이하이닉스 주식회사 어드레스 생성회로 및 이를 포함하는 메모리 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1499184A (en) * 1974-04-13 1978-01-25 Mathematik & Datenverarbeitung Circuit arrangement for monitoring the state of memory segments
GB2084362B (en) * 1980-09-19 1984-07-11 Solartron Electronic Group Apparatus for performing the discrete fourier transform
US4602328A (en) * 1982-12-17 1986-07-22 L'etat Francais Represente Par Le Ministre Des P.T.T. (Centre National D'etudes Des Telecommunications) Management system for the memory of a processor or microprocessor
JPS59128670A (ja) * 1983-01-12 1984-07-24 Hitachi Ltd ベクトル処理装置
JPH07107969B2 (ja) * 1986-11-17 1995-11-15 日本電気株式会社 アドレス生成回路
US5083267A (en) * 1987-05-01 1992-01-21 Hewlett-Packard Company Horizontal computer having register multiconnect for execution of an instruction loop with recurrance
JPH01265347A (ja) * 1988-04-18 1989-10-23 Matsushita Electric Ind Co Ltd アドレス生成装置
US5150471A (en) * 1989-04-20 1992-09-22 Ncr Corporation Method and apparatus for offset register address accessing

Also Published As

Publication number Publication date
US5471600A (en) 1995-11-28
EP0493834A3 (en) 1993-03-17
EP0493834B1 (de) 1998-11-04
JPH04230545A (ja) 1992-08-19
DE69130448T2 (de) 1999-07-15
JP2692384B2 (ja) 1997-12-17
EP0493834A2 (de) 1992-07-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee