DE69129101T2 - Control arrangement for cache memory unit - Google Patents

Description

BACKGROUND OF THE INVENTION (1) Field of the invention

The present invention relates generally to a control system for controlling an auxiliary storage unit and a cache memory unit, and more particularly to a control system for controlling an auxiliary storage unit and a cache memory unit including a cache memory and a non-volatile memory, which system is provided in a data processing system.

(2) Description of the state of the art

A data processing system has been proposed which includes a host computer, a cache storage unit having a cache memory, and an auxiliary storage unit (e.g., a DASD (Direct Access Storage Device such as a disk unit)). In this data processing unit, when the cache memory contains the same data as that in the auxiliary storage unit, the host computer reads the data from the cache memory instead of the data from the auxiliary storage unit. In this case, since the auxiliary storage unit (such as a disk unit) which requires a long access time is not accessed, the time required to obtain the data can be reduced.

Alternatively, the data supplied from the host computer is stored in the auxiliary storage unit in accordance with a data write process, often referred to as a pass-through write process.

In the pass-through write process, as shown in Fig. 1, when a host computer 31 supplies a write command together with updated data to a disk controller 33, the disk controller 33 writes the updated data into both a cache memory 35 and an auxiliary storage unit 37 (a disk unit). This pass-through write process has the advantage that the data stored in the cache memory 35 is always the same as the corresponding data stored in the auxiliary storage unit 37. However, since the time for writing the data depends on the access time of the auxiliary storage unit (the disk unit), the cache memory 35 cannot be effectively used for data writing.

In order to eliminate the above-mentioned disadvantage of the pass-through write process, a system having a non-volatile memory has been proposed as shown in Fig.2. As shown in Fig.2, the disk control unit 41 includes a cache memory unit composed of a cache memory 35 and a non-volatile memory 43. The capacity of the non-volatile memory 43 is smaller than that of the cache memory 35. This system carries out a data write process, which is often referred to as a fast write process. In the fast write process, when the host computer 31 supplies the write command together with the updated data to the disk control unit 41, the disk control unit 41 controls the cache memory unit so that the updated data is stored in both the cache memory 35 and the non-volatile memory 43. Thereafter, the disk control unit 41 writes the updated data stored in the non-volatile memory 43 into the auxiliary storage unit 37 asynchronously with the write command from the host computer 31. A process for writing the data stored in the non-volatile memory 43 into the auxiliary storage 37 is called a write-back process. According to the high-speed write process, when the renewed data is written into the nonvolatile memory 43 instead of the auxiliary storage unit 37 in response to the write command from the host computer 31, the time required for the write process based on the write command is shorter than that required in the pass-through write process described above. That is, the write process can be carried out at a high speed.

In the system including the nonvolatile memory 43, in order to use the memories effectively, a track on which data is stored is divided into N blocks, and the data for each block can be written into and read out from the cache memory 35 and the nonvolatile memory 43. Thus, when the number of blocks used in the nonvolatile memory 43 is less than N and the number of blocks corresponding to the renewed data supplied from the host computer 31 is greater than N, the data cannot be written into the nonvolatile memory 43. In this case, different writing processes are carried out based on whether or not the nonvolatile memory 43 contains data on an identified track in the cache memory 35. That is, when the non-volatile memory 43 has no data in the identified track, in a first process, the write data corresponding to the identified track supplied from the host computer 31 is written into the auxiliary memory 37 in accordance with the pass-through write process described above. When the non-volatile memory 43 has data in the identified track, in order to renew the data in the correct order in the auxiliary memory unit 37, in a second process, the write data corresponding to the identified track supplied from the host computer 31 is written into the auxiliary memory unit 37 after the data stored in the non-volatile memory 43 were supplied to the auxiliary storage unit 37 and written therein. The second process described above is often referred to as a write-back process and a pass-through write process.

According to the conventional control system for controlling the cache memory unit including the nonvolatile memory, the write data supplied from the host computer is always processed according to the fast write process while the nonvolatile memory is in a state where the number of unused blocks in the nonvolatile memory is larger than the number of blocks corresponding to the data supplied from the host computer. Therefore, in a state where the number of unused blocks in the nonvolatile memory 43 is small, a probability that the write data supplied from the host computer is processed according to the write-back process and the pass-through write process increases. In the write-back and pass-through write processes, the auxiliary storage unit is accessed twice, so that the time required for the write-back process and the pass-through write process is at least twice as long as that required for the pass-through write process.

SUMMARY OF THE INVENTION

It is therefore a general object of the present invention to provide a new and useful control system for controlling a cache memory unit with a non-volatile memory, in which the disadvantages of the previously discussed prior art are eliminated.

A more specific object of the present invention is to provide a control system for controlling a cache memory unit having a non-volatile memory, by which a probability that a write-back process and a pass-through write-in process are carried out in a state in which the number of non- used blocks in the non-volatile memory is small, can be reduced.

The above-mentioned objects of the present invention are achieved by means of a control system for controlling an auxiliary storage unit and a cache memory unit comprising a cache memory device and a non-volatile memory device based on a write command supplied together with refresh data from an external unit to write the refreshed data into a specified storage area of the auxiliary storage unit, the control system comprising: first determining means for determining whether an unused area in the non-volatile memory device is smaller than a reference area, the unused area being an area containing no data; a first processing means for performing a first process when the first determining means determines that the unused area in the non-volatile storage means is not smaller than the reference area, the first process including a step for writing the updated data to both the cache storage means and the non-volatile storage means, the updated data written to the non-volatile storage means being written to the identified storage area of the auxiliary storage means asynchronously with the write command; a second determining means coupled to the first determining means for determining whether the non-volatile storage means contains data corresponding to the identified storage area when the first determining means determines that the unused area in the non-volatile storage means is smaller than the reference area; a second processing means for performing a second process when the second determining means determines that the non-volatile storage means does not contain data corresponding to the identified storage area, the second process comprising a step of writing the updated data into both the cache memory device and the identified zone of the auxiliary storage device; third determining means, coupled to the second determining means, for determining whether or not the unused area in the non-volatile memory device can be used to store the maximum amount of data to be written into the auxiliary storage unit if the second determining means has determined that the non-volatile memory device contains data corresponding to the identified storage zone; third processing means for performing the first process if the third determining means has determined that the unused area in the non-volatile memory device can be used to store said maximum amount of data to be written into the auxiliary storage unit; and fourth processing means for performing a third process when the third determining means has determined that the unused area in the non-volatile storage means cannot be used for storing the maximum amount of data to be written into the auxiliary storage unit, the third process comprising a first step of writing the data stored in the non-volatile storage means into the identified storage region of the auxiliary storage unit, and a second step of writing the updated data into both the cache storage means and the identified storage region of the auxiliary storage unit after the first step.

According to the present invention, in a case where the unused area in the non-volatile storage device is smaller than the reference area, the area in the non-volatile storage device is prevented from being used for a new identified track and the unused area in the non-volatile storage device is preferentially used for storing data corresponding to the identified track whose data has been stored in the cache storage device. Thus, the probability that the third process (the write-back and pass-through write process) in which the auxiliary storage unit is accessed twice is carried out is reduced.

Additional objects, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a diagram illustrating a control system for controlling a cache memory unit and an auxiliary memory unit according to a pass-through write process;

Fig. 2 is a diagram illustrating a control system for controlling a cache memory unit and an auxiliary memory unit in accordance with a fast write process;

Fig. 3 is a flow chart illustrating the principles of a process performed in the control system according to an embodiment of the present invention;

Fig. 4 is a block diagram illustrating a control system according to the embodiment of the present invention;

Fig. 5A is a block diagram illustrating a structure of each channel adapter (CA) shown in Fig. 4;

Fig. 5B is a block diagram illustrating a structure of each device adapter (DA) shown in Fig. 4;

Fig. 5C is a block diagram illustrating a structure of both a resource manager unit (RM) and a cache function engine unit (CFE);

Fig. 6 is a diagram illustrating a structure of a cache control table and an LRU table stored in a memory as shown in Fig. 5C ; and

Figures 7A to 7E are flowcharts illustrating the processes for writing data into the auxiliary storage unit and the cache storage unit, which data has been supplied from a host computer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description will now be given of the principle of a process carried out by a control system according to an embodiment of the present invention, with reference to Fig.3.

The process shown in Fig.3 is carried out, for example, by the cache control unit 41 shown in Fig.2. Referring to Fig.3, at step 100, a write command is received together with write data supplied from the host computer 31. Then, at step 101, it is determined whether the number (NUNVS) of unused blocks in the nonvolatile memory 43 is smaller than a predetermined reference value (NREF). If it is determined at step 101 that the number (NUNVS) of unused blocks in the nonvolatile memory 43 is smaller than the reference value (NREF), at step 102, the cache control unit is controlled in accordance with the fast write process. That is, the write data supplied from the host computer 31 is stored in the non-volatile memory 43 in a state where the cache control unit 41 is not connected to the auxiliary storage unit 37. Thereafter, the data stored in the non-volatile memory 43 is written into the auxiliary storage unit 37 asynchronously with the write command from the host computer 31. If it is determined in step 101 that the number (NUNVS) of unused blocks in the non-volatile memory 43 is smaller than the reference value NREF, it is determined in step 103 whether the non-volatile Memory 43 contains or does not contain data on a track identified in cache memory 35. If non-volatile memory 43 contains no data on the identified track, at step 104, the write data is directly written into both auxiliary storage unit 37 and cache memory 35 in accordance with the pass-through write process to prevent the number of unused blocks in non-volatile memory 43 from increasing. In this state, when the data stored in non-volatile memory 43 is written into auxiliary storage unit 37 in accordance with the write-back process and asynchronously with the write command, the number of unused blocks in non-volatile memory 43 increases. On the other hand, if it is determined at step 103 that the nonvolatile memory 43 contains data on the identified track, it is determined at step 105 whether or not the data for one track, which is the maximum amount of data for one write operation, can be written into the nonvolatile memory 43. If it is determined at step 105 that the data for one track can be stored in the nonvolatile memory 43, the cache memory unit is controlled in accordance with the fast write process at step 102. If it is determined at step 105 that the data for one track cannot be stored in the nonvolatile memory 43, the cache memory unit and the auxiliary memory unit 37 are controlled in accordance with the write-back and pass-through write process at step 106. That is, after the data stored in the nonvolatile memory 43 is written into the auxiliary storage unit 37 in accordance with the write-back process, the write-in data is written into the auxiliary storage unit 37 in accordance with the pass-through write process.

According to the above-explained writing process, if the number of unused blocks in the non-volatile memory 43 is small (less than the reference number), that the number of blocks corresponding to the data on the newly identified tracks increases, and the unused blocks in the non-volatile memory 43 are preferentially used to store data corresponding to the identified track in the cache memory 35. That is, if the amount of data on the newly identified track in the non-volatile memory 43 is not increased, the probability that the data stored in the non-volatile memory 43 is accessed in the write-in process is reduced. Thus, the probability that the write-back and pass-through write-in process in which the auxiliary storage unit is accessed twice is also reduced.

A description will now be given of an embodiment of the present invention with reference to Figures 4 to 7E.

Referring to Fig. 4, which shows a data processing system having a control system according to an embodiment of the present invention, the data processing system includes a host computer 101, a channel 12, a file control unit 14, a first disk unit 15(0), and a second disk unit 15(1). The file control unit 14 controls the first and second disk units 15(0) and 15(1) in accordance with commands supplied from the host computer 10 via the channel 12. The file control unit 14 includes a resource manager unit 140, a cache function engine unit 145, a cache storage unit 146, a first input/output system, and a second input/output system. The first and second input/output systems each have driver/receivers 141 (0) and 141 (1) (DV/RV) coupled to the channel 12, channel adapters 142 (0) and 142 (1) (CA), device adapters 143 (0) and 143 (1) (DA), and a driver/receiver 144 (0) (DV/RV) coupled to the first disk unit 15 (0) and a driver/receiver unit 144 (1) (DV/RV) coupled to the second disk unit 15 (1). The first input/output system is connected to the resource manager unit 140, the The second input/output system is also coupled to the resource manager unit 140, the cache function engine unit 145 and the cache memory unit 146 via a c-bus 148 (1). The resource manager unit 140 controls all parts of the file control unit 14.

The cache function engine unit 145 executes processes related to controlling the cache memory unit 146. The cache memory unit 146 has a cache memory 146a and a non-volatile memory 146b.

Each of the channel adapters 142 (0) and 142 (1) is configured, for example, as shown in Fig. 5A. According to Fig. 5A, each channel adapter includes a microprocessor unit 20 (MPU), a bus interface logic unit 21, a channel interface logic unit 22 and a memory 23, which are connected to each other by a bus. The bus interface logic unit 21 is coupled to the c-bus 148 (0) or 148 (1). The channel interface logic unit 22 is coupled to the channel 12. Various control programs executed by the MPU 20 are stored in the memory 23.

Each of the device adapters 143 (0) and 143 (1) is configured as shown in Fig. 5B. As shown in Fig. 5B, each device adapter has a microprocessor unit (MPU) 24, a bus interface logic unit 25, a device interface logic unit 26, and a memory 27, which are connected to each other by a bus. The bus interface logic unit 25 is coupled to a corresponding c-bus 148 (0) or 148 (1). The device interface logic unit 26 is coupled to a corresponding disk unit 15 (0) or 15 (1). Various control programs executed by the MPU 24 are stored in the memory 27.

The resource manager unit 140 and the cache function machine unit 145 are each designed, for example, as shown in Fig.5C. According to Fig.5C, a microprocessor unit 50 (MPU) is provided with a first bus interface 51, a second bus interface 52, a first memory 53a and a second memory 53b via a bus. The first bus interface 51 is coupled to the c-bus 148 (0) and the second bus interface 52 is coupled to the c-bus 148 (1). Various control programs executed by the MPU 50 are stored in the first memory 53a. A task management table used for managing the file control unit 14 is stored in the second memory 53b of the resource manager unit 140. A cache management table used for controlling the cache memory unit 146 is stored in the second memory 53b of the cache function engine unit 145.

The cache management table stored in the second memory 53b of the cache function engine unit 145 is configured, for example, as shown in Fig.6. As shown in Fig.6, the cache management table has an unused memory table, an unused NSV (Nonvolatile Storage Device) table, and an LRU (Least Recently Used) table. The unused memory table indicates unused blocks in the cache memory 146a in which data has not yet been stored. The unused NSV table indicates unused blocks in the nonvolatile memory 146b in which data has not yet been stored. The LRU table indicates the relationships between the track addresses identifying tracks in the disk units 15(0) 15(1) and the used blocks consisting of blocks used to store the data on the tracks of the disk units 15(0) and 15(1) in the cache memory 146a and the non-volatile memory 146b. The cache function engine unit 145 controls the cache storage unit 146 with reference to the cache management table, and the cache management table is updated while the cache function engine unit 145 controls the cache storage unit 146.

A description will now be given of the operations of the file control unit 14 in a case where updated data is written into the disk unit 15 (0) or 15 (1). In this case, the file control unit 14 operates in accordance with the processes shown in Figures 7A to 7E.

When the host computer sends a write command to the channel 12, a process shown in Fig.7a starts. Next, it is assumed that the first disk unit 15(0) has been accessed. The channel adapter 142(0) receives the write command from the channel 12 at step 200. The write data and a track into which write data should be written in the first disk unit 15(0) are specified by the write command. When the channel adapter 142(0) receives the write command, the channel adapter 142(0) sends the write command to the cache function engine unit 145. Then, the cache function engine unit 145 checks the cache status concerning the identified track with reference to the cache management table shown in Fig.6, which is done at step 201. That is, the status of the blocks used for the identified track in the cache memory 146a and the nonvolatile memory 146b and the like are checked. At this step, for example, the number NUNVS of unused blocks consisting of blocks not used for storing the data in the nonvolatile memory 146b is detected. The cache function engine unit 145 determines whether the number NUNSV of unused blocks in the nonvolatile memory 146b is less than a predetermined reference value NREF, which occurs in step 202.

When it is determined that the number NUNSV of unused blocks in the nonvolatile memory 146b is not less than the reference value NREF, a process shown in Fig.7B starts. The process shown in Fig.7B is called a fast write process. The cache function engine unit 145 instructs the channel adapter 142 (0) to to start a fast write process, which is done at step 210. Then, the channel adapter 142(0) writes the write data sent from the channel 12 into the non-volatile memory 146b at step 211. When step 211 is completed, the file control unit 14 terminates the data write process. Thereafter, the data stored in the non-volatile memory 146 is written into the first disk unit 15(0) based on the control of the resource manager 140 and the cache function engine unit 145 asynchronously with the write command from the host computer 10.

On the other hand, if the function engine unit 145 determines at step 202 that the number NUNSV of unused blocks in the nonvolatile memory 146b is less than the reference value NREF, the cache function engine unit 145 checks the number NCACHE of blocks used for the identified track in the cache memory 146a by referring to the cache management table, which occurs at step 203.

Then, the cache engine unit 145 determines whether the non-volatile memory 146b contains blocks used for the identified track, which occurs in step 204. If it is determined that the non-volatile memory 146b does not contain blocks used for the identified track, a process shown in Fig.7E and Fig.7D is started. The process shown in Fig.7E and Fig.7D is called a pass-through write process. After step 204, the cache engine unit 145 instructs the channel adapter 142(0) to start the pass-through write process, which occurs in step 204. The channel adapter 142(0) is disconnected from the channel 12 at step 241, and then the channel adapter 142(0) instructs the resource manager unit 140 to execute the pass-through write process at step 242. Then the resource manager unit 140 instructs the adapter device 143(0) to start the pass-through write process at step 243. When the device adapter 143(0) is connected to the first disk unit 15(0), the device adapter 143(0) informs the resource manager unit 140 that the device adapter 143(0) has been coupled to the first disk unit 15(0), which occurs in step 244. After step 244, the process proceeds to step 227 shown in Fig.7D. If the device adapter 143(0) is coupled to the first disk unit 15(0), described above, the resource manager 140 instructs the channel adapter 142(0) to re-couple to the channel 12, which occurs in step 227. The channel adapter 142(0) is re-coupled to the channel 12 based on the command from the resource manager unit 140, which occurs in step 228. When the channel adapter 142(0) has been fully recoupled to the channel 12, the channel adapter 142(0) informs the resource manager unit 140 that the channel adapter 142(0) has been recoupled to the channel, which occurs in step 229. The resource manager unit 140 then instructs both the channel adapter 142(0) and the device adapter 143(0) to start the pass-through write process, which occurs in step 230. Thereafter, the channel adapter 142(0) receives the write data supplied from the channel 12 via the driver/receiver 141(0) and writes the write data into the cache memory 146a, which occurs in step 231. After this time, the write data is supplied from the channel adapter 142(0) to the device adapter 143(0). Then, the device adapter 143(0) writes the write data into the first disk unit 15(0). When the step 231 is completed, the file control unit 14 ends the process of writing the data.

Referring to Fig.7A, when the cache engine unit 145 determines that the non-volatile memory 146b contains blocks used for the identified track, the cache engine unit 145 determines whether the number NUNSV of unused blocks in the non-volatile memory 146b is equal to or greater than a difference between the number No of blocks for a track and the number NNVS of the blocks used for the identified track or not. Since the maximum amount of data that can be updated in one operation corresponds to one track, when the number NUNSV of the unused blocks in the nonvolatile memory 146b is equal to or greater than the difference between the numbers No and NNVS, the write data supplied from the host computer 10 can be written into the nonvolatile memory 146b using the unused blocks. That is, when the cache function engine unit 145 determines that the number NUNVS of the unused blocks in the nonvolatile memory 146b is equal to or greater than the difference between the numbers No and NNVS, the fast write process shown in Fig.7B is carried out in the same manner as described above.

On the other hand, if the number NUNSV of unused blocks in the nonvolatile memory 146b is smaller than the difference between the number No of blocks for one track and the number NNSV of blocks used for the identified track in the nonvolatile memory 146b, a case may occur where all write data is not stored in the nonvolatile memory 146b. Thus, if the cache function engine unit 145 determines that the number NUNVS of unused blocks in the nonvolatile memory 146b is smaller than the difference between the numbers No and NNVS, the write-back process and the pass-through write process are executed. That is, the process shown in Figs. 7C and 7D is started.

The cache engine unit 145 sends data of approximately the number NCACHE of blocks used for the identified track in the cache memory 146a and data in the size of the number NNVS of blocks used for the identified track in the non-volatile memory 146b to the channel adapter 142(0) and then the cache engine unit 145 instructs the channel adapter 142(0) to start the write-back process and the pass-through write process, which occurs in step 220. Then, the channel adapter 142(0) is disconnected from the channel 12 in step 221. The channel adapter 142(0) sends request data of the write-back process and the pass-through write-in process to the resource manager unit 140 in step 222. When the resource manager unit 140 receives the request data, the resource manager unit 140 instructs the device adapter 143(0) to perform the write-back process and the pass-through write-in process in step 223. The device adapter 143(0) then sends a request to obtain the write-back data to the cache engine unit 145 in step 224. The write-back data consists of data corresponding to the identified track and is stored in the non-volatile memory 146b. In response to the above-mentioned request from the device adapter 143(0), the cache function engine unit 145 reads the write-back data from the non-volatile memory 146b and sends it to the device adapter 143(0) at step 225. Thereafter, the device adapter 143(0) writes the write-back data to the identified track in the first disk unit 15(0) at step 226. The device adapter 143(0) then informs the resource manager unit 140 that the channel adapter 142(0) is again coupled to the channel 12.

When the write-back data stored in the nonvolatile memory 146b is written to the identified track in the first disk unit 15(0), the process shown in Fig.7D is carried out in the same manner as the pass-through write process described above, so that the write data supplied from the host computer 10 is written to both the cache memory 146b and the first disk unit 15(0).

In the above-explained embodiment of the present invention, the reference value NREF which corresponds to the number NUNVS of unused blocks in the non-volatile memory 146b is compared depends on the probability that accessed data is present in the cache memory 146a (the data hit) obtained in the data processing system and the like.

Claims (5)

1. A control system for controlling an auxiliary storage unit (15(0), 15(1)) and a cache storage unit (146) having a cache storage device (146a) and a non-volatile storage device (146b) on the basis of a write command supplied together with updated data from an external unit (10, 12) to write the updated data into an identified memory zone of the auxiliary storage unit (15(0), 15(1)), which control system is characterized by: a first determining means (202) for determining whether an unused area in the non-volatile memory means (146b) is smaller than a reference area, the unused area being an area that does not contain data; first processing means for performing a first process (210, 211) when said first determining means (202) determines that said unused area in said non-volatile storage means (146b) is not smaller than said reference area, said first process comprising a step of writing said updated data into both said cache storage means (146a) and said non-volatile storage means (146b), said updated data written into said non-volatile storage means (146b) being written into said identified storage area the auxiliary storage device (15(0), 15(1)) is written asynchronously to the write command; a second determining means (204) coupled to the first determining means (202) for determining whether the non-volatile storage device (146b) contains data corresponding to the identified storage zone, if the first determining means (202) has determined that the unused area in the non-volatile storage device (146b) is smaller than the reference area; second processing means (240-244, 227-231) for performing a second process when the second determining means (204) has determined that the non-volatile storage means (146b) does not contain data corresponding to the identified storage zone, the second process comprising a step of writing the updated data into both the cache storage means (146a) and the identified zone of the auxiliary storage means (15(0), 15(1)); a third determining means (205) coupled to the second determining means (204) for determining whether or not the unused area in the non-volatile storage device (146b) can be used to store a maximum amount of data in the auxiliary storage unit (15(0), 15(1)) when the second determining means (204) has determined that the non-volatile storage device (146b) contains data corresponding to the identified storage zone; a third processing device for carrying out the first process (210, 211) when the third determining device (205) has determined that the unused area in the non-volatile storage device (146b) can be used to store the maximum amount of data in the auxiliary storage unit (15(0),15(1)); and a fourth processing means (220-231) for performing a third process when the third determining means (205) has determined that the unused area in the non-volatile storage means (146b) cannot be used to store the maximum amount of data in the auxiliary storage unit (15(0), 15(1)), the third process including a first step of writing the data stored in the non-volatile storage device (146b) into the identified storage zone of the auxiliary storage unit (15(0), 15(1)), and a second step of writing the updated data into both the cache storage device (146a) and the identified storage zone of the auxiliary storage unit (15(0), 15(1)) after the first step. 2. Control system according to claim 1, characterized in that the auxiliary storage unit comprises a disk unit. 3. Control system according to claim 2, characterized in that the maximum amount of data to be written into the auxiliary storage unit (15(0), 15(1)) is defined as one track of the disk unit. 4. Control system according to claim 3, characterized in that the track is formed of a plurality of blocks, and that the data for each of the blocks can be written into or read out from the auxiliary storage unit (15(0), 15(1)) and the cache storage unit (146). 5. A control system according to claim 4, characterized in that the first determining means comprises means for determining whether or not a number of the unused blocks in the non-volatile memory means (146b) is less than a predetermined reference value.