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DE69126292D1 - PMOS-Wortleitung Speisespannungsverstärkungsschaltung für DRAM - Google Patents

PMOS-Wortleitung Speisespannungsverstärkungsschaltung für DRAM

Info

Publication number
DE69126292D1
DE69126292D1 DE69126292T DE69126292T DE69126292D1 DE 69126292 D1 DE69126292 D1 DE 69126292D1 DE 69126292 T DE69126292 T DE 69126292T DE 69126292 T DE69126292 T DE 69126292T DE 69126292 D1 DE69126292 D1 DE 69126292D1
Authority
DE
Germany
Prior art keywords
dram
supply voltage
word line
amplification circuit
voltage amplification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126292T
Other languages
English (en)
Other versions
DE69126292T2 (de
Inventor
Sang Hoo Dhong
Wei Hwang
Yoichi Taira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69126292D1 publication Critical patent/DE69126292D1/de
Application granted granted Critical
Publication of DE69126292T2 publication Critical patent/DE69126292T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
DE69126292T 1991-01-02 1991-10-28 PMOS-Wortleitung Speisespannungsverstärkungsschaltung für DRAM Expired - Fee Related DE69126292T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/636,840 US5075571A (en) 1991-01-02 1991-01-02 PMOS wordline boost cricuit for DRAM

Publications (2)

Publication Number Publication Date
DE69126292D1 true DE69126292D1 (de) 1997-07-03
DE69126292T2 DE69126292T2 (de) 1997-12-11

Family

ID=24553555

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126292T Expired - Fee Related DE69126292T2 (de) 1991-01-02 1991-10-28 PMOS-Wortleitung Speisespannungsverstärkungsschaltung für DRAM

Country Status (4)

Country Link
US (1) US5075571A (de)
EP (1) EP0493659B1 (de)
JP (1) JPH0817226B2 (de)
DE (1) DE69126292T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5491432A (en) * 1992-08-07 1996-02-13 Lsi Logic Corporation CMOS Differential driver circuit for high offset ground
US5386151A (en) * 1993-08-11 1995-01-31 Advanced Micro Devices, Inc. Low voltage charge pumps using p-well driven MOS capacitors
US5600598A (en) * 1994-12-14 1997-02-04 Mosaid Technologies Incorporated Memory cell and wordline driver for embedded DRAM in ASIC process
US5530668A (en) * 1995-04-12 1996-06-25 Ramtron International Corporation Ferroelectric memory sensing scheme using bit lines precharged to a logic one voltage
US5723994A (en) * 1996-06-10 1998-03-03 Etron Technology, Inc. Level boost restoration circuit
US5781557A (en) * 1996-12-31 1998-07-14 Intel Corporation Memory test mode for wordline resistive defects
US6147914A (en) * 1998-08-14 2000-11-14 Monolithic System Technology, Inc. On-chip word line voltage generation for DRAM embedded in logic process
US6468855B2 (en) 1998-08-14 2002-10-22 Monolithic System Technology, Inc. Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
US6509595B1 (en) 1999-06-14 2003-01-21 Monolithic System Technology, Inc. DRAM cell fabricated using a modified logic process and method for operating same
US6573548B2 (en) 1998-08-14 2003-06-03 Monolithic System Technology, Inc. DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
US6420908B2 (en) * 1999-01-05 2002-07-16 Infineon Technologies Ag Sense amplifier
US6388931B1 (en) 1999-02-25 2002-05-14 Micron Technology, Inc. Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
US6434048B1 (en) 2001-07-20 2002-08-13 Hewlett-Packard Company Pulse train writing of worm storage device
US6503793B1 (en) * 2001-08-10 2003-01-07 Agere Systems Inc. Method for concurrently forming an ESD protection device and a shallow trench isolation region
KR100630529B1 (ko) * 2004-11-15 2006-09-29 주식회사 하이닉스반도체 반도체 메모리 장치의 워드라인 구동회로
US7323379B2 (en) 2005-02-03 2008-01-29 Mosys, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
US7230454B2 (en) * 2005-02-18 2007-06-12 Cirrus Logic, Inc. Serial audio output driver circuits and methods
US20060267059A1 (en) * 2005-05-25 2006-11-30 Macronix International Co., Ltd. Peripheral circuit architecture for array memory
US20060267064A1 (en) * 2005-05-31 2006-11-30 Infineon Technologies Ag Semiconductor memory device
US8097915B2 (en) * 2005-05-31 2012-01-17 Qimonda Ag Semiconductor memory device
US7274618B2 (en) 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
US8362806B2 (en) * 2009-06-26 2013-01-29 Intel Corporation Keeper circuit

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192359A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 半導体装置
US4514829A (en) * 1982-12-30 1985-04-30 International Business Machines Corporation Word line decoder and driver circuits for high density semiconductor memory
US4639622A (en) * 1984-11-19 1987-01-27 International Business Machines Corporation Boosting word-line clock circuit for semiconductor memory
US4618784A (en) * 1985-01-28 1986-10-21 International Business Machines Corporation High-performance, high-density CMOS decoder/driver circuit
US4647956A (en) * 1985-02-12 1987-03-03 Cypress Semiconductor Corp. Back biased CMOS device with means for eliminating latchup
JP2548908B2 (ja) * 1985-04-13 1996-10-30 富士通株式会社 昇圧回路
US4678941A (en) * 1985-04-25 1987-07-07 International Business Machines Corporation Boost word-line clock and decoder-driver circuits in semiconductor memories
JPS6238592A (ja) * 1985-08-14 1987-02-19 Fujitsu Ltd 相補型メモリの行選択線駆動回路
US4742492A (en) * 1985-09-27 1988-05-03 Texas Instruments Incorporated EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor
US4701642A (en) * 1986-04-28 1987-10-20 International Business Machines Corporation BICMOS binary logic circuits
US4843261A (en) * 1988-02-29 1989-06-27 International Business Machines Corporation Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories
JP2550138B2 (ja) * 1988-03-18 1996-11-06 株式会社日立製作所 バイポーラトランジスタと電界効果トランジスタとを有する半導体集積回路装置
JP2509690B2 (ja) * 1989-02-20 1996-06-26 株式会社東芝 半導体装置
US4999518A (en) * 1989-12-08 1991-03-12 International Business Machines Corp. MOS switching circuit having gate enhanced lateral bipolar transistor

Also Published As

Publication number Publication date
EP0493659A2 (de) 1992-07-08
US5075571A (en) 1991-12-24
EP0493659B1 (de) 1997-05-28
JPH06209090A (ja) 1994-07-26
JPH0817226B2 (ja) 1996-02-21
EP0493659A3 (en) 1993-03-24
DE69126292T2 (de) 1997-12-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee