DE69123717T2 - SWITCHING DEVICE - Google Patents

Abstract

PCT No. PCT/BE91/00059 Sec. 371 Date Jun. 22, 1992 Sec. 102(e) Date Jun. 22, 1992 PCT Filed Aug. 22, 1991 PCT Pub. No. WO92/03864 PCT Pub. Date Mar. 5, 1992.A switching device for an on-off switching of electrical current operable units includes a first series of first switches which are each time connected with an address generator which is connected via a bus with a branching member, which branching member is further connected with a second series of second switches on which the units are connectable. The branching member further includes a control signal generator which is connected with the address generator and which is provided for, under control of the control signals, fetching the address each time under the form of partial addresses from the address generator.

Description

The present invention relates to a switching device for switching on and off units that can be operated with electrical current, in particular units that can be connected to the power supply network, which has the following:

a first row of switches connected to a branching element which is further connected to first inputs of a second row of switches, each of which has a first output to which the units can be connected and a second input to which a power supply, in particular the power supply network, can be connected; and which further comprises at least one address generator, so that each address generator is connected to a first input of at least one switch of the first row in order to assign an address to the switch connected thereto, the address corresponding to a further address assigned to the unit controlled by the switch; the branching element being connected to a bus provided with a predetermined number n of transmission lines for communication between the one or more address generators and the branching element.

Such a switching device is known from EP 0 119 187 and is intended for use in private households or in commercial installations. The units operable with electric current are formed, for example, by lighting points, household appliances, machines and computers. The first row of switches is arranged in the building either at different locations or at the same location, depending on the type and function of the building, and their purpose is to control the units, in particular to switch them on and off. The switches of the first row are connected to a branching element formed, for example, by a distribution box or a distribution panel, from which current or control signals are fed to a second row of switches. This second row of switches is formed, for example, by relays or remote switches, which are then used for ensure that the units are supplied with the necessary current and voltage to supply them with the required electrical energy.

A disadvantage of this known device is that the signal transmission uses signal packets, each of which has its own source and destination address label and can therefore operate on two transmission lines. In addition, such a device is hardly flexible.

The aim of the invention is to provide a solution for the above-mentioned disadvantages.

A switching device according to the invention is characterized in that

that a second input of each switch in the first row is connectable to a low voltage power supply source;

that the branching element has a control signal generator connected to r transmission lines. (2 ≤ r ≤ n) of the n transmission lines;

that the one or more address generators is/are provided with a control input connected to the r transmission lines to receive control signals generated by the control signal generator;

and that the one or more address generators have an output connected to the branching element via the remaining n-r transmission lines for transmitting to the branching element a t-th partial address (1 ≤ t ≤ 2r-1) under the control of a respective t-th control signal, each t-th partial address forming a corresponding t-th part of the address generated by the address generator that received the control signal.

By assigning an address to each switch of the first row and further by transporting the address via a bus with a predetermined number of transmission lines, one obtains on the one hand a reduced number of wires between the first switches and the branching element and on the other hand a very flexible device so that a modification to be made by assigning a different address can be implemented in a simple manner. Furthermore, by using 2r-1 control signals the addressing possibilities can be increased without the need for additional wires.

A first preferred embodiment of a switching device according to the invention is characterized in that the number r of transmission lines is equal to two. In this way, the number of address possibilities is increased by using a simple two-bit control signal.

A second preferred embodiment of a switching device according to the invention is characterized in that the second row of switches is arranged according to a matrix and that each switch of the second row is assigned a matrix address which indicates a row and a column of the matrix, the branching element being provided to convert a received address into a corresponding matrix address. The conversion into a matrix address is simple and can be implemented with only a few components.

The address generator advantageously has a programmable memory. Modifications can then be made very easily by programming the new address, which can be done by the users themselves if necessary, thus eliminating the need to call in an electrician.

A third preferred embodiment of a switching device according to the invention is characterized in that the switching device further comprises:

a control pulse generator, a comparison element and a scanning element;

wherein the control pulse generator is provided to generate and provide first and second control pulses at a control signal output in order to switch all connected units to a first position and a second position, respectively, wherein the control signal output is connected to a control signal input of the scanning element;

the sampling element having an output connected to the address input of the second switches, the sampling element being arranged to generate, under the control of a received control pulse, a series of sampling signals to sequentially sample each of the second switches and to generate each time a sampling pulse representing an actual position of a sampled switch, the sampling element being connected to a sampling signal input of the comparison element;

and wherein the comparison element has a first input connected to the second switches and a control signal input for receiving the first and second control pulses, wherein the comparison element is arranged to compare, for each sampled second switch, the sampling pulse with the control pulse present at the control signal input and to generate first and second respective comparison signals indicating a correspondence or non-correspondence of the compared pulses, wherein the comparison element activates the branching element with the second comparison signal to switch the sampled second switch. This enables all connected units to branch at one and the same point and from one and the same switching unit, regardless of the position in which they were.

Preferably, the sampling element has a counter to generate consecutive addresses as a sampling signal that are assigned to the first switches. This enables a simple implementation.

A fourth preferred embodiment of a switching unit according to the invention is characterized in that the control pulse generator has an alarm detector. The alarm unit is thus able to switch on all lighting points when a break-in is detected.

The invention will now be described by way of example, which is illustrated in the drawings, in which:

Fig. 1 is a schematic view of a switching device according to the invention with units connected thereto;

Fig. 2 a first row of switches with their address generator;

Fig. 3 shows an example of a branching element according to the invention;

Fig. 4 shows an example of a control pulse generator, a sampling element and a comparison element belonging to a switching device according to the invention;

Fig. 5 a detail from the second row of switches.

In the drawings, identical or analogous elements are assigned the same reference symbol.

A switching device according to the invention is shown schematically in Fig. 1 and comprises a first row of switches 1-1, 1-2, ... 1-m (Mε N). The switches 2-1, 2-2, ... 2-m are, for example, controlled by a push button, as in a buildings, or by another monostable switch used to control the switching on of a lamp. It is understood that other types of switches, such as touch contacts, could also be used. Each switch 2-k (1 ≤ k ≤ m) is connected to an address generator 3-k each time. In Fig. 1 each switch is connected to only one address generator, but it is also possible to connect several switches to the same address generator.

The address generators are connected to a bus 4 which has a number of transmission lines, for example eight. A predetermined number n, for example n = 5, is provided for communication between the address generator 3 and the branching element 5. By using such a bus, the entire assembly becomes much simpler, since standard components and connectors are used. The remaining lines from the bus are used for the power supply, for example.

The branching element 5 is intended for collecting the addresses from the address generator 3 and for converting the received addresses into matrix addresses in order to address the switches 8 of the second row of switches via the transmission line 6. The second row of switches comprises a collection of switches which are preferably organized according to the rows (i) and columns (j) of a matrix. The switches 8/(i,j) are preferably formed by teleswitches, for example of the type 312/346512-024 or 312/346511-024 manufactured by Vynckier, and they are provided with a pulse switch with a mechanically coupled signal contact. These switches 8/(i,j) themselves control units which are operated with electric current, 9-p (1 ≤ p ≤ z) (z = total number of elements) and which have to be connected to these switches, these units being connected for example by lighting points in a building, electrical devices such as alarm systems, computers or the control of a central heating system. These switches 8/(i,j) have a further input 7 which is connected to a power supply, for example the power supply network, and switch this supply towards the units 9-p in order to supply them with the required power.

Fig. 2 shows an example of a first series of switches with their address generator. For simplicity, only two switches 2 and two address generators 3 are shown in this example, but it will be understood that more switches and address generators can be connected in an identical manner. The switch 10 is connected on the one hand to a low voltage power supply source Vcc, for example 6 or 12 volts direct current, and on the other hand to a capacitor 11 and a resistor 12. Connected in parallel to the capacitor 11 and the resistor 12 is a first diode 13. The cathode of the first diode is connected to the anode of a second diode belonging to an opto-triac 14, for example of the type K3020P, manufactured by Telefunken. The anode of the first diode is connected on the one hand to earth and on the other hand via a resistor 15 to the cathode of the second diode.

The opto-triac 14 enables a galvanic isolation between a switch 2 and the address generator 3. It goes without saying that other connections between the address generator and the switch are also possible, such as a capacitive or inductive connection or possibly even a galvanic connection.

The branching of the components 11, 12, 13, 14 and 15 serves primarily to suppress certain mechanical disturbances in the switch 10, such as overcoming a Switch hold state. Closing the switch 10 allows the current supplied from the source Vcc to flow to the capacitor 11, so that the latter is charged. When the capacitor 11 is charged, the latter must be discharged via the second diode of the opto-triac 14, since the current cannot flow from the capacitor to earth via the first diode 13. This causes the opto-triac 14 to be activated and a switching signal to be transmitted to the address generator. By discharging the capacitor, a current flow is maintained in the circuit formed by the components 13, 14 and 15. If the switch 10 now remains on, for example, this has no consequences for the address generator, since the latter has only received a signal via the opto-triac 14 and, after the capacitor has been charged, a current originating from the switch 10 can only flow to earth via the resistor 14.

The address generator 3 has a memory element 18, preferably a programmable memory which enables modification of the programmed address. This memory element is formed, for example, by a DIP switch (dual-in-line package). The address assigned to the switch connected to it is stored in the memory element 18. The memory element of the address generator 3-1 therefore stores, for example, the address assigned to switch 2-1. This address then corresponds to a further address assigned to a switch 8 from the second row and thus to an element 9-i. The outputs of this memory element 18 are connected to the bus 4 via the transmission lines 25-a, 25-b in which diodes 19 are provided. Each line of 25-a and 25-b is connected to the cathode or anode of a diode belonging to the row of diodes 19-a or 19-b. The transmission lines 20, 21 and 22 of the bus 4 are each connected to both a diode of the series 19-a and a diode of the series 19-b and serve as a communication line for transporting the address. A line 23 or 24 from the bus 4 is connected to the cathode or anode of a diode 16 or 17. To describe the operation of the address generator, the operation of the branching element must first be explained.

Fig. 3(a + b + c) shows an example of a branching element 5 according to the invention. An input of the branching element is connected to the bus 4. The transmission lines 20 to 24 of the bus 4 are connected to a first 27 and a second flip-flop 28, respectively, via a known transmission unit 26, which has at least a reset function. A clock input of the first and second flip-flops is connected to the communication line 24 and 23, respectively, via the transmission unit 26. The outputs 29 and 30 (Q0, Q1, Q2) of the first 27 and second flip-flops 28 transmit the signals present on the communication lines 20, 21 and 23, respectively. The input D3 of the first and second flip-flops is connected to the power supply source Vcc. The lines 29 and 30 are connected to the inputs of a first decoder 31 and a second decoder 32, respectively. The decoders are designed to convert a received digital address into a matrix address for addressing the switches 8/(i,j) of the second row of switches 8. The decoder 31 provides column addressing, while the decoder 32 provides row addressing. The decoders are activated by a signal applied to their input D and originating from an output Q3 of the first flip-flop 27. The output Q3 of the flip-flop 27 is connected to a line 34 via a diode 33.

An output Q3 of the second flip-flop 28 is connected via a diode 35 to a line 34 and via a line 36 to the base of a first transistor 37, the collector of which is connected to the voltage supply source Vcc and the emitter of which is connected to a line 24. The line 36 further comprises a branch point 83. This line 36 carries a row selection signal, as will be described below. The line 34 is connected via an inverter 38 to the base of a second transistor 39, the emitter of which is connected to ground and the collector of which is connected to a line 23. The transistors 37 and 39 form a control signal generator, as will be described below. A branch point 84 is connected to an output Q3 of the second flip-flop 28 and carries a column output signal, as will be explained below.

Each output of the decoders 31 and 32 is connected to a respective gate of a MOS-FET transistor 40 and 41, respectively. The source of each MOS-FET transistor 40 is connected to the power supply source Vcc, while its drain is connected to the addressing line for addressing a matrix column (AKS) of the second switches. The source of each MOS-FET transistor 41 is connected to ground and the drain is connected to the addressing line for addressing a matrix row (ARS) of the second switch.

The operation of the branching element 5 and the extraction of the addresses from the address generator 3 will now be described in detail. Under operating conditions, the line 24 is normally high since the first transistor 37 is normally conductive. By high or low is meant that a signal with a high level or a logic value of 1, for example 12 V, or a signal with a low level or a logic value of 0, for example 0 V, is present on a line. In fact, if there is no signal on the line 20, there is also no signal at the input D3 of the second flip-flop 28, so that the output Q3 of the flip-flop 28 is high and the transistor 37 is thus kept conductive via the line 36. The voltage supplied by the power supply source The voltage supplied to Vcc is thus fed to the line 24 via the transistor 37, so that a first control signal is fed to the address generator.

By switching a switch 10, the opto-triac 14 is activated. This results in the signal present on line 24 being fed to the inputs 4', 5' and 6' of the storage element 18 via the diode 17 and the opto-triac 14 and also flowing back to the branching element via line 23. The supply of a signal to the address input 4', 5', 6' of the storage element 18 results in a partial address, namely bits D, E and F of the generated address, being fed to lines 20, 21 and 22 via lines 25-b and diodes 19. Since a signal is now present on line 23, a clock pulse is generated which is fed to the clock input (CLK) of the second flip-flop 28. The clock signal fed to the flip-flop 28 ensures that the partial address (D, E, F) present on the address lines 20, 21 and 22 is now clocked into the second flip-flop 28. The signal present at the outputs of the second flip-flop 28 is not received by the decoders at this level, since the output Q3 of the first flip-flop is still high. The flip-flop 27 has not yet been clocked in.

The switching on of the flip-flop 28 causes the output Q3 of this flip-flop to go low, since a high signal is present at the input D3. Since Q3 now goes low, the signal present on the line 36 also goes low, so that the transistor 37 is blocked. The fact that Q3 goes low also causes this low signal to be fed to point P on the line 34 via the diode 35. The line 34 therefore goes low, which in turn causes a high signal to be fed to the second transistor 39 via the inverter 38, so that this is switched on and thus a second control signal is generated. Since the transistors 37 and 39 are now blocked or conductive, lines 24 and 23 become low or are connected to earth.

The low level on line 24 and the switching of diode 17, as well as the fact that line 23 is connected to ground and the opto-triac is still activated, now lead to a circuit being formed between line 23, diode 16, opto-triac 14 and address lines 1', 2' and 3' of memory element 18. This leads to a partial address ABC being generated under the control of the second control signal and being fed to lines 20, 21 and 22 via lines 25-a and diodes 19. This leads to the second part of the address generated by address generator 3 being transferred to the branching element. Since there is a low level on line 23, the partial address ABC is transmitted in an inverted manner, whereby this has consequences for the switching of the diodes 19-a and the switching at the output of the decoder 31 as well as the level of the MOS-FET 40.

Since line 24 is now low, a clock signal is formed which is made available at a clock input of the first flip-flop 27. This results in the partial address ABC present at the input of the flip-flop 27 being clocked in. The high level present at the input D3 of the flip-flop 27 now causes the output Q3 of the flip-flop 27 to become low, which activates the decoders 31 and 33 and thus causes the partial address ABC or DEF to be transferred at the output of the flip-flop 27 or 28 to the decoders, which then convert it into a matrix address.

The high level at the output Q3 of the flip-flop 27 brings the point P on the line 34 back to a high level, so that via an inverter 38 a signal with a low level on the base of the transistor 39 and thus a blocking of this Since Q3 of flip-flop 27 is high, Q3 is low, causing a reset of flip-flops 27 and 28. This causes Q3 of flip-flop 28 to go high and transistor 37 to conduct, restoring the original situation.

The signals at the outputs of the decoders 31 and 32 have, depending on their level, the effect of making the transistors 40, 41 conductive or non-conductive, thus causing the transmission of the matrix address signal.

By using the branching element 5, on the one hand, the address generated by the address generator 3 is converted into a matrix address and, on the other hand, the possibility is created to transmit a 6-bit address over three connecting lines. The latter aspect is made possible by transmitting the 6-bit address in two partial addresses of 3 bits each. Without this design, the address would be limited to a 4-bit address, so that only 24 possible addresses would be available, whereas now 26 addresses are possible. The use of the line 23 for transmitting a control signal to the address generator instead of using this line as an address line opens up this possibility for address extension. It will be understood that the choice of two partial addresses is only one possible choice and that other possibilities could also be used, so that it would also be possible to choose two lines for 2-bit control signals as well as two address lines, in which way an 8-bit address could be transmitted using the same bus. In general, if there are n predetermined lines in the bus, it is possible to select r lines (2 ≤ r ≤ n) for the transmission of a control signal, while the remaining nr lines are used for the address bus. In this way, 2r-1 control signals can be generated, where for each t-th control signal (1 ≤ t ≤ 2r-1) the t-th part of the address is transmitted. The address transmission capacity is thus extended from an (n-1)-bit address to a [(n-1) + 2r-1]-bit address.

In addition to the possibilities of controlling the elements individually, it is also possible to control them collectively, namely by switching on or off all the connected elements in one and the same operation. The collective switching on or off can be controlled, for example, by the user himself or by a control pulse generator intended for this purpose, which would be controlled, for example, by a timer or an alarm device.

To enable such collective switching on or off, a switching device according to the invention is equipped with a control pulse generator, a sampling element and a comparison element, an example of which is given in Fig. 4 (a + b + c). The control pulse generator 101 further comprises a first and a second switching element 45 and 46 for generating an "all-off" or first control pulse and an "all-on" or second control pulse, respectively. The first and the second switching element are connected to the anode of a diode 48 and a diode 49, respectively, the cathodes of which are connected to an input of an inverter 59 and the anode of a further diode 50. An output of the inverter 59 is connected to a second input of a logic exclusive-OR gate 60, a first input of which is connected to the voltage supply source Vcc. An output of the exclusive OR gate 60 is connected to the first input of a logical AND gate 61, which has a second input 47 to which the inverted signal present on the line 24 is made available. An output of the AND gate 61 is connected to a D input of a third flip-flop 62. A Q output this flip-flop 62 is connected to a reset input (RST) 105 of a counter 58 of the scanning element 103. A reset input of the third flip-flop 62 is connected via an inverter 73 to an output Q7 of the counter 58. The output of the inverter 73 is also connected to a second input of the logical AND gates 86, 87. A first input of the logical AND gate 86 or 87 is supplied with the row or column selection signal which is supplied from the point 83 or 84. The output of the AND gates 86 and 87 is connected to the input G1 or G2 of a multiplexer 85.

A clock input of the counter 58 is connected to an output of a logical AND gate 53, the first input of which is connected to the clock pulse generator 54 and the second input of which is connected to the output of a logical exclusive-OR gate 52, the first input of which and the second input of which are connected to the voltage supply source Vcc and to the output Q7 of the counter 58, respectively. The output of the exclusive-OR gate 52 is further connected to a second input of another exclusive-OR gate 51, the other input of which is connected to a voltage supply source Vcc. An output of the exclusive-OR gate 51 is connected to the cathode of the diode 50. The output of the AND gate 53 is further connected to a second input of a logical AND gate 55, the first input of which is connected to an output of a logical exclusive-OR gate 56 of the comparison element 102. An output of the logical AND gate 55 is connected to the base of a transistor 74, the emitter and collector of which are connected to a line 23 and 24, respectively.

The second switching element 46 is further connected to a D input of a fourth flip-flop 63, from which a Q output with a first input of the exclusive-OR gate 56. The clock input of the fourth flip-flop 63 or the third flip-flop 62 is connected via the inverter 73 to the output Q7 of the counter 58 or to the clock pulse generator 54.

The counter 58 has outputs Q1, Q2, Q3 and Q7 which are connected to the inputs A, B, C and D of a third decoder 65. The outputs Q1, Q2 and Q3 are also connected to the inputs B1, B2 and B3 of the multiplexer 85. The outputs Q4, Q5, Q6 and Q7 of the counter 58 are connected to the inputs A, B, C and D of a fourth decoder 64. The outputs Q4, Q5 and Q6 are also connected to the inputs A1, A2 and A3 of the multiplexer 85. The inputs A4 and B4 of the multiplexer are connected to ground. The outputs Q1 to Q7 of the third and fourth decoders 64 are connected to the respective bases of the transistors 69 and 70. The collectors of the transistors 69 are connected to the power source Vcc and the emitters are fed via the lines 76 of the second row of switches 8 with the column address of the matrix address. The emitters of the transistors 70 are connected to ground while the respective collectors of the same are connected to the cathode of the diodes belonging to a row of optical couplers 71. A signal from the rows of the matrix of the second row of switches 8 is fed to the anodes of the diodes of the optical couplers 71. The collectors of the optical couplers 71 are connected via an inverter 57 to a second input of the exclusive OR gate 56.

The respective outputs of the multiplexer 85 are connected via resistors to the respective bases of the transistors 66, 67 and 68, whose emitters are connected to ground. The collectors of the respective transistors are connected to respective lines 80, 81 and 82, which are further connected to the transmission unit 26 (Fig. 3). The respective lines 81, 81 and 82 correspond to the lines 20, 21 and 22, but carry an inverted corresponding signal. The multiplexer 85 is activated by the signals present at the inputs G1 and G2. Because the logical AND gates 86, 87 are unblocked by the signal present at the output of the inverter 73 (inverted Q7 of the counter 58), the multiplexer 85 is active during the counting operation of the counter 58 and blocked when the counter is not counting. The supply of the row and column selection signals 83, 84 provides control synchronized with the multiplexer 85.

Now assume that a control pulse for the "all on" position is generated by the switching element 46. After completion of a counting cycle, the counter 58 indicates the maximum number, so that the line Q7 at the output of the counter goes high (logic value 1). The high level present at the output Q7 of the counter 58 connected to the exclusive OR gate 52 also ensures that a logic value 0 is present at the output of the exclusive OR gate, so that the AND gate 53 is blocked and the clock signal is not fed to the counter. The logic value 0 at the output of the exclusive OR gate 52 also ensures that the output of the exclusive OR gate 51 provides a logic value 1, which blocks the diode 50, and that a control pulse is provided by the switching element 46 via the diode 49 and the inverter 59 to the exclusive OR gate 60. When the counter is counting and Q7 is therefore low, the exclusive OR gate 51 provides a logic value 0, which turns the diode 50 on and a control pulse originating from the switching element 45 or 46 is not transmitted to the inverter 59. An input control pulse cannot thus disturb the counting of the counter.

The inverter 59 now supplies a logic value 0 to the exclusive OR gate 60, so that the latter supplies a logic value 1. This unblocks the AND gate 61 and supplies a logic value 1 to the input D of the third flip-flop 62, since a logic value 1 is present at the input 47. The Q output 194 of the flip-flop 62 goes high after receiving a clock pulse, so that the counter 58 is reset. This causes the output Q7 of the counter to go low, the flip-flop 62 is reset and the clock signals are also supplied to the counter via the exclusive OR gate 52 and the AND gate 53, so that the latter is able to start its counting cycle.

The control pulse provided by the switching element 46 is applied to the D input of the fourth flip-flop 63, which is clocked by the low level of the output Q7 of the counter 58 (via the inverter 73). Thus, as soon as the output Q7 goes low, the Q output of the flip-flop 63 goes high and remains high as long as the counter 58 has not finished counting, and thus until Q7 goes high. This maintains the control signal provided by the switching element 46 at the first input 108 of the exclusive OR gate 56 throughout the counting cycle.

In the event that an "all off" control pulse is generated by the switching element 45 for the "all on" position, the same thing would happen with regard to the counter 58 and the flip-flop 62 as described above, in fact the switching elements 45 and 46 being connected in parallel to the inverter 59, but a logic value 0 would then be fed to the D input of the fourth flip-flop 63, which would then also be present at the first input of the exclusive OR gate 56. The device thus works in an analogous manner for an "all off" control pulse or an "all on" control pulse.

The counter 58 now supplies successive counts at its outputs Q1 to Q7 under the control of the clock pulses generated by the clock pulse generator 54, the counts representing successive addresses. Accordingly, the counter generates addresses that correspond to those generated by the address generator 3, and these addresses are then also fed via the multiplexer 85 to the lines 80, 81 and 82 of the branching unit and processed in the manner described above. These addresses are now converted into matrix addresses by means of the decoders 64 and 65 in an analogous manner to that described for the decoders 32 and 31.

By counting the counter 58, the addresses are generated in a successive manner so that the matrix elements 8-i,j are successively scanned. A column address supplied to the lines 76 is supplied to the columns 1 (Fig. 5) of the matrix of the second row of switches 8, for example at the mechanically coupled signal contacts which reflect the position of the associated pulse switch. The output of each mechanically coupled signal contact is provided with a diode 77 to prevent interference between the different scanning signals supplied by the counter.

Now assume that one of the switches from the i-th row and the j-th column is closed. Every time a high sampling signal is then transmitted via the switch of the j-th column and the i-th row to the j-th line 76 of the matrix, this sampling signal flows through the diode 77 to the i-th row 72 and is thus present at the anode of the i-th diode 71. When the counter now generates the matrix address i,j, the i-th transistor 70 becomes conductive and the sampling signal present at the anode of the i-th diode 71 flows via the i-th transistor 70 to ground. This activates the i-th optical coupler 71 and a logic value is applied to the input 107 of the inverter 57. 1. This logic value 1 is converted by the inverter 57 into a logic value 0, which is then applied to the exclusive OR gate 56. When the control pulse "all on" has now been generated, a logic value 1 appears at the first input of the logic exclusive OR gate, so that the output of the exclusive OR gate is caused to supply a logic value 1 or a first comparison signal, which is then output via the AND gate 55 under the control of the clock signal and which makes the transistor 74 conductive. Under the control of this first comparison signal, the line 24 becomes active and the switch i,j remains in its position since it was already on. In the event of an "all off" control pulse being generated, the exclusive OR gate 56 generates a second comparison signal and the line 23 becomes active, causing the switch i,j to be reset. The same reasoning applies if an "all off" control pulse has been generated and it has been determined that the switch i,j was not closed, in which circumstances a logic value of 1 at the second input of the exclusive OR gate 56 causes the signal i,j to be toggled and the switch to be closed.

Claims (11)

1. Switching device for switching on and off units (9-p; p = 1,..., z) that can be operated with electrical current, in particular units that can be connected to the power supply network, which has the following: a first row of switches (1-k; k = 1,..., m) which are connected to a branching element (5) which is further connected to first inputs of a second row of switches (8/(i,j)), each of which has a first output to which the units (9-p) can be connected, and a second input to which a power supply, in particular the power supply network, can be connected; and which further has at least one address generator (3-k), so that each address generator is connected to a first input of at least one switch of the first row in order to assign an address to the switch connected to it, the address corresponding to a further address which is assigned to the unit (9-p) which is controlled by the switch; wherein the branching element (5) is connected to a bus (4) which is provided with a predetermined number n of transmission lines (20 to 24) for communication between the one or more address generators (3-k) and the branching element, characterized, that a second input of each switch of the first row is connectable to a low voltage power supply source (Vcc); that the branching element has a control signal generator (37, 39) which is connected to r transmission lines (23 to 24) (2 ≤ r ≤ n) from the n transmission lines; that the one or more address generators (3-k) is provided with a control input which is connected to the r transmission lines (23 to 24) in order to receive control signals generated by the control signal generator (37, 39); and that the one or more address generators (3-k) have an output connected to the branching element (5) via the remaining n-r transmission lines for transmitting to the branching element a t-th partial address (1 ≤ t ≤ 2r-1) under the control of a respective t-th control signal, each t-th partial address forming a corresponding t-th part of the address generated by the address generator that received the control signal. 2. Switching device according to claim 1, characterized in that the number r of transmission lines is equal to two. 3. Switching device according to claim 1 or 2, characterized in that that the second row of switches is arranged according to a matrix and that each switch of the second row is associated with a matrix address which indicates a row and a column of the matrix, the branching element being provided to convert a received address into a corresponding matrix address. 4. Switching device according to claim 3, characterized in that the matrix address consists of a column address and a row address and that the branching element is provided with a first or a second decoder to carry out the conversion into the column or row address. 5. Switching device according to one of claims 1, 2, 3 or 4, characterized in that the address generator has a memory element. 6. Switching device according to claim 5, characterized in that the memory element comprises a programmable memory. 7. Switching device according to one of claims 1 to 6, characterized in that that the switching device further comprises: a control pulse generator (101), a comparison element (102) and a scanning element (103); wherein the control pulse generator (101) is provided to generate and provide first and second control pulses at a control signal output (104) in order to switch all connected units (9-p) to a first position and a second position, respectively, wherein the control signal output (104) is connected to a control signal input (105) of the scanning element; wherein the sampling element (103) has an output (76) connected to the address input (CKj, CRi) of the second switches (8/(i,j)), wherein the sampling element is arranged to generate, under the control of a received control pulse, a series of sampling signals to sequentially sample each of the second switches and to generate each time a sampling pulse representing an actual position of a sampled switch, wherein the sampling element (103) is connected to a sampling signal input of the comparison element (102); and wherein the comparison element (102) has a first input (107) connected to the second switches (8/(i,j)) and a control signal input (108) to receive the first and second control pulses, wherein the comparison element (102) is provided to compare the sampling pulse with the control pulse present at the control signal input (108) and to generate first and second respective comparison signals indicating a correspondence and a non-correspondence of the compared pulses, respectively, wherein the comparison element (102) activates the branching element with the second comparison signal to switch the sampled second switch. 8. Switching device according to claim 7, characterized in that the sampling element has a counter to generate as a sampling signal successive addresses which are associated with the first switch. 9. Switching device according to claim 8, characterized in that the comparison element has an exclusive OR gate, of which a first gate input is connected to the control signal input and a second gate input is provided to receive the sampling pulse. 10. Switching device according to one of claims 7, 8 or 9, characterized in that the control pulse generator has a switching unit. 11. Switching device according to one of claims 7, 8 or 9, characterized in that the control pulse generator has an alarm detector.