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DE69031367D1 - Blockübertragungs- und Koprozessorschnittstellenbefehl - Google Patents

Blockübertragungs- und Koprozessorschnittstellenbefehl

Info

Publication number
DE69031367D1
DE69031367D1 DE69031367T DE69031367T DE69031367D1 DE 69031367 D1 DE69031367 D1 DE 69031367D1 DE 69031367 T DE69031367 T DE 69031367T DE 69031367 T DE69031367 T DE 69031367T DE 69031367 D1 DE69031367 D1 DE 69031367D1
Authority
DE
Germany
Prior art keywords
block transfer
interface command
coprocessor interface
coprocessor
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031367T
Other languages
English (en)
Other versions
DE69031367T2 (de
Inventor
Robin W Edenfield
Ralph Mcgarity
Russell Reininger
William B Ledbetter
Austin Van Shahan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69031367D1 publication Critical patent/DE69031367D1/de
Publication of DE69031367T2 publication Critical patent/DE69031367T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Executing Machine-Instructions (AREA)
DE69031367T 1989-06-26 1990-06-25 Blockübertragungs- und Koprozessorschnittstellenbefehl Expired - Lifetime DE69031367T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/371,343 US5185694A (en) 1989-06-26 1989-06-26 Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies

Publications (2)

Publication Number Publication Date
DE69031367D1 true DE69031367D1 (de) 1997-10-09
DE69031367T2 DE69031367T2 (de) 1998-03-19

Family

ID=23463581

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031367T Expired - Lifetime DE69031367T2 (de) 1989-06-26 1990-06-25 Blockübertragungs- und Koprozessorschnittstellenbefehl

Country Status (6)

Country Link
US (1) US5185694A (de)
EP (1) EP0405882B1 (de)
JP (1) JP3431626B2 (de)
KR (1) KR0154533B1 (de)
DE (1) DE69031367T2 (de)
HK (1) HK1002438A1 (de)

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US5953513A (en) * 1992-07-09 1999-09-14 Hitachi, Ltd. Recording and reproducing device for recording and reproducing information from different kinds of storage media having different sector formats
CA2135681C (en) * 1993-12-30 2000-01-18 Srinivas V. Makam System and method for directly accessing long-term memory devices
JP3529429B2 (ja) * 1994-06-10 2004-05-24 富士通株式会社 データ送信装置、データ受信装置、データ伝送装置及びデータ伝送方法
DE69629331T2 (de) * 1995-06-02 2004-02-12 Sun Microsystems, Inc., Mountain View System und Verfahren zur Bereitstellung einer flexiblen Speicherhierarchie
JP3513291B2 (ja) * 1995-12-14 2004-03-31 富士通株式会社 データ転送装置
US5911151A (en) * 1996-04-10 1999-06-08 Motorola, Inc. Optimizing block-sized operand movement utilizing standard instructions
US5835972A (en) * 1996-05-28 1998-11-10 Advanced Micro Devices, Inc. Method and apparatus for optimization of data writes
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
US5933855A (en) * 1997-03-21 1999-08-03 Rubinstein; Richard Shared, reconfigurable memory architectures for digital signal processing
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6414687B1 (en) 1997-04-30 2002-07-02 Canon Kabushiki Kaisha Register setting-micro programming system
US6259456B1 (en) 1997-04-30 2001-07-10 Canon Kabushiki Kaisha Data normalization techniques
AUPO647997A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6289138B1 (en) 1997-04-30 2001-09-11 Canon Kabushiki Kaisha General image processor
US6272257B1 (en) 1997-04-30 2001-08-07 Canon Kabushiki Kaisha Decoder of variable length codes
US6006303A (en) * 1997-08-28 1999-12-21 Oki Electric Industry Co., Inc. Priority encoding and decoding for memory architecture
US6108723A (en) * 1998-07-20 2000-08-22 Hewlett-Packard Company System for implementing hardware automated control of burst mode data transfer over a communication link between devices operating in a block mode
US6449711B1 (en) 1999-02-04 2002-09-10 Sun Microsystems, Inc. Method, apparatus, and article of manufacture for developing and executing data flow programs
JP2001035153A (ja) * 1999-07-23 2001-02-09 Fujitsu Ltd 半導体記憶装置
US6665749B1 (en) * 1999-08-17 2003-12-16 Nec Electronics, Inc. Bus protocol for efficiently transferring vector data
DE19948100A1 (de) * 1999-10-06 2001-04-12 Infineon Technologies Ag Prozessorsystem
US6751675B1 (en) 1999-11-15 2004-06-15 Sun Microsystems, Inc. Moving set packet processor suitable for resource-constrained devices
US7343451B2 (en) * 2003-12-25 2008-03-11 Hitachi, Ltd. Disk array device and remote copying control method for disk array device
JP2005190057A (ja) * 2003-12-25 2005-07-14 Hitachi Ltd ディスクアレイ装置及びディスクアレイ装置のリモートコピー制御方法
US7522168B2 (en) * 2005-09-27 2009-04-21 Sony Computer Entertainment Inc. Cell processor task and data management
US8037474B2 (en) * 2005-09-27 2011-10-11 Sony Computer Entertainment Inc. Task manager with stored task definition having pointer to a memory address containing required code data related to the task for execution
US8316220B2 (en) * 2005-09-27 2012-11-20 Sony Computer Entertainment Inc. Operating processors over a network
US7734827B2 (en) * 2005-09-27 2010-06-08 Sony Computer Entertainment, Inc. Operation of cell processors
US7506123B1 (en) * 2005-09-27 2009-03-17 Sony Computer Entertainment Inc. Method and system for performing memory copy function on a cell processor
US8141076B2 (en) * 2005-09-27 2012-03-20 Sony Computer Entertainment Inc. Cell processor methods and apparatus
US7975269B2 (en) * 2005-09-27 2011-07-05 Sony Computer Entertainment Inc. Parallel processor methods and apparatus
US8085275B1 (en) * 2005-12-20 2011-12-27 Nvidia Corporation System and method for low-overhead push buffer jumps
US8595747B2 (en) * 2005-12-29 2013-11-26 Sony Computer Entertainment Inc. Efficient task scheduling by assigning fixed registers to scheduler
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8543796B2 (en) * 2008-11-05 2013-09-24 Intel Corporation Optimizing performance of instructions based on sequence detection or information associated with the instructions
US9218183B2 (en) * 2009-01-30 2015-12-22 Arm Finance Overseas Limited System and method for improving memory transfer
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache
US10210114B2 (en) 2014-08-01 2019-02-19 Universiti Teknologi Malaysia Interrupt-driven I/O arbiter for a microcomputer system
DE102014111302B4 (de) * 2014-08-07 2023-09-14 Mikro Pahlawan Unterbrechungsgesteuerter Ein-/Ausgabe-Arbiter für ein Mikrocomputersystem
US9575913B1 (en) * 2015-12-07 2017-02-21 International Business Machines Corporation Techniques for addressing topology specific replicated bus units

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JPS5621240A (en) * 1979-07-27 1981-02-27 Hitachi Ltd Information processor
US4533995A (en) * 1981-08-03 1985-08-06 International Business Machines Corporation Method and system for handling sequential data in a hierarchical store
US4564899A (en) * 1982-09-28 1986-01-14 Elxsi I/O Channel bus
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
US4958351A (en) * 1986-02-03 1990-09-18 Unisys Corp. High capacity multiple-disk storage method and apparatus having unusually high fault tolerance level and high bandpass
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor
US4910656A (en) * 1987-09-21 1990-03-20 Motorola, Inc. Bus master having selective burst initiation
US4912631A (en) * 1987-12-16 1990-03-27 Intel Corporation Burst mode cache with wrap-around fill
US4926323A (en) * 1988-03-03 1990-05-15 Advanced Micro Devices, Inc. Streamlined instruction processor
EP0375883A3 (de) * 1988-12-30 1991-05-29 International Business Machines Corporation Cache-Speicheranordnung

Also Published As

Publication number Publication date
US5185694A (en) 1993-02-09
EP0405882A3 (en) 1993-04-21
DE69031367T2 (de) 1998-03-19
EP0405882A2 (de) 1991-01-02
KR910001555A (ko) 1991-01-31
JPH0337744A (ja) 1991-02-19
KR0154533B1 (ko) 1998-11-16
EP0405882B1 (de) 1997-09-03
HK1002438A1 (en) 1998-08-21
JP3431626B2 (ja) 2003-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US