[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

DE69916993T2 - Datenübertragung in quellen-synchronen und normaluhr-protokollen - Google Patents

Datenübertragung in quellen-synchronen und normaluhr-protokollen Download PDF

Info

Publication number
DE69916993T2
DE69916993T2 DE69916993T DE69916993T DE69916993T2 DE 69916993 T2 DE69916993 T2 DE 69916993T2 DE 69916993 T DE69916993 T DE 69916993T DE 69916993 T DE69916993 T DE 69916993T DE 69916993 T2 DE69916993 T2 DE 69916993T2
Authority
DE
Germany
Prior art keywords
synchrones
source
data transfer
normal clock
clock protocols
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69916993T
Other languages
English (en)
Other versions
DE69916993D1 (de
Inventor
D Macwilliams
S Wu
K Sampath
A Prasad
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE69916993D1 publication Critical patent/DE69916993D1/de
Application granted granted Critical
Publication of DE69916993T2 publication Critical patent/DE69916993T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4009Coupling between buses with data restructuring
    • G06F13/4018Coupling between buses with data restructuring with data-width conversion
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/405Coupling between buses using bus bridges where the bridge performs a synchronising function

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
DE69916993T 1998-01-13 1999-01-05 Datenübertragung in quellen-synchronen und normaluhr-protokollen Expired - Lifetime DE69916993T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/006,322 US6336159B1 (en) 1997-06-25 1998-01-13 Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
PCT/US1999/000199 WO1999036858A1 (en) 1998-01-13 1999-01-05 Data transferring in source-synchronous and common clock protocols

Publications (2)

Publication Number Publication Date
DE69916993D1 DE69916993D1 (de) 2004-06-09
DE69916993T2 true DE69916993T2 (de) 2005-04-21

Family

ID=21720327

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69916993T Expired - Lifetime DE69916993T2 (de) 1998-01-13 1999-01-05 Datenübertragung in quellen-synchronen und normaluhr-protokollen

Country Status (7)

Country Link
US (2) US6336159B1 (de)
EP (1) EP1046111B1 (de)
JP (1) JP4598270B2 (de)
CN (1) CN1199117C (de)
AU (1) AU2026999A (de)
DE (1) DE69916993T2 (de)
WO (1) WO1999036858A1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336159B1 (en) * 1997-06-25 2002-01-01 Intel Corporation Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
US7581077B2 (en) 1997-10-30 2009-08-25 Commvault Systems, Inc. Method and system for transferring data in a storage operation
US6418478B1 (en) * 1997-10-30 2002-07-09 Commvault Systems, Inc. Pipelined high speed data transfer mechanism
JP3592547B2 (ja) * 1998-09-04 2004-11-24 株式会社ルネサステクノロジ 情報処理装置および信号転送方法
US6665807B1 (en) 1998-09-04 2003-12-16 Hitachi, Ltd. Information processing apparatus
KR100447051B1 (ko) * 1999-05-31 2004-09-04 미쓰비시덴키 가부시키가이샤 데이터 전송방식
DE19960859A1 (de) * 1999-12-16 2001-07-05 Trw Automotive Electron & Comp Entkopplungseinheit für Bussysteme
US6609171B1 (en) 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
US6757763B1 (en) * 2000-04-07 2004-06-29 Infineon Technologies North America Corpration Universal serial bus interfacing using FIFO buffers
US6965648B1 (en) * 2000-05-04 2005-11-15 Sun Microsystems, Inc. Source synchronous link integrity validation
US6678767B1 (en) * 2000-10-06 2004-01-13 Broadcom Corp Bus sampling on one edge of a clock signal and driving on another edge
US6715094B2 (en) * 2000-12-20 2004-03-30 Intel Corporation Mult-mode I/O interface for synchronizing selected control patterns into control clock domain to obtain interface control signals to be transmitted to I/O buffers
US6742160B2 (en) 2001-02-14 2004-05-25 Intel Corporation Checkerboard parity techniques for a multi-pumped bus
US6711652B2 (en) * 2001-06-21 2004-03-23 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data
US7006527B1 (en) * 2001-10-12 2006-02-28 Cypress Semiconductor Corp. Multistage pipeline bit conversion
US7085889B2 (en) 2002-03-22 2006-08-01 Intel Corporation Use of a context identifier in a cache memory
US7139308B2 (en) * 2002-04-05 2006-11-21 Sun Microsystems, Inc. Source synchronous bus repeater
US20030217301A1 (en) * 2002-05-16 2003-11-20 Levy Paul S. Method and apparatus for transmitting side-band data within a source synchronous clock signal
TWI282513B (en) * 2002-06-12 2007-06-11 Mediatek Inc A pre-fetch device of instruction for an embedded system
KR100437454B1 (ko) * 2002-07-30 2004-06-23 삼성전자주식회사 소오스 싱크로너스 전송 방식을 이용한 비동기 메모리 및그것을 포함한 시스템
CA2499073C (en) 2002-09-16 2013-07-23 Commvault Systems, Inc. Combined stream auxiliary copy system and method
US7280589B2 (en) * 2003-07-24 2007-10-09 Sun Microsystems, Inc. Source synchronous I/O bus retimer
WO2005065084A2 (en) * 2003-11-13 2005-07-21 Commvault Systems, Inc. System and method for providing encryption in pipelined storage operations in a storage network
US7543094B2 (en) * 2005-07-05 2009-06-02 Via Technologies, Inc. Target readiness protocol for contiguous write
US7386750B2 (en) * 2005-07-15 2008-06-10 Hewlett-Packard Development Company, L.P. Reduced bus turnaround time in a multiprocessor architecture
JP4570532B2 (ja) * 2005-08-02 2010-10-27 パナソニック株式会社 動き検出装置、動き検出方法、集積回路およびプログラム
US7444448B2 (en) * 2005-08-03 2008-10-28 Via Technologies, Inc. Data bus mechanism for dynamic source synchronized sampling adjust
US7856571B2 (en) * 2007-01-22 2010-12-21 Hewlett-Packard Development Company, L.P. Method and system for communication employing dual slew rates
US7924142B2 (en) 2008-06-30 2011-04-12 Kimberly-Clark Worldwide, Inc. Patterned self-warming wipe substrates
EP2341445B1 (de) * 2009-12-30 2017-09-06 Intel Deutschland GmbH Verfahren zur Hochgeschwindigkeits-Datenübertragung
JP5423483B2 (ja) * 2010-03-04 2014-02-19 株式会社リコー データ転送制御装置
JP5573476B2 (ja) * 2010-08-09 2014-08-20 日本電気株式会社 被制御装置、被制御方法、制御装置、及び、制御システム
US9087163B2 (en) * 2012-07-11 2015-07-21 Silicon Image, Inc. Transmission of multiple protocol data elements via an interface utilizing a data tunnel
CN104375965B (zh) * 2013-08-15 2017-09-15 竣阳国际开发股份有限公司 多工具机操作系统
TWI509418B (zh) * 2014-06-30 2015-11-21 Chant Sincere Co Ltd 資料轉換系統與及其控制方法
US9898213B2 (en) 2015-01-23 2018-02-20 Commvault Systems, Inc. Scalable auxiliary copy processing using media agent resources
US9904481B2 (en) 2015-01-23 2018-02-27 Commvault Systems, Inc. Scalable auxiliary copy processing in a storage management system using media agent resources
US11010261B2 (en) 2017-03-31 2021-05-18 Commvault Systems, Inc. Dynamically allocating streams during restoration of data
US10908820B2 (en) 2017-09-14 2021-02-02 Samsung Electronics Co., Ltd. Host-based and client-based command scheduling in large bandwidth memory systems
CN110389919B (zh) * 2019-07-04 2021-03-19 苏州浪潮智能科技有限公司 基于risc-v处理器的异步收发传输器外设及系统
CN111708312B (zh) * 2020-04-28 2021-11-09 北京骥远自动化技术有限公司 一种高可靠数据传输plc系统及其数据传输方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4353128A (en) 1980-06-19 1982-10-05 Bell Telephone Laboratories, Incorporated Synchronous/asynchronous data communication arrangement
DE3213345C2 (de) * 1982-04-08 1984-11-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Datenübertragungseinrichtung zwischen zwei asynchron gesteuerten Datenverarbeitungssystemen
EP0262413B1 (de) * 1986-09-04 1992-07-22 Fujitsu Limited Speichereinrichtung unter Verwendung von Adressenmultiplex
US4908823A (en) 1988-01-29 1990-03-13 Hewlett-Packard Company Hybrid communications link adapter incorporating input/output and data communications technology
US5842029A (en) * 1991-10-17 1998-11-24 Intel Corporation Method and apparatus for powering down an integrated circuit transparently and its phase locked loop
US5640599A (en) * 1991-12-30 1997-06-17 Apple Computer, Inc. Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed
US5325516A (en) * 1992-03-09 1994-06-28 Chips And Technologies Inc. Processor system with dual clock
US5280587A (en) * 1992-03-31 1994-01-18 Vlsi Technology, Inc. Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value
US5359232A (en) * 1992-05-08 1994-10-25 Cyrix Corporation Clock multiplication circuit and method
JP3608804B2 (ja) * 1993-05-14 2005-01-12 株式会社ソニー・コンピュータエンタテインメント バス制御装置
JPH0844665A (ja) 1994-07-14 1996-02-16 Fujitsu Ltd 複数のデータ転送サイズ及びプロトコルをサポートするバス
TW358907B (en) * 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
US5754825A (en) 1995-05-19 1998-05-19 Compaq Computer Corporation Lower address line prediction and substitution
KR0164395B1 (ko) * 1995-09-11 1999-02-18 김광호 반도체 메모리 장치와 그 리이드 및 라이트 방법
US5727171A (en) * 1995-11-16 1998-03-10 International Business Machines Corporation Method and apparatus for allowing multi-speed synchronous communications between a processor and both slow and fast computing devices
US5893135A (en) * 1995-12-27 1999-04-06 Intel Corporation Flash memory array with two interfaces for responding to RAS and CAS signals
US5826067A (en) * 1996-09-06 1998-10-20 Intel Corporation Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US5802356A (en) 1996-11-13 1998-09-01 Integrated Device Technology, Inc. Configurable drive clock
US5809291A (en) * 1997-02-19 1998-09-15 International Business Machines Corp. Interoperable 33 MHz and 66 MHz devices on the same PCI bus
US5901304A (en) * 1997-03-13 1999-05-04 International Business Machines Corporation Emulating quasi-synchronous DRAM with asynchronous DRAM
US6336159B1 (en) * 1997-06-25 2002-01-01 Intel Corporation Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
US5919254A (en) * 1997-06-25 1999-07-06 Intel Corporation Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
US5905391A (en) * 1997-07-14 1999-05-18 Intel Corporation Master-slave delay locked loop for accurate delay or non-periodic signals
US5978869A (en) * 1997-07-21 1999-11-02 International Business Machines Corporation Enhanced dual speed bus computer system
US6108736A (en) * 1997-09-22 2000-08-22 Intel Corporation System and method of flow control for a high speed bus
US5964856A (en) * 1997-09-30 1999-10-12 Intel Corporation Mechanism for data strobe pre-driving during master changeover on a parallel bus
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
KR100255664B1 (ko) * 1997-12-29 2000-05-01 윤종용 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법

Also Published As

Publication number Publication date
AU2026999A (en) 1999-08-02
CN1288544A (zh) 2001-03-21
EP1046111A1 (de) 2000-10-25
EP1046111B1 (de) 2004-05-06
JP2002509315A (ja) 2002-03-26
US20020065967A1 (en) 2002-05-30
DE69916993D1 (de) 2004-06-09
US6336159B1 (en) 2002-01-01
EP1046111A4 (de) 2002-01-23
WO1999036858A1 (en) 1999-07-22
CN1199117C (zh) 2005-04-27
US6598103B2 (en) 2003-07-22
JP4598270B2 (ja) 2010-12-15

Similar Documents

Publication Publication Date Title
DE69916993T2 (de) Datenübertragung in quellen-synchronen und normaluhr-protokollen
DE69806740D1 (de) Datenübertragungssystem und bestandteile dafür
DE50003998D1 (de) Datenübertragungsvorrichtung und -verfahren
DE60139632D1 (de) Übertragen und empfangen von echtzeitdaten
NO20011216D0 (no) Azetidinderivater, fremstilling og medisiner inneholdende disse
GB2356279B (en) Data transfer devices and methods
DK1454907T3 (da) Quninazolin og pyridopyrmidin-derivativer
DE69816599D1 (de) Datenübertragungssteuerung und verteilte datenverarbeitung
DE69518199D1 (de) Sicheres Datenübertragungsverfahren
DE69915421D1 (de) Informationsverarbeitungsgerät und Peripheriegerät
DE69834391D1 (de) Datentransferverfahren
DE69932022D1 (de) Datenübertragungssteuerverfahren und dazu verwendete Gerät
DE69927643D1 (de) Informationsverarbeitung und Datenspeicherung
DE60017613D1 (de) Speicher und Datenverarbeitungseinheiten und Datenverarbeitungsverfahren
DE60217260D1 (de) Datenverarbeitungs- und -verschlüsselungs-Einheit
DE69935065D1 (de) Datenübertragungssteuerinrichtung und elektronisches gerät
DE60045699D1 (de) Daten-beschreibungs-verfahren und daten-bearbeitung-vorrichtung
NO20003916D0 (no) Benzotiadiazoler og derivater
DE69938991D1 (de) Datenverarbeitung
DK1068238T3 (da) Integrinheterodimer og subunit deraf
DE69928050D1 (de) Taktregenerator
DE60007919D1 (de) Datendekodiergerät und Datendekodierverfahren
DE60031928D1 (de) Eingabeeinrichtung und Informationsverarbeitungsvorrichtung
DE69942324D1 (de) Datenübertragungsgerät und Datenempfangsgerät
FI980316A (fi) Tiedonsiirtomenetelmä

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806