DE69833715D1 - Taktrückgewinnungsschaltung - Google Patents

Taktrückgewinnungsschaltung

Info

Publication number: DE69833715D1
Authority: DE; Germany
Prior art keywords: recovery circuit; clock recovery; clock; circuit; recovery
Prior art date: 1997-09-18
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69833715T

Other languages

English (en)

Other versions

DE69833715T2 (de

Inventor

Takanori Saeki

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Renesas Electronics Corp

Original Assignee

NEC Electronics Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1997-09-18

Filing date

1998-09-18

Publication date

2006-05-04

1998-09-18 Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp

2006-05-04 Application granted granted Critical

2006-05-04 Publication of DE69833715D1 publication Critical patent/DE69833715D1/de

2006-11-23 Publication of DE69833715T2 publication Critical patent/DE69833715T2/de

2018-09-19 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Landscapes

Engineering & Computer Science (AREA)
Computer Networks & Wireless Communication (AREA)
Signal Processing (AREA)
Physics & Mathematics (AREA)
Nonlinear Science (AREA)
Synchronisation In Digital Transmission Systems (AREA)
Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Dram (AREA)

DE69833715T 1997-09-18 1998-09-18 Taktrückgewinnungsschaltung Expired - Lifetime DE69833715T2 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP25320097A JP3019814B2 (ja)	1997-09-18	1997-09-18	クロックリカバリ回路
JP25320097		1997-09-18

Publications (2)

Publication Number	Publication Date
DE69833715D1 true DE69833715D1 (de)	2006-05-04
DE69833715T2 DE69833715T2 (de)	2006-11-23

Family

ID=17247953

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69833715T Expired - Lifetime DE69833715T2 (de)	1997-09-18	1998-09-18	Taktrückgewinnungsschaltung

Country Status (7)

Country	Link
US (1)	US6275547B1 (de)
EP (1)	EP0903885B1 (de)
JP (1)	JP3019814B2 (de)
KR (1)	KR100295121B1 (de)
CN (1)	CN1089504C (de)
DE (1)	DE69833715T2 (de)
TW (1)	TW437154B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE69939291D1 (de) *	1998-04-28	2008-09-25	Matsushita Electric Ind Co Ltd	Eingangsschaltung
US6985547B2 (en)	1999-09-27	2006-01-10	The Board Of Governors For Higher Education, State Of Rhode Island And Providence Plantations	System and method of digital system performance enhancement
US6760392B1 (en) *	1999-11-12	2004-07-06	Advanced Micro Devices, Inc.	Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios
US7187721B1 (en) *	2000-02-09	2007-03-06	Rambus Inc.	Transition-time control in a high-speed data transmitter
JP3386031B2 (ja) *	2000-03-06	2003-03-10	日本電気株式会社	同期遅延回路及び半導体集積回路装置
US6895188B1 (en) *	2000-04-10	2005-05-17	Sprint Communications Company L.P.	Optical signal reshaping to mitigate polarization mode dispersion
US7233637B2 (en) *	2000-04-17	2007-06-19	Adaptive Networks, Inc.	Wideband communication using delay line clock multiplier
WO2001091297A2 (en) *	2000-05-24	2001-11-29	Bogdan John W	High resolution phase frequency detectors
US6748027B1 (en) *	2000-08-10	2004-06-08	Intel Corporation	CMI signal timing recovery
US6748039B1 (en) *	2000-08-11	2004-06-08	Advanced Micro Devices, Inc.	System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system
US6904537B1 (en)	2001-08-27	2005-06-07	Network Elements, Inc.	Data transmission across asynchronous time domains using phase-shifted data packet
CN1295902C (zh) *	2003-07-08	2007-01-17	上海大学	高速突发式时钟和数据恢复器
US7091764B2 (en) *	2004-11-05	2006-08-15	Infineon Technologies Ag	Duty distortion detector
US7102403B2 (en)	2005-02-03	2006-09-05	Mediatek Incorporation	Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof
KR100734263B1 (ko)	2005-06-14	2007-07-02	삼성전자주식회사	동기화회로
JP5397025B2 (ja) *	2009-06-02	2014-01-22	ソニー株式会社	クロック再生装置および電子機器
CN101800062A (zh) *	2010-04-02	2010-08-11	福州思迈特数码科技有限公司	实现音频升频的车载dvd导航影音装置
US8922150B1 (en) *	2012-07-18	2014-12-30	The Johns Hopkins University	Differential serial driver
KR102151184B1 (ko) *	2013-07-24	2020-09-02	삼성전자주식회사	클록 데이터 복원 회로 및 이를 포함하는 타이밍 컨트롤러 그리고 이의 구동 방법
KR102378768B1 (ko) *	2018-08-21	2022-03-29	한국전자통신연구원	클럭의 위상을 조정하기 위한 전자 회로
KR102635773B1 (ko) *	2018-09-13	2024-02-08	삼성전자주식회사	저장 장치
US10991426B2 (en) *	2019-01-25	2021-04-27	Taiwan Semiconductor Manufacturing Company, Ltd.	Memory device current limiter
DE102019132067A1 (de)	2019-01-25	2020-07-30	Taiwan Semiconductor Manufacturing Co., Ltd.	Strombegrenzer für speichervorrichtung
CN115051700A (zh) *	2021-03-09	2022-09-13	长鑫存储技术(上海)有限公司	交错信号产生电路
CN113746427B (zh) *	2021-11-05	2022-02-11	深圳飞骧科技股份有限公司	一种rc振荡电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4795988A (en) *	1986-11-18	1989-01-03	Britz William J	Low distortion oscillator
US4975929A (en) *	1989-09-11	1990-12-04	Raynet Corp.	Clock recovery apparatus
US5237290A (en) *	1992-05-08	1993-08-17	At&T Bell Laboratories	Method and apparatus for clock recovery
US5592519A (en) *	1994-06-22	1997-01-07	Alcatel Network Systems, Inc.	Dual frequency clock recovery using common multitap line
DE19534693A1 (de) *	1995-09-19	1997-03-20	Phoenix Contact Gmbh & Co	Schaltungsanordnung zur Teilnehmersynchronisation bei asynchroner bitserieller Datenübertragung

1997
- 1997-09-18 JP JP25320097A patent/JP3019814B2/ja not_active Expired - Fee Related
1998
- 1998-09-14 TW TW087115272A patent/TW437154B/zh not_active IP Right Cessation
- 1998-09-16 US US09/154,037 patent/US6275547B1/en not_active Expired - Lifetime
- 1998-09-17 KR KR1019980038455A patent/KR100295121B1/ko not_active IP Right Cessation
- 1998-09-18 CN CN98120012A patent/CN1089504C/zh not_active Expired - Fee Related
- 1998-09-18 EP EP98117775A patent/EP0903885B1/de not_active Expired - Lifetime
- 1998-09-18 DE DE69833715T patent/DE69833715T2/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
KR100295121B1 (ko)	2001-07-12
CN1089504C (zh)	2002-08-21
TW437154B (en)	2001-05-28
DE69833715T2 (de)	2006-11-23
EP0903885A3 (de)	2003-05-28
EP0903885A2 (de)	1999-03-24
JP3019814B2 (ja)	2000-03-13
CN1211853A (zh)	1999-03-24
KR19990029900A (ko)	1999-04-26
JPH1198132A (ja)	1999-04-09
EP0903885B1 (de)	2006-03-08
US6275547B1 (en)	2001-08-14

Publication	Publication Date	Title
DE69833715D1 (de)	2006-05-04	Taktrückgewinnungsschaltung
DE69535087D1 (de)	2006-08-10	Schaltungsanordnung zur Taktrückgewinnung
DE69729908D1 (de)	2004-08-26	Taktsteuerungsschaltung
DE69816023D1 (de)	2003-08-07	Schaltungsanordnung
DE69836434D1 (de)	2006-12-28	Deaktivierbarer schwingkreis
DE69737171D1 (de)	2007-02-15	Schaltung zur Taktrückgewinnung
DE69709621D1 (de)	2002-02-21	Oszillatorschaltung
DE69829769D1 (de)	2005-05-19	Zeitmessschaltung
BR9706700A (pt)	1999-07-20	Relógio eletrônico combinado
DE69824816D1 (de)	2004-08-05	Fahrrad-Schaltung
DE69839396D1 (de)	2008-06-05	Schaltung zur taktwiederherstellung
DE69830541D1 (de)	2005-07-21	Taktgewinnungsschaltung
DE69839322D1 (de)	2008-05-15	Schnittstellenschaltung
DE69928050D1 (de)	2005-12-08	Taktregenerator
DE69816950D1 (de)	2003-09-11	Schaltungsanordnung
DE69835190D1 (de)	2006-08-24	Schaltung zur Taktrückgewinnung
DE69509267D1 (de)	1999-06-02	Taktschaltung
DE69831460D1 (de)	2005-10-13	Schaltungsentwurfprüfung
DE69828146D1 (de)	2005-01-20	Schaltungsanordnung
DK1020031T3 (da)	2004-01-26	Integreret kredsløb
FR2777096B3 (fr)	2000-01-21	Horloge
DE69928171D1 (de)	2005-12-15	Elektronisches Uhrwerk
DE69820925D1 (de)	2004-02-12	Takteingangsschaltung
DE69812952T2 (de)	2004-01-29	Zeitgeberschaltung
DE69734836D1 (de)	2006-01-12	Projektionsuhr

Legal Events

Date	Code	Title	Description
2007-03-29	8364	No opposition during term of opposition
2012-08-28	R082	Change of representative	Ref document number: 903885 Country of ref document: EP Representative=s name: BETTEN & RESCH, DE
2012-10-18	R081	Change of applicant/patentee	Ref document number: 903885 Country of ref document: EP Owner name: RENESAS ELECTRONICS CORPORATION, JP Free format text: FORMER OWNER: NEC ELECTRONICS CORP., KAWASAKI, JP Effective date: 20120828
2012-10-18	R082	Change of representative	Ref document number: 903885 Country of ref document: EP Representative=s name: PATENTANWAELTE BETTEN & RESCH, DE Effective date: 20120828