DE69830089D1 - Mehrpegelspeicher - Google Patents
MehrpegelspeicherInfo
- Publication number
- DE69830089D1 DE69830089D1 DE69830089T DE69830089T DE69830089D1 DE 69830089 D1 DE69830089 D1 DE 69830089D1 DE 69830089 T DE69830089 T DE 69830089T DE 69830089 T DE69830089 T DE 69830089T DE 69830089 D1 DE69830089 D1 DE 69830089D1
- Authority
- DE
- Germany
- Prior art keywords
- multilevel memory
- multilevel
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01834997A JP3409986B2 (ja) | 1997-01-31 | 1997-01-31 | 多値メモリ |
| JP1834997 | 1997-01-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69830089D1 true DE69830089D1 (de) | 2005-06-16 |
| DE69830089T2 DE69830089T2 (de) | 2006-01-19 |
Family
ID=11969205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69830089T Expired - Lifetime DE69830089T2 (de) | 1997-01-31 | 1998-01-30 | Mehrpegelspeicher |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6028792A (de) |
| EP (2) | EP1564752A1 (de) |
| JP (1) | JP3409986B2 (de) |
| KR (1) | KR100272035B1 (de) |
| CN (1) | CN1204561C (de) |
| DE (1) | DE69830089T2 (de) |
| TW (1) | TW379450B (de) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3481817B2 (ja) * | 1997-04-07 | 2003-12-22 | 株式会社東芝 | 半導体記憶装置 |
| DE69831155D1 (de) | 1998-10-29 | 2005-09-15 | St Microelectronics Srl | Verfahren und Vorrichtung zur Prüfung von nichtprogrammierten Speicherzellen in einem Mehrpegelspeicher |
| USRE40110E1 (en) | 1999-09-20 | 2008-02-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device for storing multivalued data |
| US6219276B1 (en) | 2000-02-25 | 2001-04-17 | Advanced Micro Devices, Inc. | Multilevel cell programming |
| US6297988B1 (en) | 2000-02-25 | 2001-10-02 | Advanced Micro Devices, Inc. | Mode indicator for multi-level memory |
| US6424569B1 (en) | 2000-02-25 | 2002-07-23 | Advanced Micro Devices, Inc. | User selectable cell programming |
| US6205055B1 (en) | 2000-02-25 | 2001-03-20 | Advanced Micro Devices, Inc. | Dynamic memory cell programming voltage |
| US6707713B1 (en) | 2000-03-01 | 2004-03-16 | Advanced Micro Devices, Inc. | Interlaced multi-level memory |
| US6331951B1 (en) * | 2000-11-21 | 2001-12-18 | Advanced Micro Devices, Inc. | Method and system for embedded chip erase verification |
| KR100463194B1 (ko) * | 2001-02-16 | 2004-12-23 | 삼성전자주식회사 | 낸드형 플래쉬 메모리 장치의 프로그램 방법 |
| JP2002367381A (ja) * | 2001-06-05 | 2002-12-20 | Sony Corp | 不揮発性半導体メモリ装置およびその書き込み方法 |
| US6847550B2 (en) * | 2002-10-25 | 2005-01-25 | Nexflash Technologies, Inc. | Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor |
| US7073103B2 (en) | 2002-12-05 | 2006-07-04 | Sandisk Corporation | Smart verify for multi-state memories |
| KR100546343B1 (ko) * | 2003-07-18 | 2006-01-26 | 삼성전자주식회사 | 플래시 메모리 장치의 프로그램 방법 |
| JP4170952B2 (ja) | 2004-01-30 | 2008-10-22 | 株式会社東芝 | 半導体記憶装置 |
| KR100706247B1 (ko) * | 2005-06-03 | 2007-04-11 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 독출 방법 |
| US7301817B2 (en) * | 2005-10-27 | 2007-11-27 | Sandisk Corporation | Method for programming of multi-state non-volatile memory using smart verify |
| US7366022B2 (en) * | 2005-10-27 | 2008-04-29 | Sandisk Corporation | Apparatus for programming of multi-state non-volatile memory using smart verify |
| KR100683856B1 (ko) * | 2006-01-12 | 2007-02-15 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
| KR100683858B1 (ko) | 2006-01-12 | 2007-02-15 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
| KR100816752B1 (ko) | 2006-09-15 | 2008-03-25 | 삼성전자주식회사 | 프로그램 루프 동작을 수행하는 상 변화 메모리 장치 및그것의 프로그램 방법 |
| KR100816155B1 (ko) * | 2006-12-28 | 2008-03-21 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 멀티레벨 셀 프로그램 방법 |
| US7649783B2 (en) * | 2007-01-25 | 2010-01-19 | Micron Technology, Inc. | Delayed activation of selected wordlines in memory |
| KR100927119B1 (ko) | 2007-05-10 | 2009-11-18 | 삼성전자주식회사 | 불 휘발성 반도체 메모리 장치 및 그것의 프로그램 방법 |
| KR101261008B1 (ko) * | 2007-08-14 | 2013-05-06 | 삼성전자주식회사 | 3-레벨 비휘발성 메모리 셀을 포함하는 비휘발성 메모리장치의 구동 방법 및 그 방법을 사용하는 비휘발성 메모리장치 |
| JP5172555B2 (ja) | 2008-09-08 | 2013-03-27 | 株式会社東芝 | 半導体記憶装置 |
| KR101554727B1 (ko) | 2009-07-13 | 2015-09-23 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 방법 |
| US8520426B2 (en) | 2010-09-08 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for driving semiconductor device |
| US8374031B2 (en) | 2010-09-29 | 2013-02-12 | SanDisk Technologies, Inc. | Techniques for the fast settling of word lines in NAND flash memory |
| KR101855435B1 (ko) | 2010-11-15 | 2018-05-08 | 삼성전자주식회사 | 최대 검증-시간을 조절할 수 있는 비휘발성 메모리 장치, 이의 동작 방법, 및 이를 포함하는 메모리 시스템 |
| US8737132B2 (en) | 2012-01-06 | 2014-05-27 | Sandisk Technologies Inc. | Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory |
| JP5818740B2 (ja) * | 2012-04-17 | 2015-11-18 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | テキストデータストリームに含まれるアイテムの中から出現頻度の高いアイテムを特定する方法、装置及びコンピュータプログラム |
| JP2014053060A (ja) | 2012-09-07 | 2014-03-20 | Toshiba Corp | 半導体記憶装置及びその制御方法 |
| JP2014063551A (ja) | 2012-09-21 | 2014-04-10 | Toshiba Corp | 半導体記憶装置 |
| JP6538426B2 (ja) | 2014-05-30 | 2019-07-03 | 株式会社半導体エネルギー研究所 | 半導体装置及び電子機器 |
| US9633719B2 (en) | 2015-05-29 | 2017-04-25 | Micron Technology, Inc. | Programming memory cells to be programmed to different levels to an intermediate level from a lowest level |
| CN108281163B (zh) * | 2018-02-05 | 2020-09-25 | 杭州旗捷科技有限公司 | 耗材芯片存储器电压反馈方法及耗材芯片 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5440505A (en) * | 1994-01-21 | 1995-08-08 | Intel Corporation | Method and circuitry for storing discrete amounts of charge in a single memory element |
| US5539690A (en) * | 1994-06-02 | 1996-07-23 | Intel Corporation | Write verify schemes for flash memory with multilevel cells |
| US5596526A (en) * | 1995-08-15 | 1997-01-21 | Lexar Microsystems, Inc. | Non-volatile memory system of multi-level transistor cells and methods using same |
| JP3180669B2 (ja) * | 1996-06-03 | 2001-06-25 | 日本電気株式会社 | 不揮発性半導体メモリおよびその書き込み方法 |
-
1997
- 1997-01-31 JP JP01834997A patent/JP3409986B2/ja not_active Expired - Lifetime
-
1998
- 1998-01-26 TW TW087101025A patent/TW379450B/zh not_active IP Right Cessation
- 1998-01-26 CN CNB981062512A patent/CN1204561C/zh not_active Expired - Lifetime
- 1998-01-29 US US09/015,611 patent/US6028792A/en not_active Expired - Lifetime
- 1998-01-30 DE DE69830089T patent/DE69830089T2/de not_active Expired - Lifetime
- 1998-01-30 EP EP05009495A patent/EP1564752A1/de not_active Withdrawn
- 1998-01-30 EP EP98101617A patent/EP0856850B1/de not_active Expired - Lifetime
- 1998-01-31 KR KR1019980002664A patent/KR100272035B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW379450B (en) | 2000-01-11 |
| CN1195176A (zh) | 1998-10-07 |
| KR100272035B1 (ko) | 2000-11-15 |
| CN1204561C (zh) | 2005-06-01 |
| JP3409986B2 (ja) | 2003-05-26 |
| KR19980070971A (ko) | 1998-10-26 |
| EP0856850A2 (de) | 1998-08-05 |
| US6028792A (en) | 2000-02-22 |
| EP0856850B1 (de) | 2005-05-11 |
| EP1564752A1 (de) | 2005-08-17 |
| EP0856850A3 (de) | 1999-06-16 |
| JPH10214492A (ja) | 1998-08-11 |
| DE69830089T2 (de) | 2006-01-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |