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DE69610097D1 - Vorrichtung und verfahren zur reduzierung der latenzzeit des lesefehlgriffs von cachespeichern - Google Patents

Vorrichtung und verfahren zur reduzierung der latenzzeit des lesefehlgriffs von cachespeichern

Info

Publication number
DE69610097D1
DE69610097D1 DE69610097T DE69610097T DE69610097D1 DE 69610097 D1 DE69610097 D1 DE 69610097D1 DE 69610097 T DE69610097 T DE 69610097T DE 69610097 T DE69610097 T DE 69610097T DE 69610097 D1 DE69610097 D1 DE 69610097D1
Authority
DE
Germany
Prior art keywords
reducing
cache storage
latent time
read mistake
mistake
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69610097T
Other languages
English (en)
Other versions
DE69610097T2 (de
Inventor
Uwe Kranich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69610097D1 publication Critical patent/DE69610097D1/de
Application granted granted Critical
Publication of DE69610097T2 publication Critical patent/DE69610097T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE69610097T 1995-06-05 1996-06-04 Vorrichtung und verfahren zur reduzierung der latenzzeit des lesefehlgriffs von cachespeichern Expired - Lifetime DE69610097T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/464,351 US5752263A (en) 1995-06-05 1995-06-05 Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads
PCT/US1996/008635 WO1996039657A1 (en) 1995-06-05 1996-06-04 Apparatus and method for reducing read miss latency

Publications (2)

Publication Number Publication Date
DE69610097D1 true DE69610097D1 (de) 2000-10-05
DE69610097T2 DE69610097T2 (de) 2001-05-10

Family

ID=23843593

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69610097T Expired - Lifetime DE69610097T2 (de) 1995-06-05 1996-06-04 Vorrichtung und verfahren zur reduzierung der latenzzeit des lesefehlgriffs von cachespeichern

Country Status (6)

Country Link
US (1) US5752263A (de)
EP (1) EP0834119B1 (de)
JP (1) JP3763579B2 (de)
KR (1) KR100397026B1 (de)
DE (1) DE69610097T2 (de)
WO (1) WO1996039657A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6092149A (en) * 1997-05-28 2000-07-18 Western Digital Corporation Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses
US6044439A (en) * 1997-10-27 2000-03-28 Acceleration Software International Corporation Heuristic method for preloading cache to enhance hit rate
US6308241B1 (en) * 1997-12-22 2001-10-23 U.S. Philips Corporation On-chip cache file register for minimizing CPU idle cycles during cache refills
US6032249A (en) * 1998-02-02 2000-02-29 International Business Machines Corporation Method and system for executing a serializing instruction while bypassing a floating point unit pipeline
EP0936539B1 (de) 1998-02-12 2012-10-31 Infineon Technologies AG Vorrichtung und Verfahren zum Holen von Befehlen für eine programmgesteuerte Einheit
US20020188805A1 (en) * 2001-06-05 2002-12-12 Sailesh Kottapalli Mechanism for implementing cache line fills
WO2003034205A1 (en) * 2001-10-12 2003-04-24 Pts Corporation Early resolving instructions
GB2381602B (en) * 2001-10-12 2004-04-14 Siroyan Ltd Early resolving instructions
US7162588B2 (en) * 2002-08-23 2007-01-09 Koninklijke Philips Electronics N.V. Processor prefetch to match memory bus protocol characteristics
US7647477B2 (en) * 2004-05-11 2010-01-12 Sun Microsystems, Inc. Branch target aware instruction prefetching technique
US7590830B2 (en) * 2004-05-28 2009-09-15 Sun Microsystems, Inc. Method and structure for concurrent branch prediction in a processor
KR100673311B1 (ko) * 2005-05-23 2007-01-24 임재성 칠러 겸용 항온항습기
KR100775442B1 (ko) * 2006-08-11 2007-11-12 김종훈 전자부품 성능검사를 위한 항온 제어 장치
US20140164738A1 (en) * 2012-12-07 2014-06-12 Nvidia Corporation Instruction categorization for runahead operation
US20190303037A1 (en) * 2018-03-30 2019-10-03 Ca, Inc. Using sequential read intention to increase data buffer reuse

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
US4882642A (en) * 1987-07-02 1989-11-21 International Business Machines Corporation Sequentially processing data in a cached data storage system
US4860199A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Hashing indexer for branch cache
DE69128741T2 (de) * 1990-05-18 1998-07-16 Koninkl Philips Electronics Nv Mehrstufiger Befehlscachespeicher und Verwendungsverfahren dafür
US5235697A (en) * 1990-06-29 1993-08-10 Digital Equipment Set prediction cache memory system using bits of the main memory address
US5483641A (en) * 1991-12-17 1996-01-09 Dell Usa, L.P. System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities
US5553305A (en) * 1992-04-14 1996-09-03 International Business Machines Corporation System for synchronizing execution by a processing element of threads within a process using a state indicator
US5461718A (en) * 1992-04-24 1995-10-24 Digital Equipment Corporation System for sequential read of memory stream buffer detecting page mode cycles availability fetching data into a selected FIFO, and sending data without aceessing memory
US5371870A (en) * 1992-04-24 1994-12-06 Digital Equipment Corporation Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching
EP0612013A1 (de) * 1993-01-21 1994-08-24 Advanced Micro Devices, Inc. Kombination von Vorausholungspuffer und Befehlscachespeicher
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5588128A (en) * 1993-04-02 1996-12-24 Vlsi Technology, Inc. Dynamic direction look ahead read buffer
US5388247A (en) * 1993-05-14 1995-02-07 Digital Equipment Corporation History buffer control to reduce unnecessary allocations in a memory stream buffer
US5524220A (en) * 1994-08-31 1996-06-04 Vlsi Technology, Inc. Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems

Also Published As

Publication number Publication date
US5752263A (en) 1998-05-12
JP3763579B2 (ja) 2006-04-05
JPH11506854A (ja) 1999-06-15
EP0834119B1 (de) 2000-08-30
KR19990022419A (ko) 1999-03-25
KR100397026B1 (ko) 2003-11-20
DE69610097T2 (de) 2001-05-10
EP0834119A1 (de) 1998-04-08
WO1996039657A1 (en) 1996-12-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GARAND CAYMAN, KY