DE69602742T2 - CIRCUITS, SYSTEMS AND METHODS FOR CHANGING STORAGE DATA USING LOGICAL FUNCTIONS - Google Patents

Description

FIELD OF INVENTION

The present invention relates generally to electronic circuits and, more particularly, to circuits, systems, and methods for modifying stored data using logic functions.

BACKGROUND OF THE INVENTION

A typical processing system with video/graphics display capability has a central processing unit (CPU), a display controller coupled to the CPU by a system bus, a system memory also coupled to the system bus, a frame buffer coupled to the display controller by a local bus, peripheral circuitry (e.g., clock drivers and signal converters), display driver circuitry, and a display unit. The CPU generally provides overall system control and controls the contents of the graphics images to be displayed on the display unit in response to user commands and program instructions read from system memory. The display controller, which may be, for example, a video graphics architecture (VGA) controller, is generally interfaced to the CPU and display driver circuitry, exchanges graphics data and/or video data with the frame buffer during data processing and display refresh operations. , controls frame buffer operations, and performs additional processing on the target graphics or video data, such as color expansion. The display driver circuitry converts the digital data received from the display controller to the analog levels required by the display device to produce graphics/video display images. The display device may be any type of device that presents the user with images that convey the information represented by the processed graphics/video data.

The frame buffer, typically constructed of dynamic random access memory (DRAM) devices, stores words of graphics or video data that define the color/grayscale of each pixel of an entire display frame during processing operations such as filtering or drawing images. During display refresh, this "pixel data" is read from the frame buffer one pixel at a time as the corresponding pixels on the display screen are refreshed. Thus, the size of the frame buffer directly corresponds to the number of pixels in each display frame and the number of bits (bytes) in each word used to define each pixel. The size and performance of the frame buffer is determined by a number of factors, such as the number of monitor pixels, the monitor DOT clock rate, the display refresh, data read/write frequency, and memory bandwidth, to name a few.

It is often necessary to operate on selected pixel data within the frame buffer using logical functions to effect changes on the display screen. For example, when a cursor crosses a window boundary or when a window is "clicked", it may be desirable to change the color of the window for emphasis. Another example is the implementation of drawing, Tools that allow the user to control the opacity of a given display window. In currently available systems, a selected byte of data is typically read from a given location in the frame buffer, a given logical operation is modified, and the data is appropriately modified and then written back into the frame buffer as modified data. These operations are typically performed using either two antiparallel RAS accesses or a read-modify-write cycle. In the former case, two RAS/CAS cycles are required, one to read the unmodified data from memory and one to write the modified data back into memory. In the latter case, an extended RAS/CAS cycle is used during which the data is read out, modified, and written back in. In either case, an execution (time) sacrifice is made with each byte of data to be modified. If a large number of bytes are modified, the impact on system performance can be significant.

Several attempts have been made to reduce or eliminate the problems with read-modify-write updates in memory. One such attempt is described in US Patent 5,432,743 (the '743 patent) and its Japanese equivalent JP-A-06 076 565. Another is set forth in GB-A-2 225 567 (the '657 patent). The systems disclosed in these documents can be described as follows.

In the system disclosed in the '743 patent (and its Japanese equivalent), data in a predetermined memory cell can be selectively subjected to a logical operation. In particular, a level circuit is used to determine the logical level of modifying data written into the memory in response to a logical operation enable signal. As a As a result, the modifying data in the given cell is either inverted or remains the same.

The '743 system has several significant disadvantages. First, two separate inputs are required to input the modifying data and the logical operation enable signal. This is in addition to the inputs of US-A-5,432,743 and JP-A-06 076 565 for the normal memory control signals, such as the row and column address clock signals and the write enable signal. Second, a number of additional internal signals must be generated to ensure accurate operation synchronization in this system. Finally, because the '743 system can perform either logical OR or logical AND operations, it cannot support both operations in a single set of control circuitry. In the words of the designers of the '743 patent, "the circuits are designed to realize" a given logical operation; the problem of a single circuit being able to perform one or more possible logical operations in response to a control signal or the like remains unsolved.

In the system disclosed in the '657 patent, data held in a single cell is fed back by the sense amplifier to a series of gates and transistors. These gates and transistors, responsive to several internally generated signals as well as the loop back bit, determine whether the data within the cell requires inversion. If inversion is not required, the sense amplifier continues to hold the existing bit, otherwise the state of the sense amplifier is reversed.

The '657 system is also subject to a number of disadvantages. Admittedly, a number of "quick operations" are required for a given logical operation. This forces a number of control signals to be input through a corresponding number of pins. As is well known, extra pins increase the cost of the device and the packaging size. Most importantly, data looping requires additional circuitry to perform the loopback itself and requires the sense amplifier to be active and hold valid data.

Thus, the need has arisen for devices, systems and methods to be able to perform logical operations on data stored in a memory. In particular, the need has arisen for devices, systems and methods that minimize the performance penalties incurred by currently available systems, particularly those systems that require both multiple read and write cycles to be performed while performing a logical operation. Furthermore, such devices, systems and methods should be particularly applicable to performing logical operations on pixel data stored in a frame buffer.

SUMMARY OF THE INVENTION

According to the principles of the present invention, selected logical operations can be performed on data stored within selected locations in a memory without multiple or extended RAS/CAS cycles. The principles of the present invention generally take advantage of the fact that during AND and OR operations, a data bit being operated on either remains the same or is replaced by a corresponding bit of the modifying data depending on the state of the bit of the modifying data.

According to a first aspect of the present invention, there is provided a memory system comprising an array of memory cells arranged in rows and columns and circuitry for selectively performing logical operations on a data bit stored in a selected cell using a bit of received modifying data and a mode data bit. The circuitry for performing the logical operations performs a logical AND operation as a pure function of a logical state of the modifying bit and writes the modifying data bit into the selected cell when the modifying data bit is a logical zero and retains an existing bit stored in the cell when the modifying data bit is a logical one. Further, circuitry is provided for receiving and storing the modifying data bit and the mode data bit in series through a single data port, the mode data bit being latched on a falling edge of a row address clock signal and the modifying data bit being latched on the falling edges of both the column address clock signal and the write enable signal.

According to a second aspect of the present invention, there is provided a memory system comprising an array of memory cells arranged in rows and columns and circuitry for selectively performing logical operations on a data bit stored in a selected cell using a bit of the received modifying data and a mode data bit. The circuitry for performing the logical operations performs a logical OR operation as a function of a logical state of the modifying bit and writes the bit of the modifying data into the selected cell when the bit of the modifying data is a logical one and maintains an existing bit stored in the cell when the bit of the modifying data is a logical is zero. A circuit is further provided for receiving and holding the modifying data bit and the mode data bit in series through a single data port, the mode data bit being held on the falling edge of a row address clock signal and the modifying data bit being held on the falling edges of both the column address clock signal and the write enable signal.

Devices, systems and methods embodying the principles of the present invention have significant advantages over the prior art. In particular, the principles of the present invention enable the minimization of the performance penalties incurred by currently available systems, circuits and methods for modifying data bits within a memory device, and particularly in those systems that require multiple read and write cycles to be performed. Furthermore, the principles of the present invention are particularly useful for performing logical operations on pixel data stored in a frame buffer.

The foregoing has set forth the features and technical advantages of the present invention in considerable detail so that the following detailed description of the invention may be better understood. Additional features and advantages of the invention are described below and form the subject of the claims of the invention. It should be noted that those skilled in the art may readily utilize the disclosed conception and specific embodiment as a basis for modifying or developing other structures for carrying out the same purpose of the invention.

SHORT DESCRIPTION OF THE CHARACTERS

For a complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

Figure 1 is a functional block diagram of a video/graphics processing system embodying the principles of the present invention;

Fig. 2 is a more detailed functional block diagram of the image buffer of Fig. 1 according to an embodiment of the present invention;

Fig. 3 is a signal waveform diagram to explain the functioning of the circuit according to Fig. 2 during a modification process; and

Fig. 4 is a schematic electrical diagram of the internal circuit for generating the write enable signal embodied in the circuit of Fig. 2.

DETAILED DESCRIPTION OF THE INVENTION

Fig. 1 is a high level functional block diagram of the portion of a processing system 100 that controls the display of graphics and/or video data. The system 100 includes a central processing unit 101, a system bus 102, a display controller 103, a frame buffer 104, a digital-to-analog converter (DAC) 105, and a display device 106. In a preferred embodiment of the present invention, the display controller 103 and the frame buffer 104 and DAC 105 are fabricated together on a single integrated circuit chip 107.

The CPU 101 controls the overall operation of the system 100, determines the content of the graphic data to be displayed on the display unit 106 using user commands, and performs various data processing functions. For example, the CPU 101 may The CPU 101 may be a dedicated microprocessor used in commercial personal computers. The CPU 101 communicates with the rest of the system 100 via the system bus 102, which may be, for example, a local bus, an ISA bus, or a PCI bus. The DAC 105 receives digital data from the controller 103 and in response outputs the necessary analog data to drive the display 106. Depending on the specific implementation of the system 100, the DAC 105 may also include a color palette, YUV to RGB format conversion circuitry, and/or x and y zoom circuitry, to name a few options.

In the illustrated embodiment, controller 103 is a display controller, such as a VGA controller, that controls, among other things, the exchange of graphics and/or video data with frame buffer 103, controls memory refresh, and performs data processing functions such as color expansion. A display controller is the "master" for the specific application of the display and thus frees CPU 101 to perform computing tasks. In addition, the architecture of a display controller optimizes it to perform graphics and video functions in a more sophisticated manner than a general purpose microprocessor. Controller 103 may also include a color palette, cursor generation hardware, and/or video/graphics conversion circuitry, to name a few options.

The frame buffer 104 is preferably a dynamic random access memory (DRAM) comprising an array of rows and columns of DRAM cells and associated address and control circuitry, as well as row and column decoders, read and write buffers, and sense amplifiers. The frame buffer 104 is discussed in more detail below.

The display 106 may be, for example, a CRT unit or a liquid crystal display, an electroluminescent display (ELD), plasma display (PLD), or other type of display device that displays images on a display screen in the form of a plurality of pixels. Furthermore, the display 106 may be a state of the art device such as a digital micromirror device or a silicon carbide type device that directly accepts digital data. Note that in alternative embodiments, the "display" 106 may be another type of output device such as a laser printer or similar document viewing/printing application.

In accordance with the principles of the present invention, selected logical operations may be performed on data words within selected locations within the frame buffer 104. In particular, these principles provide the advantage that during AND and OR operations, a data bit in memory being operated on either remains the same or is replaced by the corresponding bit of modifying data supplied by the controller 103, depending on the status of the bit of modifying data. This feature is illustrated in Table 1:

As can be seen from Table 1, during an AND operation, the resulting data for those input conditions specified in the second and fourth rows (i.e. the modifying data equal to logic one) remain the same as already in the selected memory cell. In this case, a read (refresh) of the data within the given cell operation is all that is required to perform the "modification." This can be accomplished with a single RAS/CAS cycle with the write enable signal inactive. During an AND operation, with the input conditions set in rows one and three (i.e., the modifying data is logic zero), the resulting data is the same as the modifying data. In this case, all that is required to modify the data in the memory cell is to write the modifying data directly into the memory cell. This can also be accomplished with a single RAS/CAS cycle, only this time the write enable signal is active. In any case, there is no need to perform both a read and a write operation to modify the data in the memory cell. Furthermore, as discussed further below in connection with Figure 2, there is also no need to actually perform the AND operation; the data is either simply refreshed by a read operation or written directly as a function of the status of the corresponding bit of the modifying data.

For an OR operation, the resulting date remains the same as the date already stored in the selected memory cell for input conditions as specified in the first and third lines (i.e., the modifying data is equal to logic zero). Again, all that is required to "modify" the date in the cell is to perform a single RAS/CAS cycle read operation. For the input conditions specified in the second and fourth lines (i.e., the modifying data is equal to logic one), the resulting date is the same as the modifying date and therefore all that is required for the modifying date is to write it directly into the selected memory location using a conventional single RAS/CAS write cycle. As was the case with the AND operation, there is no need to perform an actual OR operation; the data is either refreshed by a read operation or the modifying data is written directly as a function of the modifying data.

Similar principles can be followed for the modification of data within given memory cells using NAND and NOR operations. In the case of a NAND operation, the modifying data is inverted (i.e., the complement is taken) and the conditions for an OR operation are applied as discussed immediately above. For a NOR operation, the complement is again taken for the modifying data and the conditions for an OR operation are applied as discussed.

Figure 2 is a more detailed functional block diagram of the frame buffer 104 in accordance with a preferred embodiment of the present invention. A waveform graphical representation describing the operation of the circuit of Figure 2 is provided in Figure 3. The frame buffer 104 has an array 200 of conventional dynamic random access memory (DRAM) cells arranged in M rows and N columns. Coupled to the array 200 are the row decoder circuit 201, sense amplifiers 202 and column decoder circuit 203. In the preferred embodiment, N sense amplifiers 202 are provided, one for each column in array 200. Row decoder circuit 201 and column decoder circuit 203 control access to P-cell storage locations from a selected row of array 200 in a conventional manner in response to row and column addresses held in address latches 204 by means of RAS and CAS.

The frame buffer 104 also has a read/write control circuit embodying the principles of the present invention. Reading of data from addressed locations in the array 200 is accomplished by sense amplifier 205 and output buffer 206 when the output enable signal is active. The write/modify circuit includes a first data latch 207 which holds data to be written into the array 200 during a conventional write and holds the modifying data during a modify. Writes and modifications are performed by the write buffer 208 which has P conventional write buffers for writing into each accessed P cell location. During the modification cycles, the mode decoder 209 decodes the mode control data held in the second data latch 210 to determine whether an AND or OR operation (consequently, if complementary modification data is used, a NOR or NAND operation) should take place. In the preferred embodiment, the latch 210 receives and latches at least two data bits which, together with the conventional (external) write enable signal WE, determine whether a conventional write or an AND or OR operation has been requested by the controller 103.

In embodiments where the controller 103 and the frame buffer 104 are fabricated as separate components, the frame buffer 104 also has data ports 211 and associated TTL drivers 212 for receiving data (DQ), address, RAS, CAS, WE and OE signals from the controller chip.

During an AND or NOR operation, the write buffer 208 writes the modifying data held in the data latch 207 into the addressed memory location if the modifying data is logical zero. If the modifying data is logical one, no writing is performed and instead a Read (as is well known, a read operation refreshes the existing data stored in a given accessed memory cell, whatever its status). During an OR or NAND operation, the write buffer 208 writes the modifying data held in the data latch 207 to the addressed memory cell when the modifying data is a logic one; a read occurs when the modifying data is a logic zero. In either case, the modifying data is controlled by enabling or not enabling the write buffer 208.

Figure 4 is a logic diagram of the preferred circuitry 400 for enabling or disabling write buffer 208 to perform the cell data modifications described above. Preferably, this write circuitry is located within write buffer 209 along with the write buffers themselves, although in alternative embodiments, circuitry 400 may be located anywhere on the chip. Circuitry 400 generates an "internal write enable" signal that enables/disables write buffer 208 during data modification operations. The internal write enable signal is derived from the conventional write enable signal generated by controller 103 for conventional writing, the MODE_AND and MODE_OR control signals, and the modifying data. In the preferred embodiment, the circuit 400 is duplicated by the number P so that each of the P bits accessed in the array 200 during a single addressing cycle can be independently modified. Accordingly, in order to independently modify a number of P bits at a time, the controller 103 generates P bits of modifying data which are held in the latch circuit 207.

The control signals MODE_AND and MODE_OR are generated by the decoder circuit 209 from a control word (opcode) which held in the data latch 210. Assuming a modification is requested by the controller, the external write enable signal is active (i.e., high). When the MODE_AND bit is high and the MODE_OR bit is low, an AND operation is selected and the internal write enable signal is active (high) when the modifying data is a logic zero. When the MODE_AND bit is low and the MODE_OR bit is high, an OR operation is selected and the internal write enable signal is active (high) when the modifying data is a logic one. For a conventional write, the MODE_AND and MODE_OR are inactive (low), so the internal write enable signal simply follows the external write enable signal.

In the case of a NAND operation, the complement of the modifying data is taken and the OR mode is selected. In the case of a NOR operation, the complement of the modifying data is taken and the AND mode is applied. Note that most controllers, such as controller 103, advantageously simultaneously generate complementary data for use in other operations.

The waveform graphical representation of Fig. 3 illustrates the timing of a given modifying operation. On the falling edge of the row address strobe signal (RAS), the mode select signal is latched in the data latch 201. The falling edge of the RAS also latches the row address for the selected location in array 200 in the address latch 204. The column portion of the address is latched in the address latch 204 on the falling edge of the column address strobe signal (CAS). When the column address strobe signal (CAS) and the external enable signal both go low, the modifying data is latched in the data latch 207. The data within the data latch 210 is decoded by the mode decoder 209. and presented to the circuitry shown in Fig. 4 as MODE_AND and MODE_OR, as modifying data within the data latch 207 and the external write enable signal. Modification of the addressed cell or cells (depending on the number of cells P in each address location) continues as previously indicated.

Although the present invention and its advantages have been described in detail, it is to be noted that various changes, substitutions and modifications may be made without departing from the scope of the invention as defined in the appended claims.

Claims (5)

1. A memory system (104) comprising an array (200) of memory cells arranged in rows and columns, and circuitry (208) for selectively performing logical operations on a data bit stored in a selected cell using a bit of received modifying data and a mode data bit for selecting a logical operation to perform, circuitry (208) for performing logical operations that performs a logical AND operation purely as a function of a logical state of the modifying bit and writes the modifying data bit into the cell when the modifying data bit is logical 0 and maintains an existing bit stored in that cell when the modifying data bit is logical 1, marked by: a circuit (207, 210) for receiving and storing the modifying data bit and the mode data bit in series through a single data port (211), wherein the mode data bit is latched upon a falling edge of a row address strobe signal and will latch the modifying data bit when a column address strobe signal and a write enable signal both go low. 2. The memory system of claim 1, wherein the circuit for performing the logical operations (208) is further operable to perform an OR operation as a function of the modifying bit by writing the bit of the modifying data into the cell when the bit of the modifying data is logical 1 and holding the bit stored in the cell when the bit of the modifying data is a logic 0. 3. Storage system according to claim 2, wherein the circuit (208) for selectively performing logical operations further comprises: a row and column decoder circuit (202, 203) for accessing the selected cell; a write buffer (208) for selectively writing the bit of the modifying data into the selected cell in response to a write enable signal; and a circuit (208) for generating the write enable signal when the bit of the modifying data is logic 1 during an OR operation and when the bit of the modifying data is logic 0 during an AND operation. 4. A memory system (104) comprising an array (200) of memory cells arranged in rows and columns and a circuit (208) for selectively performing logical operations on a bit of data stored in a selected cell using a bit of received modifying data and a mode data bit to select a logical operation to perform, wherein the circuit (208) for performing logical operations performs a logical OR operation purely as a function of a logical state of the modifying bit and writes that bit of modifying data into the cell when the bit of modifying data is a logical 1 and maintains an existing bit stored in that cell when the bit of modifying data is a logical 0; marked by: a circuit (207, 210) for receiving and locking the modifying data bit and the mode data bit in series through a single data port (211), the mo data bit is latched at a falling edge of the row address strobe, and the modifying data bit is latched when a column address strobe signal and a write enable signal both go low. 5. The memory of claim 4, wherein the circuit (208) for performing logical operations is further operable to perform an AND operation by writing the bit of the modifying data into the cell when the bit of the modifying data is a logical 0 and by holding the bit stored in the cell when the bit of the modifying data is a logical 1.