DE69520974T2 - An integrated semiconductor circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit having a two-dimensional memory array, and more particularly to a semiconductor integrated circuit that enables either a digital filtering operation such as a convolutional processing operation or a processing operation using two-dimensional data such as searching for the motion vector of a moving image to be carried out in real time.

Among the various information processing operations on two-dimensional data, the image processing operation involves a two-dimensional array of pixels on a screen, so that the two-dimensional data often has to be processed. A two-dimensional filtering operation is one such information processing operation.

Fig. 2 shows a known semiconductor integrated circuit for processing an image. This device is suitable for a two-dimensional filtering operation as described by Yoshiki Kobayashi, Tadashi Fukushima, Syuichi Miura, Morio Kanasaki and Kohtaro Hirasawa in "A BiCMOS Image Processor with Line Memories", ISSCC Digest of Technical Papers, pages 182 to 183, February 1987.

The semiconductor integrated circuit of Fig. 2 is summarized here. As shown in Fig. 2(a), the semiconductor integrated circuit is composed of a preprocessing circuit PPU for performing a preprocessing operation such as a threshold operation on the input image data; line memories LM1 and LM2 for storing images of one line to cause a delay of one line each; a shift register SR; a data memory DM for storing the weighting coefficients of the filter; a processing circuit PE, and connection units LU1 and LU2 with adders. Fig. 2B shows an example of calculation in the case where the semiconductor integrated circuit of Fig. 2A is used to calculate a 3 × 3 spatial filter. In Fig. 2B, the reference symbols F32 and F(x + i)(y + i) denote the (density) value of the pixel in the third row and the second column in the data block of the input image and the value of the pixel in the (x + i)-th row and the (y + i)-th column, respectively. The reference symbols Wij, W-1-1, - - - and W11 denote filter coefficients and the reference symbols Rxy denote the value of the pixel in the row x and the column y in the data block of the processed output image. The operations of the semiconductor integrated circuit of Fig. 2A are described with reference to Fig. 2B. In the calculation for the 3 x 3 spatial filter, as As is well known, the value of Rxy can be expressed by the sum of the products of the values of the pixels of the input images and the filter coefficients, as shown in the equation in Fig. 2B. Therefore, to determine the value of Rxy, the values of the pixels of nine input images around the pixel in row x and column y in the data block of the input image are required. The input image data is first fed to the preprocessing circuit PPU. Since the filtering operation does not involve threshold processing, the input image data is passed as it is to the shift register SR and the line memory LM1. The output of the line memory LM1 is output with a delay of one line. The output of the line memory LM1 is fed to the line memory LM2, from which it is output with a further delay of one line. As a result, the values of the pixels of the input image required for calculating the 3 × 3 spatial filter are stored in different shift registers for each line. Fig. 2B shows the state in which the values of the nine pixels of the input image are stored in the shift registers around F22. The values of the nine pixels stored in the shift registers are successively input to the processing circuits PE1, PE2 and PE3, where their products with the corresponding coefficients are calculated. The resulting products are input to the connection units LU1 and LU2 and added there, so that in this case the value of R22 is determined. In the known semiconductor integrated circuit of Fig. 2, therefore, the values of the pixels over the three lines are input to the three processing circuits by making use of the delays of the line memories so that the three multiplications are carried out in parallel. As a result, the spatial filter can be carried out at high speed. The cited reference mentions that a BiCMOS circuit experimentally manufactured using 1.8 micron technology can perform the calculations for the 3 x 3 spatial filter for a TV picture of 512 x 512 pixels in real time.

A first object of the present invention is to provide a semiconductor integrated circuit for carrying out the processing operations on two-dimensional data with high parallelism, and a second problem to be solved is to accommodate a number of such processing circuits in a highly integrated semiconductor chip so that the processing operations are carried out by means of two-dimensional memory cell arrays with high parallelism, wherein the memory cell arrays should be capable of processing a large number of two-dimensional data.

In the described, known integrated semiconductor circuit of Fig. 2, the calculations for the spatial filter are carried out at high speed by the nine Multipliers to calculate an output pixel are always executed three by three in parallel. In the future, however, the parallelism must be increased to achieve higher speed.

As the picture quality of televisions, workstations, personal computers and game machines rises to a higher level, the number of pixels for an image also increases, and the pixel frequency increases. In addition, portable devices with communication and display functions are expected to become widely used in the near future. It is also expected that such devices are required to provide a clear display by processing the data for a moving image obtained through the communication function. In such devices, a battery with a low voltage is used for power supply. In general, however, as the battery voltage drops, the speed of semiconductor integrated circuits drops in proportion to the drop in the power supply voltage, so that the conventional semiconductor integrated circuit may no longer be able to achieve a sufficient processing speed. To solve this problem, parallelism must be increased to compensate for the drop in processing speed. A semiconductor integrated circuit with higher parallelism that can process two-dimensional data at high speed is therefore desired.

In addition, in image display devices, a so-called "image memory" is used to store the data for at least one display image in order to be able to carry out the generation and processing of an image by the CPU and the display of the image on the screen simultaneously. The size of image display devices can be reduced, especially the size of portable devices, if the processing operations for the image memory and for the two-dimensional data are carried out in a highly parallel manner in a single semiconductor chip.

According to a first aspect of the present invention, an integrated semiconductor circuit is provided with

a memory cell array (MAR) having a number of data lines (DE), a number of word lines (W1 to W3) intersecting the data lines (DE), and a number of memory cells arranged at desired interfaces between the data lines (DE) and the (W1 to W3);

a parallel data transmission circuit (TRC) for parallel transmission of a number of data from the number of data lines (DE); and with

a number of processing circuits (PE1 to PEn) for receiving the number of data transmitted by the parallel data transmission circuit (TRC) as input signals,

wherein the parallel data transmission circuit (TRC) is arranged to connect the data lines (DG) to the processing circuits (PE1 to PEn) in a sequence which includes

i) a first connection arrangement in which each data line is connected to a first corresponding processing circuit, and

ii) a second connection arrangement in which each data line is connected to a second corresponding processing circuit;

wherein the first and second corresponding processing circuits for each data line are adjacent, and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to one another.

According to a second aspect of the present invention, an integrated semiconductor circuit is provided with

a memory cell array (MAR) having a number of data line groups (DG), a number of word lines (W1 to W3) intersecting the data line groups (DG), and a number of memory cells arranged at desired interfaces between the data line groups (DG) and the word lines (W1 to W3);

a parallel data transmission circuit (TRC) for parallel transmission of a number of data groups from the number of data line groups (DG); and

a number of processing circuits (PE1 to PEn) for receiving the number of data groups transmitted by the parallel data transmission circuit (TRC) as input signals;

wherein the parallel data transmission circuit (TRC) is arranged to connect the data line groups (DG) to the processing circuits (PE1 to PEn) in a sequence which includes

i) a first connection arrangement in which each data line group is connected to a first corresponding processing circuit; and

ii) a second connection arrangement in which each data line group is connected to a second corresponding processing circuit;

wherein the first and second corresponding processing circuits for each data line group are adjacent and the respective lines to which each processing circuit connected in the first and second connection arrangements, lie next to each other.

According to a third aspect of the present invention, an integrated semiconductor circuit is provided with

a first and a second memory cell array (MAR 1 and MAR 2), each having a number of data lines, a number of word lines intersecting the data lines, and a number of memory cells arranged at desired interfaces between the data lines and the word lines (W1 to W3);

a first parallel data transfer circuit (TRC 1) for parallel transfer of a number of first data from the number of data lines of the first memory cell array (MAR 1);

a second parallel data transfer circuit (TRC 2) for parallel transfer of a number of second data from the number of data lines of the second memory cell array (MAR 2); and

a plurality of processing circuits (PE1 to PEn) for receiving the first and second plurality of data from the first and second parallel data transfer circuits (TRC 1 and TRC 2);

wherein the first parallel data transfer circuit (TRC 1) is arranged to connect the data lines of the first memory cell array (MAR 1) to the processing circuits (PE1 to PEn) in a sequence that includes

i) a first connection arrangement in which each data line of the first memory cell array (MAR 1) is connected to a corresponding processing circuit, and

ii) a second connection arrangement in which each data line of the first memory cell array (MAR 1) is connected to another corresponding processing circuit;

wherein the one and the other corresponding processing circuit for each data line of the first memory cell array (MAR 1) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other; and

wherein the second parallel data transfer circuit (TRC 2) is arranged to connect the data lines of the second memory cell array (MAR 2) to the processing circuits (PE1 to PEn) in a sequence which includes

i) a third connection arrangement in which each data line of the second memory cell array (MAR 2) is connected to a corresponding processing circuit; and

ii) a fourth connection arrangement in which each data line of the second memory cell array (MAR 2) is connected to another corresponding processing circuit;

wherein the one and the other corresponding processing circuits for each data line of the second memory cell array (MAR 2) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other.

According to a fourth aspect of the present invention, an integrated semiconductor circuit is provided with

a first and a second memory cell array (MAR 1 and MAR 2), each having a number of data line groups, a number of word lines intersecting the data line groups, and a number of memory cells arranged at desired intersections between the data line groups and the word lines;

a first parallel data transfer circuit (TRC 1) for parallel transfer of a number of first data groups from the number of data line groups of the first memory cell array (MAR 1);

a second parallel data transfer circuit (TRC 2) for parallel transfer of a number of second data groups from the number of data line groups of the second memory cell array (MAR 2); and

a number of processing circuits (PE1 to PEn) for receiving the number of first and second data groups from the first and second parallel data transfer circuits (TRC 1 and TRC 2);

wherein the first parallel data transfer circuit (TRC 1) is arranged to connect the data line groups of the first memory cell array (MAR 1) to the processing circuits in a sequence which includes

i) a first connection arrangement in which each data line group of the first memory cell array (MAR 1) is connected to a corresponding processing circuit; and

ii) a second connection arrangement in which each data line group of the first memory cell array (MAR 1) is connected to another corresponding processing circuit;

wherein the one and the other corresponding processing circuits for each data line group of the first memory cell array (MAR 1) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other; and

wherein the second parallel data transfer circuit (TRC 2) is arranged to connect the data line groups of the second memory cell array (MAR 2) to the processing circuits in a sequence which includes

i) a third connection arrangement in which each data line of the second memory cell array (MAR 2) is connected to a corresponding processing circuit; and

ii) a fourth connection arrangement in which each data line group of the second memory cell array (MAR 2) is connected to another corresponding processing circuit;

wherein the one and the other corresponding processing circuits for each data line group of the second memory cell array (MAR 2) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other.

Since the areas of the data lines of the two-dimensional memory arrays accessed by adjacent processing circuits may overlap, it is possible to perform a filtering operation for an image by calculating the value of a pixel from the value of a pixel adjacent to the first pixel. For example, in a 3 × 3 filter, the two-dimensionally arranged surrounding 3 × 3 input pixels are required to obtain a result for an output pixel, and the filtering operation can be carried out in the row direction by supplying the adjacent pixels of the same row to a processing circuit. Moreover, if the processing circuit can perform the processing operation by means of a plurality of data groups read out on one of the aforementioned plurality of data line groups by selecting two or more word lines, the filtering operation can be carried out by supplying the one of the 3 × 3 input pixels which is perpendicular to the row direction to a processing circuit. As a result, the filtering operation can be carried out by supplying the 3 × 3 pixels to a processing circuit. In addition, since the adjacent processing circuits have overlapping areas for the data lines that they can access through the parallel data transfer circuit, the convolution operation and the processing operation can be performed using the two-dimensional data of the 3 x 3 filter or the like are executed in parallel by the number of processing circuits,

In the drawing shows:

[Fig.1]

An embodiment for the structure (i.e., a 3 x 3 spatial filter) of a semiconductor integrated circuit according to the present invention.

[Fig.2]

A well-known semiconductor integrated circuit with a line memory.

[Fig.3]

An embodiment for the structure (i.e., a 5 x 5 spatial filter) of a semiconductor integrated circuit according to the present invention.

[Fig.4]

An embodiment of a first structure for increasing the layout pitch of the processing circuit in the embodiment of Fig. 1.

[Fig.5]

An embodiment for the construction of a parallel data transmission circuit in the embodiment of Fig. 4.

[Fig.6]

An embodiment of a method for controlling the parallel data transfer circuit in the embodiments of Figs. 4 and 5.

[Fig.7]

A second embodiment of a structure for increasing the layout pitch of the processing circuit in the embodiment of Fig. 1.

[Fig.8]

An embodiment for the construction of a parallel data transmission circuit in the embodiment of Fig. 7.

[Fig.9]

An embodiment of a method for controlling the parallel data transfer circuit in the embodiments of Figs. 7 and 8.

[Fig.10]

An embodiment for constructing a motion vector processing circuit according to the present invention.

[Fig.11]

An embodiment for the construction of a minimum distance processing circuit for the embodiment of Fig. 10.

Fig. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention, that is, the structure of an apparatus for processing image data input in real time by a 3 x 3 spatial filter. In Fig. 1, not only the structure of the present embodiment is shown, but also the correspondences between the pixels of an image block and the contents of the memory cells of the apparatus and a method of controlling a parallel data transfer circuit are shown. According to the present embodiment, the spatial filters for one line of the output image can be processed in parallel. The present embodiment is constructed as shown to include: a serial access memory SAM1 for storing the input pixels Fxy of one line and for writing these pixels in parallel into a two-dimensional memory array MAR; the two-dimensional memory array MAR for storing the values of the pixels for three lines output from the serial access memory SAM1; a sense amplifier 5A for reading out and holding the values of the pixels of one line from the two-dimensional memory array MAR in parallel; a parallel data transfer circuit TRC for transferring the read values to a group of processing circuits in parallel; a data memory DM for storing filter coefficients; and the grouped processing circuits PE1, PE2, - - - PEn for carrying out multiplication/addition operations in parallel. The operations of the present embodiment will be described below with reference to Fig. 1.

First, the input images, composed of P-bit data, are serially input into the serial access memory SAM1. The input images are written in parallel into a word line W1 of the two-dimensional memory array MAR when the pixel values F11, F12, - - - F1k of the first line are stored. Then, the pixel values of the second and third lines of the input image are written in the same way into word lines W2 and W3 each time they are stored in the serial access memory SAM1. In this way, the two-dimensional memory array MAR prepares the data of the three lines required to calculate the pixel values of the output image. The correspondence between the data block of the input image and the data on the word lines of the two-dimensional memory array MAR is shown in the bottom left of Fig. 1.

While the data of the next line are written into the serial access memory SAM1, the values R11, R12, - - - and R1k of the pixels of the second line of the output image are calculated in parallel. The control of the parallel data transfer circuit This is done through nine processing cycles, as shown in the bottom right of Fig. 1. First, in the first cycle, the input images of a line stored in the word line W of the two-dimensional memory array MAR are read out and held by a data line group DG in the sense amplifier SA. One (L) of the switches L, C and R of a selector SEL of the parallel data transfer circuit TRC constructed from such selectors is switched to ON. As a result, the parallel data transfer circuit TRC transfers the input pixel F 11 to the processing circuit PE1, the input pixel F12 to the processing circuit PE2, - - and the input pixel F1k-2 to the processing circuit PEn. Simultaneously, a weighting coefficient C-1-1 is read out from the data memory DM and multiplied by the input pixel that is input to the processing circuit. Then, in the second cycle, the switch C in the selector SEL is turned ON to input the input pixel F12 to the processing circuit PE1, the input pixel F13 to the processing circuit PE2, - - - and the input pixel F1k-1 to the processing circuit PEn through the parallel data transfer circuit, and these input pixels are multiplied by the weighting coefficient C-10. In the third cycle, the switch R in the selector SEL is turned ON to input the input pixel F13 to the processing circuit PE1, the input pixel F14 to the processing circuit PE2, - - - and the input pixel F1k to the processing circuit PEn through the parallel data transfer circuit, and these input pixels are multiplied by the weighting coefficient C-11. After thus using the input images stored in the word line W1 of the two-dimensional memory array MAR, the word line W2 is selected to read out the input images of one line and hold them in the sense amplifier. Then, in the fourth cycle, the switch L in the selector SEL is turned ON to input the input pixel F21 to the processing circuit PE1, the input pixel F22 to the processing circuit PE2, - - - and the input pixel F2k-2 to the processing circuit PEn. These input pixels are multiplied by the weighting coefficient CO-1 and the products are added to the previously calculated values. Thereafter, in the fifth cycle, the switch C in the selector SEL is turned ON to input the input pixel F22 to the processing circuit PE1, the input pixel F23 to the processing circuit PE2, - - - and the input pixel F2k-1 to the processing circuit PEn. These input pixels are multiplied by the weighting coefficient CO00 and the products are added to the previously calculated values. Similarly, in the sixth cycle, the switch R in the selector SEL is turned ON to input the input pixel F23 into the processing circuit PE1, the input pixel F24 to the processing circuit PE2, - - - and the input pixel F2k to the processing circuit PEn. These input pixels are multiplied by the weighting coefficient C01 and the products are added to the previously calculated values. In the seventh to ninth cycles, by selecting the word line W3, the values R22, R23, - - - and R2k1 of the pixels of the second line of the output image in the processing circuits PE1, PE2, - - - and PEn are determined with similar calculations. These pixel values R22, R23, - - -, R2k-1 are transferred in parallel to the serial access memory SAM2 and output sequentially. The final pixel does not necessarily have an input pixel and may be transferred as it is as shown. To process the output images of the following one line, similar operations may be repeated. That is, when the pixel information of one line is stored in the serial access memory SAM1, it is transferred to the word line of the two-dimensional memory array into which it was rewritten last, so that the output image of one line is processed while the pixel information of the following line is written into the serial access memory SAM1. In the present embodiment, therefore, the 3 × 3 spatial filtering operations for a number of images on the same line of the output image can be processed in parallel and in real time. The individual processing circuits can carry out the processing operations and the data transfers in the period in which the images of one line are input. As a result, the time available for the processing operations is longer than in the conventional methods in which the processing operation is carried out for each period in which a pixel is input. In other words, real time processing can be obtained even when the input pixels have a high frequency.

As described above, in the present embodiment, moreover, the information held in a sense amplifier can be transferred to various processing circuits via the parallel data transfer circuit TRC. As a result, the two-dimensional filtering operations or convolution operations can be carried out in parallel without moving or transferring the data held in the sense amplifier between the sense amplifiers or between the processing circuits during the operations. As a result, no complex circuit is required for transfer operations between the sense amplifiers or between the processing circuits, so that a highly integrated circuit with low power consumption can be realized. In the present embodiment, as shown in Fig. 1, the processing circuits are arranged directly below of the two-dimensional memory array MAR. As a result, the data transmission path from the two-dimensional memory array to the processing circuits can be shortened to a very short, constant distance. In addition to the advantage that the delay time for transmission is short, this provides the further advantage that the processing circuits are less distributed and can thus be easily synchronized. In addition, since the parallel data transmission circuit and the processing circuits are arranged next to and directly below the memory array, they can be highly integrated to reduce the power consumption by transmitting the pixel information.

The embodiment of Fig. 1 was directed to a device for 3 × 3 filter calculations. In the parallel data transfer circuit, therefore, a processing circuit and the data lines for three pixels are connected to each other, and the sense amplifier and the processing circuits are connected with an overlap of two pixels between adjacent processing circuits. However, in the embodiment of Fig. 1, the processing operations of a filter of an arbitrary size of 3 × 3 or more can be obtained by changing the structure of the parallel data transfer circuit and the memory array. Fig. 3 shows an embodiment for the structure of the processing device for a 5 × 5 filter. The present embodiment is modified from the embodiment of Fig. 1 in such a way that the number of word lines of the two-dimensional memory array MAR is increased to five and that the overlap of the parallel data transfer circuit TRC is increased to four pixels. The selector SEL of the parallel data transfer circuit TRC is designed as a 5:1 selector for selecting P bit data from 5P bit data, and the twenty-five coefficients required for the 5 × 5 filter can be stored by increasing the capacity of the data memory. In the present embodiment, one processing circuit can be supplied with the data from the sense amplifier corresponding to the five pixels, and the adjacent processing circuits share the data lines for four pixels of the data line group. As a result, the processing operations for the 5 × 5 filter can be carried out in parallel while the word lines of the two-dimensional memory array are selected sequentially as in the embodiment of Fig. 1. Incidentally, in the present embodiment, not only the operations for a 5 × 5 filter can be carried out, but also a 4 × 4 filter can be easily constructed by using four of the five word lines and four of the five sets of connecting lines connected to one transfer circuit TRC. Similarly, it is possible to perform the processing operations for a 3 · 3 filter or a 2 · 2 filter.

In the embodiments of Figs. 1 and 3, one processing circuit can be provided for P data lines when the value of the pixel is expressed by P bits. For example, when the pixel value is expressed with an accuracy of 8 bits, the processing circuits can be arranged at a pitch of eight data lines. However, it may be difficult to arrange the processing circuits in this way when the processing circuits are large or when the data lines of the two-dimensional memory array are closely spaced.

In this case, the embodiment shown in Fig. 4 can be used. Fig. 4 shows an embodiment for increasing the layout pitch of the processing circuits of Fig. 1 for calculating the 3 x 3 filter. In the present embodiment, the input images of one line input to the serial access memory SAM1 are transferred to a register RG1 having a capacity of three lines through the parallel data transfer circuit TRC1 composed of distributors DIS. As a result, the layout pitch of the processing circuit is three times as large as that of the embodiment of Fig. 1. In the embodiment of Fig. 1, one processing circuit can transfer the data from the data lines of three pixels, and two transfer paths in adjacent processing circuits overlap. In the present embodiment, on the other hand, one processing circuit can transfer data from the data lines of nine pixels, and the parallel data transfer circuit is constructed so that the adjacent processing circuits share six data lines. The operation of the present embodiment will be described below with reference to Fig. 4.

First, when the input images of the first line are stored in the serial access memory SAM1, the switches L in all the distributors DIS are turned ON to write the input images in parallel to the register RG1. Then, when the input images of the second line are stored in the serial access memory SAM1, the switches C in all the distributors DIS are turned ON to write these input images in parallel to the register RG1. Then, when the input images of the third line are stored in the serial access memory SAM1, the switches C in all the distributors DIS are turned ON to write these input images in parallel to the register RG1. The images of the successive first, second and third lines are thus written in the register RG1 and transferred in parallel from the register RG1 to the register RG2 via the data line group DG. Then, in the register RG2 prepares the pixels of the input images for the three lines required to prepare the output images of the second line. These data are transferred to the processing circuit through the parallel data transfer circuit TRC2 so that the values of the pixels of the second line of the output images are determined. The transfer and processing operations on the data are otherwise carried out while the input images of the fourth line are being written into the serial access memory SAM1. When the calculations of the pixel values for the second line of the output images are completed so that the input images of the fourth line can be written into the serial access memory SAM1, the switch L of the distributor DIS is turned ON to overwrite one-third of the contents of the register RG1. Since at this time the images of the second, third and fourth lines of the input images are prepared in the register RG1, they are transferred in parallel from the register RG1 to the register RG2 to carry out the processing operations for the output images of the third line. If these operations are carried out each time the input images for one line are stored in the serial access memory SAM1, the processing operations for the 3 × 3 filter can be continuously carried out in parallel. In these operations, how the processing operations are carried out by passing the data from the register RG2 to the processing circuits will be described with reference to Figs. 5 and 6.

5A and 5B show an example of the structure of the parallel data transmission circuit TRC2 for the embodiment of Fig. 4. As shown in Fig. 5A, the selectors SEL of the parallel data transmission circuit TRC2 are arranged in two layers, and three control signals φLi, φC1 and φRi are respectively supplied to them. Each selector consists of three switches L, C and R as shown on the left side of Fig. 5B. When the switch L is turned ON by the control signal φLi, a left input signal INL is output; when the switch C is turned ON by the control signal φCi, a middle input signal INC is output; and when the switch R is turned ON by the control signal φRi, a right input signal INR is output. These switches can be formed by a parallel connection of MOS transistors as shown on the right side of Fig. 5B. Fig. 5A shows the state in which the input images of the first, second and third lines are transferred to the register RG2. In this state, as stated above, the pixel data for parallel processing of the output images of the second line are to be transferred to the processing circuit. Fig. 6 shows the corresponding temporal output of the control signals. In Fig. 6, the letters φL1, φC1 and φR1 and φL2, φC2 and φR2 are the control signals for the selectors SEL which form the parallel data transfer circuit TRC2. Fig. 6 also shows which pixel data are output at different times to the left four outputs TNO0, TNO1, TNO2 and TNO3 of the parallel data transfer circuit TRC2. As shown in Fig. 5a, the output TNO1 of the parallel data transfer circuit TRC is connected to the processing circuit PE1. From Fig. 6 it can be seen that the pixels F11, F12, F13, F21, F22, - - - and so on and the 3 x 3 pixel data around the pixel F22 are input to the processing circuit PE1. Similarly, the 3 × 3 pixel data around the pixel F23 is input to the processing circuit PE2, and the 3 × 3 pixel data around the pixel F24 is input to the processing circuit PE3. As a result, the output images of the two lines can be processed in parallel by the processing circuits PE1, PE2, PE3, - - -, etc. The processing operations of the output images on the third and subsequent lines can be carried out similarly. The 3 × 3 filter may not be processed at the left end TNO0, so that the output signal is not output by the processing circuit but as it is, as in Fig. 1. According to the embodiment shown and described in Figs. 4, 5 and 6, the layout pitch of the processing circuits is increased, and the two-dimensional filter operations can be carried out in parallel for each line of the output images. Although a 3 × 3 filter is described here, the present invention can be easily extended to the processing operations for a larger filter.

Fig. 7 shows a second embodiment for increasing the layout pitch of the processing circuits compared with the apparatus of Fig. 1 for calculating the 3 × 3 filter. In Fig. 4, the larger layout pitch is achieved by arranging the same number of processing circuits as in the apparatus of Fig. 1 over a layout width three times as large. In the present embodiment, on the contrary, the layout pitch is increased by reducing the number of processing circuits to one third while arranging the processing circuits with the same layout width as in the embodiment of Fig. 1. Figs. 8A and 8B show an example of the structure of the parallel data transfer circuit TRC1 for the embodiment of Fig. 7. Fig. 8A shows the state in which the pixel values F 11 , F 12 , - - - and so on of the first line of the input images are transferred to the sense amplifier SA. The parallel data transmission circuit TRC 1 comprises a kind of 5:1 selectors SEL for selecting P bits from 5P bits each, as shown in Fig. 7. Fig. 8A shows an embodiment in which the selector SEL of Fig. 7 is constructed of a kind of 2:2 selector SEL2-1 for selecting P bits from 2P bits. The Selectors are arranged in three layers, each selector SEL2-1 is supplied with the two control signals φL1 and φRi. The selector SEL2-1 consists of the two switches L and R as shown on the left side of Fig. 8B. The left input signal INL is output when the switch L is turned ON by the control signal φLi, and the right input signal INR is output when the switch R is turned ON by the control signal φRi. These switches can be formed by a parallel connection of MOS transistors as shown on the right side of Fig. 8B.

The operation of the embodiment of Figs. 7 and 8 will now be explained with reference to Fig. 9. In Fig. 9, (φL1, φR1), (φL2, φR2), (φL3, φR3) denote the individual control signals for the selectors SEL of the parallel data transmission circuit TRC1 of Fig. 8. Fig. 9 shows the timing of the selection of the word lines and the mentioned control signals, the pixel data output from the left four outputs TNO0, TNO1, TNO2 and TNO3 of the parallel data transmission circuit TRC1 and the timing of turning the switches L, C and R of the distributors DIS in the parallel data transmission circuit TRC2 to ON. In the present embodiment, since the number of processing circuits is reduced to one third, three consecutive output pixels are processed by one processing circuit. First, the input images of the first row are stored in the serial access memory SAM1 and then transferred to the word line W1 of the two-dimensional memory array MAR. Similarly, the input images of the second and third rows are transferred to the word lines W2 and W3, and then the processing of the output images of the second row is started. The input images of the first row on the word line W1 are read out by the data line group DG, and their pixels F11, F12, F13, - - - and so on are held from the left in the sense amplifier as shown in Fig. 8A. Thereafter, the control signal for the selectors SEL in the parallel data transfer circuit TRC1 is switched as shown in the column for the cycle t1 of Fig. 9. Then, the pixels F11, F14, F17, - - - and so on are transferred to the processing circuits PE1, PE2 and PE3 via the outputs TNO1, TNO2 and TNO3 of the parallel data transfer circuit TRC. The pixels are multiplied by the weighting coefficients read from the data memory in the multipliers MT1, MT2, - - - and so on, and the resulting products are stored in the registers RG1, RG2, - - - and so on. Thereafter, the control signals for the selectors SEL are switched as shown in the column for the cycle t2 in Fig. 9. The pixels F12, F15, F18, - - - and so on are then transferred to the processing circuits PE1, PE2, PE3. These data are multiplied by the weighting coefficients. The products are added to the previous results stored in the registers, and the sum is stored in the registers again. Furthermore, as shown in the column for cycle t3 in Fig. 9, the control signals are switched to transfer the pixels F13, F16, F19, - - - and so on to the processing circuits PE1, PE21, PE3. These data are multiplied and added to the previous results. The results obtained up to this point are written into the serial access memory SAM2 via the switch L of the distributor DIS in the parallel data transfer circuit TRC2 of Fig. 7. The data is intermittently written into the serial access memory SAM2.

Then, while the input pixels of the first line are held in the sense amplifier, the data are transferred as shown in cycles t4 to t6 of Fig. 9, and the processing results are intermittently written into the serial access memory SAM2 by turning on the switch C of the distributor DIS.

Then, while the input pixels of the first line are held in the sense amplifier, the data are transferred as shown in cycles t7 to t9 of Fig. 9, and the processing results are intermittently written into the serial access memory SAM2 by turning on the switch R of the distributor DIS. Thereafter, the word line W2 is selected to hold the input pixels of the second line in the sense amplifier, and corresponding operations are carried out. At this time, at the beginning of cycles t1, t4, and t7, the results obtained using the input pixels of the first line are supplied from the serial access memory SAM2 to the registers RG1, RG2, - - - and so on of Fig. 7, and the newly obtained multiplication results are added to the supplied results. When corresponding operations are carried out when the word line W3 is selected to hold the input pixels of the third line in the sense amplifier, all the values of the pixels of the output images of the second line in the serial access memory SAM2 are determined. If these operations are continued each time the input pixels of one line are stored in the serial access memory SAM1, the processing operations for the 3 x 3 filter can be carried out continuously. As with the embodiment of Fig. 4, the present embodiment can obtain the advantage that the layout pitch of the processing circuits can be made three times as large as in the embodiment of Fig. 1. In the present embodiment, the number of processing circuits is reduced to one third because one processing circuit can carry out the processing operations for three consecutive output pixels. so that this embodiment is suitable for the case where not many processing circuits can be integrated on one chip. To increase the distance between the processing circuits even further, it is sufficient for one processing circuit to process three or more consecutive pixels, which is easy to understand. To this end, as is also easy to understand, the transmission network can be constructed in such a way that the data is transmitted from the number of sense amplifiers to one processing circuit, with two transmission paths of adjacent processing circuits overlapping.

The embodiments described with reference to Fig. 9 include a two-dimensional linear filter. Thanks to these embodiments, the lines or edges in the image can be quickly emphasized or smoothed by changing the sizes and coefficients of the filters. Furthermore, by changing the functions of the processing circuits, specific patterns can be extracted or the processing operations of a non-linear filter such as a median filter can be carried out at high speed. Also, the above embodiments can of course be used to create a cellular automaton or a neural network that is connected only to the neighboring neuron when they process the output signals using the information from neighboring cells distributed in two dimensions. In the illustrations describing the above embodiments, the two-dimensional memory cell array only stores the data of the pixels for the number of rows required for the processing operations. However, by increasing the number of word lines of the two-dimensional memory array, the pixel data for more lines can be easily stored. For example, when storing the data for an entire image, the embodiments can be used as so-called "image memories". In this case, only a part of the two-dimensional memory array is processed, while the remaining data is serially read out and output as it is, so that only a part of the screen is processed by the filter or the like. The processed area can be easily moved back and forth by appropriately controlling the word lines.

An embodiment for detecting a motion vector in which the present invention is applied to something other than a filter will now be described by way of example. Detecting a motion vector is useful in compressing/decompressing a moving digital image. However, because of the large amount of data to be processed, an apparatus for quickly detecting the motion vector is desired. As is well known, the motion vector detected by dividing the input image into blocks of a number of pixels, each block then being compared with a block arranged to correspond to a reference image and a number of blocks in the vicinity of that reference block to determine the block with the smallest distance and to determine the coordinate difference from the block of the input image.

10 and 11 show an embodiment of an apparatus for determining the motion vector of a moving picture by means of the present invention. In order to simplify the description, it is assumed hereinafter that the block has a size of 3 x 3 pixels and the search has a scope of two pixels in the vertical and horizontal directions. However, the present invention is not limited to these numerical values, but can be easily extended. Fig. 11 shows the structure for a minimum distance processing unit for determining the minimum of the inter-block distance determined as in Fig. 10 and for outputting the motion vector. The structure and operation of the present embodiment will now be described.

In the device of Fig. 10, the pixel REFx'y' of a reference image used for comparison with the pixel Fxy of the input image is input one by one in real time to the serial access memories SAM1 and SAM2. After this input to the serial access memories, the pixel is transferred to two-dimensional buffer arrays BAF2 and BAF1 for three lines and also to the two-dimensional memory arrays MAR2 and MAR1 for comparison. The two-dimensional memory array MAR2 can store the input images of three lines so that a block of size 3 x 3 pixels can be stored in one column. On the other hand, the two-dimensional memory array MAR1 can store the input images of seven lines comprising two vertical lines in addition to the position corresponding to the block of input images in the memory array MAR2. The input images input to the serial access memory SAM2 are input with a delay of two lines from the reference image input to the serial access memory SAM1, so that the data is transferred from the serial access memories SAM1 and SAM2 to the buffer arrays BAF1 and BAF2 and the memory arrays MAR1 and MAR2 each time the data of one line is stored. The image in the memory array MAR1 comprises two vertical lines in addition to the position corresponding to the block of the input image in the memory array MAR2. The two-dimensional buffer arrays BAF2 and BAF1 for three lines are provided for temporarily storing the data for determining the motion vector of the block of the next column, while the motion vector for the block of a column. At the end of each processing operation for the motion vector of the block of a column, the data of these two-dimensional buffer arrays BAF1 and BAF2 are transferred to the memory arrays MAR1 and MAR2 so that the motion vector of the block of the next column can be worked out. As mentioned above, in order to determine the motion vector, it is necessary to determine the distance between the block of the input image and the block of the reference image whose position is shifted in the vertical and horizontal directions. The interblock distance can be determined by summing the difference between the values of the pixels for one block and the pixels for another block. In the embodiment of Fig. 10, the distances between the pixels read out from the memory arrays MAR2 and MAR1 are calculated in parallel by the processing circuits PE1, - - - and PEn. If the control signals φL, φC and φR for the parallel data transfer circuit TRC2 are switched each time the word lines of the memory array MAR2 are selected in succession, it is possible to transfer the pixels of different blocks for the processing circuits. On the other hand, the memory array MAR1 contains the data of the reference image and another two vertical lines in addition to the position corresponding to the block of the input image in the memory array MAR2. Therefore, by switching the word lines, the y-coordinate of the pixels to be transferred can be changed within the two vertical pixels in addition to the position corresponding to the block of the input image. Furthermore, by switching the control signals for the parallel data transfer circuit TRC1, the pixels which are shifted horizontally by two pixels in the x-direction within the range of the total of seven pixels in addition to the position corresponding to the block of the input image are transferred to the individual processing circuits. As a result, the coordinates of the block of the reference image to be input to the processing circuits are shifted within the range of the two pixels with respect to the input image in the x and y directions. The signal lines of the parallel data transmission circuit TRC1 require an overlap of four lines, but the signal lines of the output TN1 do not require an overlap.

The distance between the block of the input image and the block of the reference image is determined in the following manner. First, the shift of the coordinates is fixed, and the pixels of the block of the input image and the block of the reference image are transferred to the individual processing circuits PE1, - - - PEn. The distances between the pixels determined by the processing circuits are transferred to accumulators ACC1, - - - ACCn so that the values thereof are stored for a block. The distances between the blocks thus determined are transferred to minimum distance processing units MIN1, - - - MINn. These minimum distance processing units determine the coordinate shift which minimizes the distances between the blocks. The structure of these minimum distance processing units is shown in Fig. 11. The minimum distance processing unit MINi is constructed as shown in Fig. 11 to include a comparator COM, registers REG1 and REG2, and switches SWB1 and SWB2. The inter-block distance BLDi(Δx, Δy) for predetermined displacements Δx and Δy is input to the comparator COM after determination. The comparator COM compares the newly determined interblock distance BLDi(Δx, Δy) with the interblock distance (Δx', Δy') of other displacements Δx' and Δy' already determined and stored in the register REG1. If the distance BLDi(Δx, Δy) is found to be smaller, the switch SWB1 is turned ON so that the contents of the register REG1 are updated with the value BLDi(Δx, Δy). The register REG2 stores the displacement (Δx', Δy'), which is also updated with (Δx, Δy) when the switch SWB2 is turned ON. On the other hand, if the distance BLDi(Δx, Δy) is larger, the switches SWB1 and SWB2 are not turned ON, so that the contents of the registers are not updated. By performing these operations for all shifts, the register REG2 determines the shift for the minimum interblock distance, ie, the motion vector MC. In Fig. 10, the motion vectors of the blocks of a column are determined in parallel, transferred to the serial access memory SAM3, and sequentially output from the chip.

As described, in the embodiments of Figs. 10 and 11, it is possible to determine the motion vectors for the blocks of one column in parallel for an image that is input in real time. The motion picture compression/decompression system using the motion vector can therefore perform high-speed processing operations by incorporating the semiconductor integrated circuit of the present invention into the system. In the structure of Fig. 10, the pitch of the processing circuits can be increased by the methods of Figs. 4 and 7.

Embodiments of the present invention have been described using two-dimensional memory arrays whose word lines can store the pixel data of one or more rows. However, if the word lines are excessively long, the line capacitance and resistance increase to such an extent that it may be difficult to drive the lines quickly. In this case, the arrays can be divided. In a simple division, the pixels required for the processing circuitry at the end of a subarray are in the adjacent subarray, so that a special access path is required. To avoid this, the pixel data at the end of the subarrays may be duplicated in the adjacent subarrays. In the illustrations for explaining the embodiments, the detailed structure of the two-dimensional memory arrays and the method for generating the control signals are not shown in detail, but can be easily constructed using the technique used in ordinary LSI circuits. For example, the two-dimensional memory array can be constructed by a DRAM array of individual transistor cells. In this case, since the two-dimensional memory array can be highly integrated, more processing circuits can be accommodated on the same chip than with an SRAM array or the like. As a result, the processing operation becomes faster. As described, most embodiments of the present invention use the information of the memory array only for a short time. Thus, even with a DRAM array, automatic refreshing is performed during the processing operation. The refreshing therefore does not need to be carried out by interrupting the processing operation.

In the semiconductor integrated circuit according to the present invention, the processing operations on two-dimensional data such as a two-dimensional spatial filter, a convolution operation or the operations for searching the motion vector between images can be carried out in parallel. These processing operations can therefore be carried out in real time at a high speed.

Claims (21)

1. Integrated semiconductor circuit, with a memory cell array (MAR) having a number of data lines (DE), a number of word lines (W1 to W3) intersecting said data lines (DE), and a number of memory cells arranged at desired interfaces between the data lines (DE) and the word lines (W1 to W3); a parallel data transmission circuit (TRC) for parallel transmission of a number of data from the number of data lines (DE); and with a number of processing circuits (PE1 to PEn) for receiving the number of data transmitted by the parallel data transmission circuit (TRC) as input signals, wherein the parallel data transmission circuit (TRC) is arranged to connect the data lines (DG) to the processing circuits (PE1 to PEn) in a sequence that includes: i) a first connection arrangement in which each data line is connected to a first corresponding processing circuit, and ii) a second connection arrangement in which each data line is connected to a second corresponding processing circuit; wherein the first and second corresponding processing circuits for the data lines are adjacent and the respective lines to which each processing circuit in the first and second connection arrangements is connected are adjacent to one another. 2. A semiconductor integrated circuit according to claim 1, wherein each of the plurality of processing circuits (PE1 to PEn) performs processing operations using a number of data read out by selecting two or more of the plurality of word lines (W1 to W3) to one of the plurality of data lines (DG). 3. Integrated semiconductor circuit according to claim 1 or claim 2, further comprising a first memory (SAM 1) with serial access for storing externally input serial data and for parallel output of this serial data to the number of data lines (DG); and a second serial access memory for converting the output data of the number of processing circuits (PE1 to PEn) into serial data and for outputting this serial data to the outside. 4. A semiconductor integrated circuit according to any one of claims 1 to 3, wherein each of the plurality of processing circuits (PE1 to PEn) performs processing operations using the number of data of the memory cell array (MAR) and a predetermined constant. 5. Integrated semiconductor circuit, with a memory cell array (MAR) having a number of data line groups (DG), a number of word lines (W1 to W3) intersecting the data line groups (DG), and a number of memory cells arranged at desired interfaces between the data line groups (DG) and the word lines (W1 to W3); a parallel data transmission circuit (TRC) for parallel transmission of a number of data groups from the number of data line groups (DG); and a number of processing circuits (PE1 to PEn) for receiving the number of data groups transmitted by the parallel data transmission circuit (TRC) as input signals; wherein the parallel data transmission circuit (TRC) is arranged to connect the data line groups (DG) to the processing circuits (PE1 to PEn) in a sequence which includes: i) a first connection arrangement in which each data line group is connected to a first corresponding processing circuit; and ii) a second connection arrangement in which each data line group is connected to a second corresponding processing circuit; wherein the first and second corresponding processing circuits for each data line group are adjacent, and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to one another. 6. A semiconductor integrated circuit according to claim 5, wherein each of said plurality of processing circuits (PE1 to PEn) is formed using a plurality of data groups formed by selecting two or more of said plurality of word lines (W1 to W3) to one of the number of data line groups (DG), executes a processing operation. 7. Integrated semiconductor circuit according to claim 5 or 6, further comprising a first memory (SAM 1) with serial access for storing externally input serial data and for parallel output of this serial data to a number of data line groups (DG); and a second memory (SAM 2) with serial access for converting the output data of the number of processing circuits into serial data and for outputting this serial data to the outside. 8. Integrated semiconductor circuit according to one of claims 5 to 7, wherein each of the plurality of processing circuits (PE1 to PEn) performs processing operations using the number of data groups of the memory cell array (MAR) and a predetermined constant. 9. Integrated semiconductor circuit, with a first and a second memory cell array (MAR 1 and MAR 2), each having a number of data lines, a number of word lines intersecting the data lines, and a number of memory cells arranged at desired interfaces between the data lines and the word lines (W1 to W3); a first parallel data transfer circuit (TRC 1) for parallel transfer of a number of first data from the number of data lines of the first memory cell array (MAR 1); a second parallel data transfer circuit (TRC 2) for parallel transfer of a number of second data from the number of data lines of the second memory cell array (MAR 2); and a plurality of processing circuits (PE1 to PEn) for receiving the first and second plurality of data from the first and second parallel data transfer circuits (TRC 1 and TRC 2); wherein the first parallel data transfer circuit (TRC 1) is arranged to connect the data lines of the first memory cell array (MAR 1) to the processing circuits (PE1 to PEn) in a sequence that includes: i) a first connection arrangement in which each data line of the first memory cell array (MAR 1) is connected to a corresponding processing circuit, and ii) a second connection arrangement in which each data line of the first memory cell array (MAR 1) is connected to another corresponding processing circuit; wherein the one and the other corresponding processing circuit for each data line of the first memory cell array (MAR 1) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other; and wherein the second parallel data transfer circuit (TRC 2) is arranged to connect the data lines of the second memory cell array (MAR 2) to the processing circuits (PE1 to PEn) in a sequence which includes: i) a third connection arrangement in which each data line of the second memory cell array (MAR 2) is connected to a corresponding processing circuit; and ii) a fourth connection arrangement in which each data line of the second memory cell array (MAR 2) is connected to another corresponding processing circuit; wherein the one and the other corresponding processing circuits for each data line of the second memory cell array (MAR 2) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other. 10. Integrated semiconductor circuit, with a first and a second memory cell array (MAR 1 and MAR 2), each having a number of data line groups, a number of word lines intersecting the data line groups, and a number of memory cells arranged at desired intersections between the data line groups and the word lines; a first parallel data transfer circuit (TRC 1) for parallel transfer of a number of first data groups from the number of data line groups of the first memory cell array (MAR 1); a second parallel data transfer circuit (TRC 2) for parallel transfer of a number of second data groups from the number of data line groups of the second memory cell array (MAR 2); and a number of processing circuits (PE1 to PEn) for receiving the number of first and second data groups from the first and second parallel data transfer circuits (TRC 1 and TRC 2); wherein the first parallel data transfer circuit (TRC 1) is arranged to connect the data line groups of the first memory cell array (MAR 1) to the processing circuits in a sequence which includes: i) a first connection arrangement in which each data line group of the first memory cell array (MAR 1) is connected to a corresponding processing circuit; and ii) a second connection arrangement in which each data line group of the first memory cell array (MAR 1) is connected to another corresponding processing circuit; wherein the one and the other corresponding processing circuits for each data line group of the first memory cell array (MAR 1) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other; and wherein the second parallel data transfer circuit (TRC 2) is arranged to connect the data line groups of the second memory cell array (MAR 2) to the processing circuits in a sequence which includes: i) a third connection arrangement in which each data line of the second memory cell array (MAR 2) is connected to a corresponding processing circuit; and ii) a fourth connection arrangement in which each data line group of the second memory cell array (MAR 2) is connected to another corresponding processing circuit; wherein the one and the other corresponding processing circuits for each data line group of the second memory cell array (MAR 2) are adjacent and the respective lines to which each processing circuit is connected in the first and second connection arrangements are adjacent to each other. 11. A semiconductor integrated circuit according to claim 3, wherein the serial data input into the first serial access memory (SAM 1) is pixel data of an image. 12. Integrated semiconductor circuit according to claim 11, further comprising a data memory (DM) for storing filter coefficients; wherein each of the plurality of processing circuits (PE1 to PEn) performs a filter processing operation of the image based on the pixel data and the filter coefficients. 13. A semiconductor integrated circuit according to claim 12, wherein the filter processing operation uses two-dimensional data stored in the first memory cell array (MAR 1). 14. Integrated semiconductor circuit according to claim 9, further comprising a first serial access memory for storing externally input serial data and for outputting this serial data in parallel to the number of data lines of the first memory cell array; a second serial access memory for storing externally input serial data and for outputting this serial data in parallel to the number of data lines of the second memory cell array; and a third serial access memory for converting the output data of the number of processing circuits into serial data and for outputting this serial data to the outside. 15. A semiconductor integrated circuit according to claim 14, wherein the serial data input to the first serial access memory is pixel data of a reference image and the serial data input to the second serial access memory is pixel data of an input image. 16. Integrated semiconductor circuit according to claim 15, further comprising a third and a fourth memory cell array, each having a number of data lines, a number of word lines intersecting the data lines, and a number of memory cells arranged at desired interfaces between the data lines and the word lines; wherein the data lines of the third memory cell array are each coupled to the data lines of the first memory cell array; wherein the data lines of the fourth memory cell array are each coupled to the data lines of the second memory cell array; and wherein the plurality of processing circuits performs a processing operation while the third and fourth memory cell arrays store data for the following operation. 17. A semiconductor integrated circuit according to claim 16, wherein the plurality of processing circuits (PE1 to PEn) process the motion vector of a moving image using the pixel data of an input image and a reference image. 18. Integrated semiconductor circuit according to claim 10, further comprising a first serial access memory for storing externally input serial data and for outputting this serial data in parallel to the number of data line groups of the first memory cell array; a second serial access memory for storing externally input serial data and for outputting this serial data in parallel to the number of data line groups of the second memory cell array; and a third serial access memory for converting the output data of the number of processing circuits into serial data and for outputting this serial data to the outside. 19. A semiconductor integrated circuit according to claim 18, wherein the serial data input to the first serial access memory is pixel data of a reference image and the serial data input to the second serial access memory is pixel data of an input image. 20. Integrated semiconductor circuit according to claim 19, further comprising a third and a fourth memory cell array, each having a number of data line groups, a number of word lines intersecting the data line groups, and a number of memory cells arranged at desired interfaces between the data line groups and the word lines, wherein the data line groups of the third memory cell array are respectively coupled to the data line groups of the first memory cell array; wherein the data line groups of the fourth memory cell array are each coupled to the data line groups of the second memory cell array; and wherein the plurality of processing circuits performs a processing operation while the third and fourth memory cell arrays store data for the following operation. 21. A semiconductor integrated circuit according to claim 20, wherein the plurality of processing circuits obtain the motion vector of a moving image using the pixel data of an input image and a reference image.