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DE4238113A1 - Semiconductor chip mounting arrangement for fragile semiconductor element - includes silicon rubber encapsulation on all sides of chip within plastics package - Google Patents

Semiconductor chip mounting arrangement for fragile semiconductor element - includes silicon rubber encapsulation on all sides of chip within plastics package

Info

Publication number
DE4238113A1
DE4238113A1 DE4238113A DE4238113A DE4238113A1 DE 4238113 A1 DE4238113 A1 DE 4238113A1 DE 4238113 A DE4238113 A DE 4238113A DE 4238113 A DE4238113 A DE 4238113A DE 4238113 A1 DE4238113 A1 DE 4238113A1
Authority
DE
Germany
Prior art keywords
chip
silicon rubber
semiconductor chip
sides
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE4238113A
Other languages
German (de)
Inventor
Winfried Seiler
Bernhard Gutsche
Juergen Ruschen
Klaus Ehrhardt
Joachim Mitzner
Hartmut Grudzinski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SMI SYSTEM MICROELECTRONIC INNOVATION GMBH, 15236
Original Assignee
MIKROELEKTRONIK und TECHNOLOGI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MIKROELEKTRONIK und TECHNOLOGI filed Critical MIKROELEKTRONIK und TECHNOLOGI
Priority to DE4238113A priority Critical patent/DE4238113A1/en
Publication of DE4238113A1 publication Critical patent/DE4238113A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L19/00—Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
    • G01L19/14—Housings
    • G01L19/147—Details about the mounting of the sensor to support or covering means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor chip (6) which is within a plastics package and an elastic material (3,5) is used to encase the semiconductor chip on all sides. Pref. the semiconductor chip is attached to a carrier strip (2) via a silicon rubber chip adhesive (3), which extends around the chip side edges. The bonding wire connections are provided before the top surface of the coated with a silicon rubber (6) which flows around the chip edges. ADVANTAGE - Tension-free assembly allows use of relatively cheap plastics housing.

Description

Die Erfindung betrifft eine Anordnung zur spannungsfreien Chip­ montage von thermo-mechanisch sensiblen Halbleiterchips insbe­ sondere im Plastgehäuse.The invention relates to an arrangement for voltage-free chip assembly of thermo-mechanically sensitive semiconductor chips especially especially in the plastic case.

Dabei treten aufgrund der unterschiedlichen thermischen Aus­ dehnungskoeffizienten der einzelnen Montagekomponenten elek­ trische Instabilitäten auf, was speziell unter Prüfbedingungen beobachtet wird, da hier elektrische, thermische und mechanische Belastungen am Chip erfolgen.Due to the different thermal outputs expansion coefficients of the individual assembly components elec trical instabilities, especially under test conditions is observed because here electrical, thermal and mechanical There are loads on the chip.

Bekannt ist die Herstellung von drucksensiblen Halbleiterbauele­ menten im Hohlgehäuse wie CERDIP oder im Metallgehäuse, die aber eine sehr kostenintensive Montage erfordern. Auch die üblichen Montagetechnologien wie Chipbefestigung durch Weichlöten, mit Epoxidklebstoffen oder eutektischem Löten und einer zusätzlichen Chipabdeckung mit Silikonkautschuk vor der Plastumhüllung bieten keine Lösung für die Herstellung von thermo-mechanisch sensiblen Halbleiterbauelementen mit konstanten elektrischen Parametern im Temperaturbereich und bei Temperaturwechselbelastungen.The production of pressure-sensitive semiconductor components is known elements in a hollow housing such as CERDIP or in a metal housing, but they do require a very expensive assembly. Even the usual ones Assembly technologies such as chip mounting by soft soldering, with Epoxy adhesives or eutectic soldering and an additional Provide chip cover with silicone rubber before the plastic encapsulation no solution for the production of thermo-mechanically sensitive Semiconductor components with constant electrical parameters in the Temperature range and in case of temperature changes.

Solche Lösungen sind beispielsweise aus der DD 1 59 484 oder der DE 40 41 347 bekannt.Such solutions are for example from DD 1 59 484 or DE 40 41 347 known.

In der DD 1 59 484 wird zwischen dem Halbleiterchip und dem Plast­ material (Gehäuse) eine Pufferzone aus elastischem Material an­ geordnet. Diese Pufferzone soll die mechanischen Spannungen auf­ nehmen, indem das Chip nach dem Chip- und Drahtbonden allseitig von einem elastischen Material umhüllt wird. Dabei ist aller­ dings die allseitige Umhüllung nur auf die Grenzfläche zwischen Plastmaterial (zum Verschließen) und Halbleiterchip begrenzt.In DD 1 59 484 between the semiconductor chip and the plastic material (housing) to a buffer zone made of elastic material orderly. This buffer zone is intended to relieve the mechanical stresses take out the chip on all sides after chip and wire bonding is covered by an elastic material. Everything is there However, the all-round wrapping only on the interface between plastic material (for sealing) and semiconductor chip limited.

Nach der DE 40 41 347 ist ein Verfahren bekannt, wonach die Zu­ verlässigkeit von integrierten Schaltkreisen in Kunststoffge­ häusen dadurch erreicht werden soll, daß vor dem Umpressen der Chips deren Oberseite und die Schmalseiten einschließlich der dazugehörigen Kanten mit einer wenigstens auf der Chipoberseite gleichmäßig dicken, kompressiblen Kunststoffschicht (Polyimid) versehen wird. Die Gleichmäßigkeit der Schicht wird durch senk­ recht zur Oberfläche der Chips einwirkende Zentrifugalkräfte erreicht, wobei die gleichmäßige Verteilung dadurch erfolgt, daß eine Vielzahl von auf einem Streifen aus Blech aufgebrachten Chips in eine Achse parallel zur Längsachse des Streifens rotie­ ren.According to DE 40 41 347 a method is known, according to which the Zu reliability of integrated circuits in plastic houses should be achieved in that before pressing the Chips whose top and the narrow sides including the associated edges with at least on the chip top uniformly thick, compressible plastic layer (polyimide)  is provided. The uniformity of the layer is lowered centrifugal forces acting right to the surface of the chips achieved, the uniform distribution takes place in that a variety of applied on a strip of sheet metal Rotate chips in an axis parallel to the longitudinal axis of the strip ren.

Weder bei der Anordnung nach DD 1 59 484 noch bei dem Verfahren nach DE 40 41 347 wird die Chipverspannung, verursacht durch die Montage der Chips auf dem Chipträger mittels eutektischem Bon­ den oder Kleben mit bekannten Chipkleber vermieden. Ohne Schaf­ fung einer Pufferzone zwischen Chipträger und Halbleiterchip treten mechanische Verspannungen aufgrund der verschiedenen thermischen Ausdehnungskoeffizienten der Materialien Silizium, Kleber und Chipträger auf. Ausgehend von diesem Sachverhalt ist selbst die Montage mittels eutektischem Bonden und Kleben im Keramikgehäuse ohne metallischen Trägerstreifen nicht ohne Chip­ verspannung zu realisieren.Neither in the arrangement according to DD 1 59 484 nor in the method according to DE 40 41 347, the chip tension is caused by the Assembly of the chips on the chip carrier using a eutectic receipt avoided or sticking with known chip adhesive. Without sheep a buffer zone between the chip carrier and the semiconductor chip occur mechanical tension due to the different thermal expansion coefficient of silicon materials, Glue and chip carrier on. Based on this fact is even the assembly by means of eutectic bonding and gluing in Ceramic housing without a metal carrier strip, not without a chip to realize tension.

Die erfindungsgemäße Lösung in allen genannten Montagevarianten ermöglicht erst die vollständige spannungsfreie Montage von Halbleiterchips und damit eine hohe Stabilität elektrischer Parameter im vorgesehenen Temperaturbereich.The solution according to the invention in all the assembly variants mentioned enables the completely tension-free assembly of Semiconductor chips and thus a high stability of electrical Parameters in the intended temperature range.

Der im Patentanspruch 1 angegebenen Erfindung liegt das Problem zugrunde, bei der Montage von thermo-mechanisch sensiblen Halb­ leiterchips insbesondere im Plastgehäuse konstante elektrische Parameter auch nach thermischen Wechselbelastungen zu gewähr­ leisten.The invention specified in claim 1 is the problem the basis for the assembly of thermo-mechanically sensitive half conductor chips, especially in the plastic housing, constant electrical Ensure parameters also after thermal alternating loads Afford.

Dieses Problem wird durch die im Patentanspruch 1 angeführten Merkmale gelöst.This problem is solved by those mentioned in claim 1 Features resolved.

Die mit der Erfindung erzielten Vorteile bestehen insbesondere darin, daß eine mechanisch spannungsfreie Montage der Halblei­ terchips im kostengünstigerem Plastgehäuse erfolgen kann. The advantages achieved with the invention are in particular in that a mechanically stress-free assembly of the half lead terchips can be done in a cheaper plastic case.  

Eine vorteilhafte Ausgestaltung der Erfindung ist im Patentan­ spruch 2 angegeben. Dieser ermöglicht eine problemlose Umhül­ lung des Halbleiterchips von einem elastischen Material, das gleichzeitig zur Chipbefestigung auf dem Chipträger genutzt wird.An advantageous embodiment of the invention is in the patent pronounced 2. This enables easy wrapping development of the semiconductor chip from an elastic material, the used at the same time for chip attachment on the chip carrier becomes.

Ein Ausführungsbeispiel der Erfindung ist in der Zeichnung dar­ gestellt und wird nachfolgend näher beschrieben.An embodiment of the invention is shown in the drawing and is described in more detail below.

Die Fig. 1 zeigt in schematischer Darstellung einen Schnitt durch ein DIL-Plastgehäuse mit der erfindungsgemäßen vollstän­ digen Umhüllung eines Halbleiterchips 6 aus Silikonkautschuk 3, 5. Fig. 1 shows a schematic representation of a section through a DIL plastic housing with the inventive complete coating of a semiconductor chip 6 made of silicone rubber 3 , 5th

Auf der Mittelinsel des Trägerstreifens 2 ist ein Halbleiter­ chip 6 mit Silikonkautschuk 3 als Chipkleber befestigt, wobei gleichzeitig eine Benetzung der Chipkanten mit Silikonkautschuk, wie Fig. 1 zeigt, erfolgt. Das Halbleiterchip 6 ist über Bond­ drähte 4 mit den inneren Trägerstreifenenden des Trägerstreifens 2 verbunden. Nach der Ausführung der Bonddrähte 4 erfolgt das Auftragen von Silikonkautschuk 5 auf die Halbleiterchipober­ fläche mit Fließverhalten desselben über die Chipkanten, so daß dieser sich mit dem Silikonkautschuk 3 verbindet. Eine an­ schließende Aushärtung des Silikonkautschuks sichert dessen elastische Eigenschaften. Die Ausbildung des Plastgehäuses 1 erfolgt in bekannter Weise, indem das Plastmaterial in eine entsprechende Form gespritzt wird, in die obengenannter Träger­ streifen 2 mit einer vollständigen Umhüllung des Halbleiterchips 6 mittels Silikonkautschuk 3, 5 eingelegt ist.On the central island of the carrier strip 2 , a semiconductor chip 6 is fastened with silicone rubber 3 as a chip adhesive, wherein the chip edges are simultaneously wetted with silicone rubber, as shown in FIG. 1. The semiconductor chip 6 is connected via bonding wires 4 to the inner carrier strip ends of the carrier strip 2 . After the execution of the bonding wires 4 , the application of silicone rubber 5 to the semiconductor chip surface with flow behavior of the same takes place over the chip edges, so that this connects with the silicone rubber 3 . Subsequent curing of the silicone rubber ensures its elastic properties. The plastic housing 1 is formed in a known manner by injecting the plastic material into an appropriate shape, into which the above-mentioned carrier strips 2 are inserted with a complete covering of the semiconductor chip 6 by means of silicone rubber 3 , 5 .

Claims (2)

1. Anordnung zur spannungsfreien Chipmontage für thermisch- mechanisch sensible Halbleiterchips insbesondere im Plastge­ häuse, dadurch gekennzeichnet, daß sie zusätzlich allseitig mit einem elastischen Material (3) (5) umgeben sind.1. Arrangement for voltage-free chip assembly for thermally-mechanically sensitive semiconductor chips, in particular in plastic housing, characterized in that they are additionally surrounded on all sides with an elastic material ( 3 ) ( 5 ). 2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß die allseitige Umhüllung (3) (5) dadurch erreicht wird, daß die Chipbefestigung (3) auf dem Chipträger (2) mit Silikonkaut­ schuk (3) erfolgt und dieser gleichzeitig das Chip (6) voll­ ständig abdeckt.2. Arrangement according to claim 1, characterized in that the all-round sheath ( 3 ) ( 5 ) is achieved in that the chip attachment ( 3 ) on the chip carrier ( 2 ) with silicone rubber ( 3 ) and the chip ( 6 ) fully covers all the time.
DE4238113A 1992-11-12 1992-11-12 Semiconductor chip mounting arrangement for fragile semiconductor element - includes silicon rubber encapsulation on all sides of chip within plastics package Ceased DE4238113A1 (en)

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DE4238113A DE4238113A1 (en) 1992-11-12 1992-11-12 Semiconductor chip mounting arrangement for fragile semiconductor element - includes silicon rubber encapsulation on all sides of chip within plastics package

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DE4238113A DE4238113A1 (en) 1992-11-12 1992-11-12 Semiconductor chip mounting arrangement for fragile semiconductor element - includes silicon rubber encapsulation on all sides of chip within plastics package

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0882964A1 (en) * 1997-06-06 1998-12-09 Siemens Aktiengesellschaft Semiconductor pressure sensor device and its manufacturing method
EP0882965A1 (en) * 1997-06-06 1998-12-09 Siemens Aktiengesellschaft Semiconductor pressure sensor device and its manufacturing method
WO2006026951A1 (en) * 2004-09-07 2006-03-16 Infineon Technologies Ag Semi-conductor sensor component provided with a cavity housing and sensor chip and method for the production thereof
WO2006105760A1 (en) * 2005-04-04 2006-10-12 Infineon Technologies Ag Plastic housing and semi-conductor component comprising said type of plastic housing in addition to a method for the production thereof
WO2006105759A1 (en) * 2005-04-04 2006-10-12 Infineon Technologies Ag Semi-conductor sensor component with a cavity housing and sensor chip and method for the production thereof
US7964954B2 (en) * 2006-03-13 2011-06-21 Infineon Technologies Ag Integrated circuit having a semiconductor sensor device with embedded column-like spacers
US8264085B2 (en) 2008-05-05 2012-09-11 Infineon Technologies Ag Semiconductor device package interconnections
DE19936610B4 (en) * 1999-01-27 2013-08-01 Mitsubishi Denki K.K. Semiconductor acceleration sensor and method of making the same
DE102011003195B4 (en) 2011-01-26 2019-01-10 Robert Bosch Gmbh Component and method for manufacturing a component
DE102007057441B4 (en) 2007-11-29 2019-07-11 Robert Bosch Gmbh Method for producing a micromechanical component with a volume-elastic medium and micromechanical component

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3148786A1 (en) * 1980-12-10 1982-07-29 Hitachi Microcomputer Engineering Ltd., Tokyo SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION THEREOF
DD159484A1 (en) * 1981-06-03 1983-03-09 Elvira Donner METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS
DE3444699A1 (en) * 1984-12-07 1986-06-19 Telefunken electronic GmbH, 7100 Heilbronn ELECTRICAL POWER COMPONENT
DE3804810A1 (en) * 1987-02-18 1988-09-01 Mitsubishi Electric Corp SEMICONDUCTOR COMPONENT

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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EP0882965A1 (en) * 1997-06-06 1998-12-09 Siemens Aktiengesellschaft Semiconductor pressure sensor device and its manufacturing method
DE19724026A1 (en) * 1997-06-06 1998-12-10 Siemens Ag Pressure sensor component and manufacturing method
DE19724025A1 (en) * 1997-06-06 1998-12-10 Siemens Ag Pressure sensor component and manufacturing method
EP0882964A1 (en) * 1997-06-06 1998-12-09 Siemens Aktiengesellschaft Semiconductor pressure sensor device and its manufacturing method
DE19936610B4 (en) * 1999-01-27 2013-08-01 Mitsubishi Denki K.K. Semiconductor acceleration sensor and method of making the same
WO2006026951A1 (en) * 2004-09-07 2006-03-16 Infineon Technologies Ag Semi-conductor sensor component provided with a cavity housing and sensor chip and method for the production thereof
US7749797B2 (en) 2004-09-07 2010-07-06 Infineon Technologies Ag Semiconductor device having a sensor chip, and method for producing the same
WO2006105759A1 (en) * 2005-04-04 2006-10-12 Infineon Technologies Ag Semi-conductor sensor component with a cavity housing and sensor chip and method for the production thereof
US7464603B2 (en) 2005-04-04 2008-12-16 Infineon Technologies Ag Sensor component with a cavity housing and a sensor chip and method for producing the same
US7919857B2 (en) 2005-04-04 2011-04-05 Infineon Technologies Ag Plastic housing and semiconductor component with said plastic housing
WO2006105760A1 (en) * 2005-04-04 2006-10-12 Infineon Technologies Ag Plastic housing and semi-conductor component comprising said type of plastic housing in addition to a method for the production thereof
US7964954B2 (en) * 2006-03-13 2011-06-21 Infineon Technologies Ag Integrated circuit having a semiconductor sensor device with embedded column-like spacers
DE102007057441B4 (en) 2007-11-29 2019-07-11 Robert Bosch Gmbh Method for producing a micromechanical component with a volume-elastic medium and micromechanical component
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