DE4229837A1 - A SEMICONDUCTOR MEMORY DEVICE WITH A VARIETY OF MICROGRABES AND / OR MICROCYLINDERS WITH MEMORY ELECTRODES - Google Patents

Description

The invention relates to a capacitor with a high storage capacity in a limited Surface is formed on a semiconductor substrate. In particular, the invention relates to a Semiconductor memory cell with one Storage capacitor, the semiconductor memory cell with a transfer transistor on one Semiconductor substrate formed source and Has drain regions, the gate electrode adjacent to the source and drain areas is arranged, and with a storage capacitor, the one storage electrode with a variety of Has micro trenches and / or micro cylinders with are connected to the source region, one dielectric layer covers the storage electrode and a plate electrode the dielectric layer covered.

A dynamic memory with random access (DRAM) has a large number of memory cells, each one a transfer transistor and one Has storage capacitor. Consequently, the grows area occupied by the DRAM with a Increase in the density of the memory cells. There a such an increase in the occupation area a decrease caused in the yield, it is necessary that Storage capacity in a limited, narrow Area by the corresponding memory card is occupied without increasing one  The occupancy area grows accordingly Increase in the density of the memory cells. Around There are a number of requirements to meet Capacitor cell structures have been proposed as a stacked capacitor cell and one Trench capacitor cell. The stacked capacitor is particularly proposed for megabit DRAMs been due to the simplicity of the Manufacturing process and high immunity against errors caused by foreign bodies in the Comparison with the trench capacitor. A way the Meeting the requirements is the surface of the Enlarge storage electrode or the effective Thickness of the dielectric layer of the capacitor diminish and dielectric good substances too use. However, the present invention not to reduce the effective thickness of the dielectric layer or an increase in Dielectric constant directed to one Enlargement of the surface of the storage electrode.

A known technique in which the storage electrode is engraved to enlarge the surface of the storage electrode is disclosed in "Extended Abstracts of the 21st Conference on Solid State Devices and Materials (SSMD)", 1989, pages 137-140. This technique combines the following steps: application of polysilicon to selectively oxidized n-type silicon substrate by chemical vapor deposition at low pressure (LPCVD), doping of the applied polysilicon by phosphorus diffusion with POCL ₃ as a source, application of a mixture of a spin-on glass (SOG) and a resistive layer on the doped polysilicon, heating the mixed layer, selectively etching the SOG in a buffered HF solution, whereby only the resistance particles remain on the polysilicon, dry etching the polysilicon using the dispersed resistance particles as an etching mask, removing the resistance particles and structuring the polysilicon to form it the storage electrode. As a result, by using the resistive particles left on the polysilicon surface as an etching mask, the surface of the storage electrode is increased by forming an engraved storage electrode. Furthermore, the enlargement of the surface of the storage electrode is achieved by controlling the size of the resistance particles and the etching time of the polysilicon. The size of the resistor particles can be controlled by the mixing ratio of resistor material and SOG and the thickness of the mixture applied to the polysilicon. However, since the technique requires the use of uniformly sized particles and the control of the coating thickness of the mixture due to the mixing ratio of the resistive material and SOG, difficulties in repeating the engraving of the storage electrode and increasing the reliability may arise. Another difficulty is that the engraving process for enlarging the surface is complicated.

Another known technique for increasing the Surface of the storage electrode is in IEDM, 1990,  Pages 655-656, on or SSDM, 1990, Pages 872- 876 and SSDM, 1990, pages 869-872, wherein a memory cell a hemispherical Has grain storage electrode. This technique is based on the fact that during the application of polysilicon through LPCVD the polysilicon under a certain Condition an uneven surface with silicon dents or hemispherical grains. Farther this publication discloses such an uneven Surface active in a narrow temperature range (5 ° C) occurs that is adjacent to one Transition temperature of the polysilicon from is non-crystalline to the crystalline state, wherein the surface of the storage electrode doubled is expanded by conventional polysilicon. There this technique is well controllable through use existing facilities within the Temperature range of 5 ° C is that Manufacturing process simple and has one reliable repeatability. However the surface of the storage electrode only on that double a conventional storage electrode enlarged. Hence the application of this technique for storage devices with high density as in DRAM's of 10 or 100 megabits difficult because of one high increase in storage capacity in one confined, narrow area is difficult.

The invention is therefore based on the object Storage capacitor with a high storage capacity to be provided in a limited area.  

Another object of the present invention is a storage capacitor with an enlarged Surface of the storage electrode in a limited Area to form.

Another object of the invention is one Storage capacitor with an enlarged Storage capacity in a limited, small Area through a simple manufacturing process to manufacture.

Finally, it is an object of the invention, one Storage capacitor with high reliability and high storage capacity in a limited, small Area.

Another object of the present invention is a storage capacitor with high storage capacity and reliable repeatability in one to form a limited, small area.

To solve the problem, a capacitor according to the invention a first electrode and one on the dielectric layer formed on the first electrode, the first electrode being formed from polysilicon is and a variety of micro-trenches and / or Has microcylinder in a particular Area of the electrode are formed.

Furthermore, a semiconductor memory cell according to the invention, a transfer transistor and Storage electrode on, wherein the transfer transistor Source and drain areas and one to the source and  Has drain regions adjacent to the gate electrode, and the storage capacitor a first den Source range contacting and from the Gate electrode spaced apart first electrode, one that first electrode covering dielectric layer and a second covering the dielectric layer Has electrode, wherein the first electrode Is polysilicon and a variety of micro-trenches and / or micro-cylinders which in one predetermined area are formed.

Furthermore, according to the invention, a method for Formation of a storage electrode with a variety of micro trenches and / or micro cylinders provided at which grains on a Surface of the storage electrode are formed a masking layer on the sidewalls of the appropriate grains for etching is formed and a anisotropic etching using the Etching mask layer is carried out as a mask.

Furthermore, according to the invention, a capacitor provided that a first in a limited Region of a substrate, one Dielectric formed on the first electrode Layer and one on the dielectric layer formed second electrode, the first Electrode a variety of micro-trenches and / or Contains microcylinders of the line layer, the Conduction layer in the lower area of the micro trenches and / or microcylinder in contact with one Is insulation layer and a thin conductive  Layer the conductive layer inside and outside the micro-trenches and / or micro-cylinders covered.

Furthermore, a semiconductor memory cell according to the invention a transfer transistor and Storage capacitor on, the transfer transistor Source and drain areas of a second Has conductivity type based on a Semiconductor substrate of a first conductivity type are formed, a first conductivity layer adjacent to the source and drain areas and isolated by a gate oxide layer from one Channel area between the source and drain areas is formed and a first insulation layer covers the first conductive layer, the Storage capacitor a second conductive layer which is in contact with the drain region and extends over the first insulation layer, one second insulation layer which is the second conductive Layer covers a field oxide layer on the Substrate formed adjacent to the source region is a first electrode made of a conductive Layer contacted the source area, one predetermined area of the first conductive layer overlaps and above the field oxide layer extends, a dielectric layer the first Electrode covers, and a second electrode dielectric layer covered, the first Electrode a variety of micro-trenches and / or Microcylinders of the conductive layer, which conductive layer in lower sections of the Micro trenches and / or micro cylinders in contact with the Insulation layer, and a thin conductive  Layer the conductive layer inside and outside the micro-trenches and / or micro-cylinders covered.

According to a further aspect of the invention, a Semiconductor memory cell a transfer transistor and a storage capacitor, the Transfer transistor source and drain regions of one second conductivity type, which on a Semiconductor substrate of a first conductivity type are formed, a first to the source and Drain areas adjacent and through a Gate oxide layer isolated from a channel region Line layer between the source and Drain areas is formed, and a Insulation layer which is the first conduction layer covered, the storage capacitor one on the Field oxide layer formed substrate, which is formed adjacent to the source region, a first Electrode from a conductive layer the source area contacted, the first electrode a predetermined Section of the first line layer covered and extends over the field oxide layer, one dielectric layer covers the first electrode, and a second electrode the dielectric layer covered, the first electrode being a plurality of Micro trenches and / or micro cylinders of the Has line layer, these in lower Areas of the micro trenches and / or micro cylinders in Contact with the insulation layer is thin Line layer the line layer inside and Exterior of the micro trenches and / or micro cylinders covered.  

Furthermore, according to the invention, a method for Production of a storage electrode with a Variety of micro trenches and / or micro cylinders provided, with the process steps: formation of grains on a surface of the Storage electrode, forming an etch masking layer on the side walls of the corresponding grains and Perform anisotropic etching by use through etching mask layer as a mask.

Furthermore, according to the invention, a method for Formation of a storage electrode with a variety of micro trenches and / or micro cylinders provided with the procedural steps: Flattening a surface of an insulation layer, on which the storage electrode is formed intended to form grains on a surface of the Storage electrode, forming an etching mask layer Sidewalls of the corresponding grains, performing an anisotropic etching by combining the Etching mask layer as a mask, to screw hole-like To form holes through the storage electrode penetrate to the insulation layer in them to apply, and forming a thin conduction layer of polysilicon covering the inside and outside of the Screw hole-like holes covered.

Furthermore, a method according to the invention for Manufacture of a storage capacitor for use in a semiconductor memory device Use a polysilicon layer with a Variety of hemispherical grains provided with the procedural steps: forming one  Etching mask layer on the surface of the hemispherical grains, structuring the Polysilicon layer, performing an anisotropic Etching by using the etching mask layer as Mask and remove the etch mask layer to form a storage electrode.

According to another aspect of the invention, a Process for forming a first electrode of the Storage electrode in one A semiconductor memory device having the following Method steps provided: Form a Source region contacting polysilicon layer, which have a variety of hemispherical grains has its surface and the second Insulation layer covered, forming one Etching mask layer on the surface of the hemispherical grains, structuring the Polysilicon layer, performing an anisotropic Etching by using the etching mask layer as Mask and remove the etching mask layer.

Advantageous embodiments of the invention in the following with the help of those attached in the drawing Figures explained and described in more detail.

Show it:

Fig. 1 is a plan view of an inventive DRAM memory cell;

Fig. 2 is a cross-sectional view taken along line 2-2 of Fig. 1;

Figs. 3A to 3C manufacturing method of the structure shown in Fig. 2;

FIG. 4A shows an enlarged illustration of an embodiment of a rounded region ( 100 ) of FIG. 3B;

FIG. 4B and 4C are representations of a manufacturing method of a storage capacitor, wherein in Figure 4A illustrated hemispherical grains are formed continuously.

FIG. 5A shows an enlarged illustration of a further embodiment of rounded regions ( 100 ) according to FIG. 3B;

FIG. 5B, and 5C are explanatory views showing a manufacturing method of a storage capacitor in which the hemispherical grains shown in Figure 5A are spaced apart.

Fig. 6 is a plan view of another embodiment of a DRAM memory cell according to the invention;

FIG. 7 shows a cross section along the line 3-3 from FIG. 6;

Figs. 8A to 8D, an exemplary illustration of a manufacturing method of the structure of FIG. 7;

FIG. 9A shows an enlarged illustration of an embodiment with a rounded region ( 500 ) according to FIG. 8D;

Fig. 9B and 9C are explanatory views showing a manufacturing method of a storage electrode, wherein the hemispherical grains shown in Figure 9A are formed continuously.

10A is an enlarged view of a further embodiment of the rounded portion (500) of FIG. 8C.

FIG. 10B and 10C exemplary illustration of a manufacturing method of a storage capacitor in which the hemispherical grains shown in Figure 10A are spaced from each other.

11A to 11D is a further illustration of a manufacturing method of the structure of FIG. 7.

FIG. 12A is an enlarged illustration of a rounded area corresponding to FIG. 11B;

FIG. 12B to 12I are explanatory views showing a manufacturing method of a storage capacitor, wherein the hemispherical in Figure 12A grains are spaced from each other.

FIG. 13A to 13F, further exemplary illustrations of a manufacturing method of a storage capacitor in accordance with the invention;

FIG. 14A to 14H another exemplary illustrations of a manufacturing method of a storage capacitor according to the invention, and

FIG. 15 is a plan view showing the etching pattern used in FIG. 14C.

According to Fig. 1 and 2, a deposited oxide film 12 is formed for determining a memory cell region on a p-type semiconductor substrate 10. The semiconductor substrate 10 may be a p-type trench region. A transfer transistor is formed in an active area. The transistor has an N-type source region 16 adjacent to the field oxide layer 12 , an N-type drain region 20 , which is separated from the source region 16 by an N-channel region 18 , and a gate electrode 24 , which is on a gate oxide layer 22 over the channel region 18 and is formed adjacent to the source and drain regions 16 and 20 . The active region 14 is formed on a main surface of the semiconductor substrate 10 , which is surrounded by the field oxide layer 12 . The gate electrode 24 is connected to a word line 26 . A word line 28 , which is connected to a gate electrode of a transfer transistor in an adjacent active region, is formed on the field oxide layer 12 . The gate electrode 24 is insulated from the word line 28 by an insulation oxide layer 30 . The insulation oxide layer 30 has an opening 32 for exposing a part of the source region 16 . A first electrode of a storage electrode 36 contacts the source region 16 in a source contact region 34 through the opening 32 and defines the storage capacitor region 38 , which extends over the adjacent gate electrode 24 and the word line 28 . According to the present invention, an upper region of the storage electrode 36 has a number of micro-trenches or micro-cylinders to enlarge the surface of the storage electrodes, as will be described in detail below. A dielectric layer 40 is formed on the surface of the storage electrode 36 and a plate electrode layer 42 is formed on the dielectric layer 40 . Accordingly, the storage capacitor 44 has the storage electrode 36 , the dielectric layer 40, and the plate electrode layer 42 . A protective layer 46 is formed on the second electrode of the plate electrode 42 and an exposed area of the insulation oxide layer 30 . The protective layer 46 has an opening 50 , which is arranged adjacent to the drain region 20 of the transfer transistor and which exposes a highly doped N⁺ region 48 which extends over the surface of the semiconductor substrate 10 . A bit line 42 formed from a conductive material contacts the N⁺ region 48 in a bit line contact region 54 through the opening 50 and crosses the word lines 26 , 28 , wherein it extends in a band-like manner over the protective layer 46 . A second protective layer (not shown) covers bit line 52 .

As described above, a DRAM memory cell according to the invention has a transistor and a capacitor. The capacitor is a stacked capacitor with a storage electrode with a multiplicity of micro-trenches on an area of 0.4 × 1.2 μm ² , which is occupied by the storage capacitor region 38 . However, it should be noted that the present invention is not fully reactive in terms of increasing the area of the storage electrode.

Referring to FIG. 3A to 3C, 4A to 4C and 5A to 5C, a manufacturing method of the present invention DRAM memory cell is described in detail. However, since the operation of the DRAM memory cell is well known, the operation is not described in detail.

Referring to FIG. 3A, a pair of transfer transistors is shown on a semiconductor substrate. Although the manufacturing process is well known, it will be briefly described below.

The substrate 10 is a P-type trench with a concentration of 4 to 5 × 10 ¹⁶ atoms / cm ³ , which is in a P-type silicon wafer with a crystal surface (1,0,0) and a concentration of 1 × 10 ¹⁵ atoms / cm ^{3 is} formed. The field oxide layer 12 is formed with a thickness of 3000 Å on a part of the substrate 10 for defining the active region 14 . Then, a gate oxide layer 22 having a thickness of 150 Å is formed on the semiconductor substrate in the active region 14 by known dry oxidation with O ₂ , and a phosphorus-doped polysilicon layer is deposited on the semiconductor substrate 10 to form the gate electrode 24 . After the polysilicon has been applied, the gate electrode 24 or the word line 26 and the word line 28 are structured by conventional photoetching. The structuring method removes the gate oxide layer outside a deeper region of the gate electrode 24 and the word lines 26 and 28 in order to expose the substrate 10 in the active region 14 . Phosphorus ions are then implanted at a dose of 1.6 x 10 ¹³ ions / cm ² below 60 KeV to form the source and drain regions 16 and 20 . After the phosphorus ion implantation, an SiO ₂ isolation layer 30 of 2700 Å thick is evenly deposited by LPCVD at about 820 ° C to isolate the gate electrode 24 , word lines 26 , 28 and the ion implanted source and drain regions 16 and 20 .

According to Fig. 3B, the isolation oxide is formed the opening 32 30 for exposing a part of the surface of the source region 16 through the insulating oxide layer 30 by conventional photo-etching after forming. After removal of the photoresist used to form the opening 32 , a 2500 Å polysilicon layer 56 is formed with a number of hemispherical grains on its surface on the substrate which is in contact with the source contact region 34 through the opening 32 . Such a polysilicon layer having such a surface structure can be applied by LPCVD, using helium-buffered SiH4 (20%) at 550 ° C. under atmospheric pressure from a bar (see IEEE Trans. On Electron Devices, Vol. ED-36, No. 2 , Pages 351 to 353, 1989, or SSDM, pages 863 to 876, 1990). Alternatively, polysilicon layer 56 may be formed by depositing 1000 Å thick polysilicon under a conventional temperature condition (above 600 ° C.) for polysilicon deposition. Then, a polysilicon approximately 1500 Å thick with a number of hemispherical grains is deposited on the surface thereof on the polysilicon surface. The diameter or the height of the hemispherical grains is preferably approximately 0.07 to 0.15 μm. After the polysilicon layer 56 has been formed , arsenic ions are implanted at a dose of 3 × 10 ¹⁵ ions / cm ² below 100 KeV in order to dope the polysilicon layer 56 . Even though the polysilicon layer 56 can be doped with phosphorus impurities, it is advantageous to dope arsenic impurities in order to form a good micro-trench structure on the polysilicon layer 56 . Then, a 300 Å thick SiO ₂ mask layer 58 is deposited on the doped polysilicon layer 56 by known chemical vapor deposition (CVD). A dielectric substance with a high dielectric constant, such as Si ₃ N ₄ or Ta ₂ O _5, can be used as the mask layer 58 . However, when considering the etching process for forming the micro-trenches, it is advantageous to use a dielectric substance with a high selectivity with regard to polysilicon / dielectric substance. After the mask layer 58 has been deposited, a structuring process is carried out in order to determine the storage capacitor area 38 by conventional photoetching. As a result, the patterned polysilicon layer 56 has the micro-trenches shown in FIG. 3B, and the patterned mask layer 58 is formed of SiO ₂ .

An etching method for forming micro-trenches according to the invention is described in detail below with reference to FIGS . 4A to 4C and 5A to 5C. FIGS. 4A and 5A are enlarged views of various embodiments of a rounded portion 100 as described in Fig. 3B.

Fig. 5A shows the arrangement of the grains in the case where the distance S between the hemispherical grains is greater than twice the thickness X of the mask layer 58 made of SiO ₂ (i.e., S 2X), and Fig. 4A shows the arrangement of the Grains in the case where the distance S is zero.

In practice, when the polysilicon layer 56 is deposited by LECVD in a temperature range in which the polysilicon layer 56 changes from the non-crystalline to the crystalline state, the distance S between the grains becomes a mixture of the states S = 0 and S <X. That is, the arrangement of the grains shown in Figs. 4A and 5A can be done at the same time.

Referring to FIG. 4A, a SiO ₂ -Rückätzprozeß to form a side wall in the conventional LDD MOSFET (MOSFET with lightly doped drain) - carried out manufacturing process with respect to the Polysiliziumoxidschicht 58 to adjust the etching in the thickness X (= 300 Å). If the SiO ₂ layer 58 is applied, the result of the etching back process is that the etching mask 52 remains and the upper regions 66 of the grains are exposed in accordance with FIG. 4B, since the SiO ₂ layer has been applied thicker in the valleys between the polysilicon grains is. An anisotropic etch with selectivity of 40 with respect to polysilicon / SiO _{2 is then} carried out to form depressions 0.2 μm thick. Such etching is performed using LAM Co.'s Model No. "Rainbow 4400" at a power of 200 watts, with a hemispherical pressure of 350 millibars and a mixed gas of HBR (hydrogen bromide): Cl ₂ = 40 SGGM: 120 SGGM is used. As a result, depressions in the shape of an upside down T are formed with cylindrical partition walls in the polysilicon shown in FIG. 4C and hemispherical regions 64 corresponding to the exposed grains 66 are formed on the bottom surfaces of the depressions, whereby the surface of the storage electrode 36 continues to grow. After forming such micro-trenches, an Si ₃ H ₄ layer approximately 70 Å thick is formed on the surface of the storage electrode by conventional CVD and a dielectric layer 40 of an NO structure (or an ONO structure if a naturally oxidized SiO ₂ - Layer) is applied from an approximately 20 Å thick SiO ₂ layer, which is obtained by heat oxidation of the surface of the Si ₃ N ₄ layer, is applied. Then, a doped polysilicon layer is formed on the dielectric layer 40 by a known technique, and the doped polysilicon layer is patterned by known photoetching to form the plate electrode 42 .

In the case of FIGS . 5A to 5C, after etching back the mask layer 58, an etching mask layer 62 is formed on the side walls of the corresponding grains 60 according to FIG. 5B, and the upper regions 66 of the grains 60 and the surface regions 68 of the polysilicon layer 56 which are between the grains 60 is deposited, are exposed. Subsequently, etching in the nanometer range is carried out, and as a result, a storage electrode 36 with a plurality of microcylinders 70 as shown in FIG. 5C is formed. In this case too, the hemispherical regions 64 , which correspond to the shape of the exposed upper regions 66 , are formed on the bottom surface of the cylinders 70 . However, the bottom surfaces 80 outside the microcylinder 70 are etched deeper than the hemispherical regions 64 . As a result, the manufacture of the micro-trenches or micro-cylinders can be accomplished by a self-aligned etching process without using a photoresist, thereby simplifying the manufacturing process.

In the case where the structures of Fig. 4A and Fig. 5A are mixed, a number of micro cylinders and of poles having a number of micro-trenches by anisotropic etching can be obtained.

Thereafter, the dielectric layer 40 with NO or ONO structure and the plate electrode 42 are formed on the surface of the storage electrode 36 by a predetermined method.

The method of manufacturing a stacked capacitor with an SiO ₂ etch mask layer 62 on the surface of the storage electrode 36 has been described. However, since the etching mask layer 62 cannot assume the role of the dielectric layer, the etching mask layer 62 is preferably removed. The SiO ₂ etching mask layer 62 can be removed by a buffered HF solution after the anisotropic etching process.

Generally, anisotropic etching leaves sharp edges on the etched edge areas. The sharp edges can also be formed around areas other than the corner areas that have been damaged by anistropic etching. The existence of such sharp edges prevents sufficient reliability of the thin dielectric layer 40 covering the storage electrode 36 , and furthermore the breakdown voltage of the storage capacitor is reduced.

A method for rounding the sharp edges can be carried out before the dielectric layer 40 is applied and after the etching mask layer 62 has been removed (in the case of a stacked capacitor without an etching mask layer 62 ). An SiO ₂ layer approximately 10 Å thick is deposited on the storage electrode 36 by immersing the substrate in a mixed solution of HCL: H ₂ O ₂ : H ₂ O = 1: 1: 6 at a temperature of 60 ° C to 80 ° C carried out. Then the sharp edges of the oxide layer formed during the chemical oxidation process are removed with the buffered HF solution.

The embodiment according to the present invention forms a 2500 Å thick polysilicon layer 56 with hemispherical grains and etches the recesses to a depth of 2000 Å. However, it should be noted that the present invention is not limited to these numerical values. By increasing the thickness of the polysilicon layer 56 and by deeply etching the trenches depending on the selectivity of the polysilicon / dielectric substance, the surface of the storage electrode 36 can continue to grow.

Referring to FIG. 3C, the plate electrode 42 described above is shown. The next process step relates to a reflux process for applying a protective layer such as BPSG (borophosphosilicate glass) or PSG on the substrate 10 in order to level the device. Then opening 50 is formed by a known technique as in FIG. 2 and an N⁺ region 48 is formed through opening 59 . Then, a bit line 52 made of aluminum is formed which is in contact with the N⁺ region 48 .

In the embodiment of the invention, bit line 52 overlaps and extends across the transfer transistor and stacked capacitor 44, and the gate electrode of the transfer transistor is made of polysilicon. However, the invention is not limited to such a structure. In addition, the polysilicon forming the first electrode can be replaced by a recrystallized silicon.

Furthermore, the invention can be used to form a Depression in a semiconductor substrate and then for Formation of a stacked capacitor in the Deepening can be used.

Will continue to be a storage capacitor with high Storage capacity in a limited area requires an isolated substrate, the Capacitor by forming a storage electrode a variety of micro-trenches on the isolated Substrate are formed using a dielectric Layer on this and a plate electrode on the dielectric layer is deposited.

The structure of the storage electrode and its Manufacturing methods are according to the invention of examples. However various other embodiments possible. The following are examples Embodiments of the invention mentioned.  

example 1

Referring to FIG. 6 and 7, another embodiment of the DRAM memory cell is shown according to the invention. A field oxide layer 12 for determining a memory cell area is applied to a P-type semiconductor substrate 10 . The semiconductor substrate 10 may be a P-type trench region. A transfer transistor has an N-type source region 16 adjacent to the field oxide layer 12 , an H-type drain region 20 which is arranged separated by an H-channel region 18 from the source region 16 , a gate oxide layer 22 on the channel region 18 and a gate electrode applied on the gate oxide layer 22 24 adjacent to the source and drain regions 16 and 20 . The transistor is formed in an active region 14 on a main surface of the semiconductor substrate 10 , which is surrounded by the field oxide layer 12 . The gate electrode 24 is connected to a word line 26 . A word line 28 , which is connected to a gate electrode of a transfer transistor formed in an adjacent active region, is formed on the field oxide layer 12 . The gate electrode 24 is insulated from the word line 28 by a first insulation layer 30 . The first insulation layer 30 has an opening 135 through which the drain region 20 of the transfer transistor contacts a bit line 150 . An opening 125 is formed in the first insulation layer 30 and a second insulation layer 190 covers the bit line 150 . The surface of the second insulation layer 190 is leveled. A storage electrode 200 contacts the source region 16 in a source contact region 18 through the opening 125 and determines the storage capacitor region, which extends over the adjacent gate electrode 24 and the word line 28 . According to the invention, an upper region of the storage electrode 20 has a plurality of micro-trenches or micro-cylinders in order to enlarge the surface of the storage electrode as described below. A dielectric layer 40 is coated on the surface of the storage electrode 200 and a plate electrode 400 is coated on the dielectric layer 40 . Such a DRAM memory cell is an application of a DASH (diagonal, active stacked capacitor cell with high-packed memory node) structure, in which a bit line is formed under the memory capacitor. The DASH structure is disclosed in IEDM 1988, pages 596 to 599. In a DRAM memory cell with DASH structure, since the expansion of the storage capacitor in the horizontal direction can be designed without limitation of the bit line design rule, it is easy to compare the storage capacity of the capacitor in a simple process compared to a DRAM memory cell in which the storage capacitor formed under the bit line to enlarge. It should therefore be noted that the storage electrode 200 , which defines the storage capacitor region, is extensible until it touches the storage electrode of an adjacent storage capacitor.

A production method of the DRAM memory cell according to FIG. 7 is described below with reference to FIGS. 8A to 8D, 9A to 9C and 10A to 10C.

Referring to FIG. 8A, a method for forming a pair of transfer transistors with bit line 150 will be described. The process before forming bit line 150 is the same as the process described in FIG. 3A. Since the bit line 150 is formed on the insulation layer 30 , the surface of the first insulation layer 30 is preferably flattened using a reflow method such as BPSG. Then, part of the first insulation layer 30 formed on the drain region 20 is removed by conventional photoetching to form the opening 135 through which the drain region 20 of the transfer transistor is connected to the aluminum bit line 150 .

According to Fig. 8B, the bit line 150,190 applied a second insulation layer of BPSG or PSG having a thickness of about 5000 Å on the substrate and the surface leveled by backflow after forming. The second insulation layer 190 is generally made of silicon oxide or a stacked layer of silicon oxide and silicon nitride. In both cases, the surface flattening process is carried out after the second insulation layer 190 has been applied. Alternatively, the leveling process can be accomplished by depositing a silicon oxide layer on the substrate by depositing resistive particles and then etching with a controlled etch ratio of resistive silicon oxide layer.

Referring to FIG. 8C, the second insulating layer 190 is 125, the surface of the source region 16 through the second insulating layer 190 and the first insulation layer 30 is introduced, the opening for exposing a part by a konventionales photoetching after completion of the formation and the leveling. After the photoresist to form the opening 125 is removed, the 2500 Å thick polysilicon layer 56 with hemispherical grains on its surface is formed on the second insulation layer 190 . This contacts the surface of the source region 16 , as has been described in accordance with FIG. 3B. After the polysilicon layer 56 has been formed, the arsenic ion implantation for doping the polysilicon layer is carried out in accordance with FIG. 3B. Then a mask layer 250 of SiO _{2 is} deposited on the doped polysilicon layer 56 with a thickness of approximately 300 to 500 Å by conventional CVD. The dielectric substance with a high dielectric constant, such as Si ₃ N ₄ or Ta ₂ O _5, can be used as the mask layer 58 . However, when considering the etching process for forming the micro-trenches, it is preferable to use a dielectric substance with a high selectivity with respect to polysilicon / dielectric substance. After the mask layer 250 has been deposited, a structuring method for determining the storage capacitor area is carried out by conventional photoetching.

The method for forming the micro-trenches according to the present invention is described in detail below with reference to FIGS. 9A and 10A, in which enlarged representations of various embodiments of the rounded regions 500 according to FIG. 8C are shown accordingly. FIG. 10A shows the arrangement of the grains in the case where the distance S between the hemispherical grains is greater than 2 times the thickness X of the masking layer 250 made of SiO ₂ (i.e., S 2X), and FIG. 9A shows the arrangement of FIG Grains at a distance S = 0.

According to FIG. 9A, an SiO ₂ etch-back process is carried out on the polysilicon oxide layer 250 , as is used to form a side wall according to the known LDD MOSFET (MOSFET with lightly doped drain) production, in order to have a thickness X (= 300 to 500 Å) the SiO ₂ layer 250 to stop the etching. This procedure is the same as the procedure of Fig. 4B. When the SiO ₂ layer 250 has been deposited, the result of the etch back process is that the etch mask 251 remains in the valleys and the top portions 222 of the grains 221 are exposed because the SiO ₂ layer is in the valleys between the polysilicon grains 221 is applied thicker.

According to Fig. 9B, an anisotropic etching is performed with a selectivity with respect to polysilicon / SiO ₂ is equal to 40 to completely aufzuätzen the polysilicon layer 56 of 2500 Å thick, in order to expose the second insulating layer 91 outside the region below the etching mask 251st Such etching is carried out using the model No. "Rainbow 4400" from LAM Co., at a power of 200 watts at an atmospheric pressure of 350 millibars and when using a mixed gas of HBR (hydrogen bromide): Cl ₂ = 40SCCM: 120SCCM . As a result, the micro-trenches 230 are formed with a screw hole-like structure that penetrate through the polysilicon layer 56 . It should be noted that the embodiment is different from the method of Fig. 4C in that the recess depth in Fig. 4C is 0.2 µm, while the hole depth of this embodiment is 2500 Å. After the screw trench-like micro-trenches 230 are formed, a doped, thin polysilicon layer 240 is uniformly applied to the inside and outside of the micro-trenches 230 by LPCVD at a rate of 20 to 25 A / min in a decay gas SiH ₄ at over 600 ° C what temperature polysilicon is formed. Since the effective thickness of the thin polysilicon layer 240 should be less than half the diameter (0.07 to 0.15 µm) of the hemispherical grains 221 to ensure a sufficient surface area of the storage capacitor, the thickness of the thin polysilicon layer 240 is 300 to 700 Å . A patterning process is applied to the thin polysilicon layer 240 deposited over the entire surface of the substrate by conventional photoetching to define the storage capacitor area and form the storage electrode 200 . As a result, the storage electrode 200 has the polysilicon layer 56 and the thin polysilicon layer 240 has a plurality of micro-trenches 230 .

Referring to FIG. 9C, the storage electrode is a Si ₃ N ₄ layer of about 70 Å thickness on the surface of the polysilicon layer 240 (or the storage electrode 200) was formed by conventional CVD 200 after formation. Further, a dielectric layer 40 is formed on an NO layer (or an ONO layer when a naturally oxidized SiO ₂ layer is added) of 20 Å in thickness SiO ₂ by heat oxidation of the surface of the deposited Si ₃ N ₄ . Then, the polysilicon layer 400 of doped polysilicon is deposited on the dielectric layer 40 to complete the fabrication of the storage capacitor shown in FIG. 8D.

FIG. 10A to 10C show another embodiment of the storage capacitor according to the invention. In this case, after etching back the mask layer 250, an etching mask layer 251 is formed on the side walls 225 of the corresponding grains 221 according to FIG. 10A. The upper regions 222 of the grains 221 and the surface regions 226 of the polysilicon layer 56 applied between the grains 221 are exposed. Thereafter, nanometer scale etching is performed on the polysilicon layer 56 to expose the second insulation layer 190 and the thin polysilicon layer 240 applied to the entire surface of the substrate. Then, the storage electrode 200 is structured according to FIG. 10B. Furthermore, the dielectric layer 40 and the plate electrode 400 are successively applied to the storage electrode 200 .

It should be noted that even in the case where the distance between the hemispherical grains is not uniform, the storage capacitor can be manufactured by the above method according to the invention. Furthermore, it should be noted that precise control of the etching depth for the formation of the micro-trenches is not necessary, since after the complete removal of the polysilicon 56 except for portions under the etching mask layer 251 with a high selectivity for polysilicon / silicon oxide, the thin polysilicon layer 240 is formed to form the storage electrode 200 becomes.

In the above, it would be assumed as an example that the storage electrode uses silicon oxide used as an etching mask. However, since the etch mask layer 251 does not play the role of the dielectric layer and cannot increase the surface area of the storage capacitor, the etch mask layer 251 is preferably removed by performing anisotropic etching and immersing in a buffered RF solution.

Although the embodiment described according to FIG. 7 shows a DRAM memory cell with DASH structure in which the bit line is arranged under the storage capacitor, the present invention is not restricted to such a structure. For example, this embodiment can also be used with a DRAM memory cell according to FIG. 2. In this case, before the polysilicon layer 56 serving as the storage electrode 36 is applied, the insulation layer 30 formed below the polysilicon layer 56 should be leveled.

Example 2

Another embodiment of the invention is described below according to FIGS. 11A to 11D and 12A to 12I.

Referring to FIG. 11A, a polysilicon layer is deposited 56 of 2500 Å thickness having hemispherical grains on its surface on the second insulating layer 190 and contacts the source region 10 through the opening 125. Then an arsenic ion implantation is performed. According to Fig. 11B, a SiN layer 330 is deposited from 20 to 500 Å thick on the polysilicon layer 56 by conventional LPCVD and an SOG layer 340 of about 2000 Å thickness is deposited on the SiN layer 330. Because the thickness of the SOG layer 340 is much greater than the height of the hemispherical grains, the rough surface of the polysilicon layer 56 is completely covered by the SOG layer 340 .

FIG. 12A shows an enlarged illustration of the rounded region of FIG. 11B. In FIG. 12B, after the SOG layer 340 has been applied and leveled, it is etched back or dry etched to expose upper regions 331 of the hemispherical grains 221 , the surface of which are covered with the SiN layer 330 . The exposure of the SiN layer 330 can be precisely determined by controlling the time and the extent of the etching. In Fig. 12C, the exposed SiN layer 331 is removed by dry etching using the model number "Rainbow 4400" from LAM Co. or by wet etching with phosphoric acid (H ₃ PO ₄ ). Then, the remaining SOG layer 342 as shown in FIG. 12D is completely removed by immersing the substrate in a BOG (Buffered Oxide Etchant) solvent for about one minute.

Referring to FIG. 12E, the upper portions of the hemispherical grains 221 of the exposed polysilicon layer 56 are oxidized to form an oxide film 231 of 100 to 1000 Å thickness. This oxidation process can be carried out using dry O ₂ or immersing the substrate in a mixed solution of HCL: H ₂ O ₂ : H ₂ O = 1: 1: 6 at 60 to 80 ° C. At this time, a thin oxide layer 232 is also formed on the SiN layer 330 . However, this can be removed simply by immersing the substrate in BOE solution for about 10 seconds. The oxide layer 231 is used as an etching mask for forming the micro-trenches. After the oxidation process, the SiN layer 330 remaining on the hemispherical grains 221 and the polysilicon layer 56 are removed by immersing the substrate in H ₃ PO ₄ solution according to FIG. 12F.

Referring to FIG. 11C, the etching mask 231, the polysilicon layer 56 from the oxide layer patterned by conventional photo-etching after forming to form the storage electrode. In the above patterning, it should be noted that since the polysilicon layer 56 is formed above the bit line 51 , the expansion of the surface of the storage capacitor can be designed without restricting the bit line design rule.

Referring to FIG. 12C, an anisotropic etching selectivity for polysilicon / SiO ₂ is equal to 40 with a thickness of 0.2 microns carried out at the polysilicon layer 56 using the etching mask layer 231st Such an etching is performed using the model No. "Rainbow 4400 from LAM Co." carried out at a power of 200 watts under atmospheric pressure of 350 millibars with a mixed gas of HBR (hydrogen bromide): Cl ₁ = 40SCCM: 120SCCM. As a result, as shown in FIG. 12G, micro-trenches 224 having a rounded area corresponding to the shape of the grains are formed in the lower part. The bottom surfaces of the micro trenches 224 have a slight slope. With such a structure, the step coverage characteristic of the applied dielectric layer can be improved compared to other structures.

Referring to FIG. 12H are not serving as a dielectric layer etching mask layer 231 is removed to the preparation of the storage electrode to complete the two hundred and first It should be noted that the surface of the storage electrode 201 from which the etching mask layer 231 has been removed is well rounded and has no damaged portions. A dielectric layer is then applied thereon to prevent an undesirable decrease in the breakdown voltage of the storage capacitor.

Then, a Si ₃ H ₄ layer about 70 Å thick is deposited on the surface of the storage electrode 201 by conventional CVD, and a dielectric layer 40 made of an NO layer of 20 Å thick SiO ₂ (or an ONO layer if a natural one) oxidized SiO ₂ layer has been added) obtained by heat oxidation of the surface of the Si ₃ N ₄ layer is applied. Then, a polysilicon layer of doped polysilicon is deposited on the dielectric layer 40 to complete the fabrication of the storage capacitor shown in FIG. 121.

Then a protective layer 46 such as BPSG (borophosphosilicate glass) or PSG is applied to the substrate 10 and a reflux process is carried out to level the device. As a result, the DRAM memory cell shown in Fig. 11D is manufactured.

In the above embodiment, the thickness of the polysilicon layer 220 serving as a storage electrode is 2500 Å and the depth of the trenches is 2000 Å. However, it should be noted that the invention is not limited to these numerical values. The surface area of the storage electrode 201 can be increased by increasing the thickness of the polysilicon layer 56 and by etching the trenches deeper depending on the selectivity of the polysilicon / silicon oxide. Of course, the embodiment according to the invention can be used for a storage electrode in which the distance between the hemispherical grains is zero.

Example 3

Reference is now made to Figures 13A to 13F, 14A to 14H and 15 which illustrate another embodiment of the invention.

Referring to FIG. 13A, a gate electrode 24 and a word line 28 on a semiconductor substrate 10 of a first conductivity type 3A are similar to FIG. Formed. Then a first interlayer insulation layer 600 such as BPSG or oxide layer is applied to the entire surface of the substrate 10 and subsequently leveled. A first insulation layer 610 of 500 to 1000 Å in thickness such as a nitride layer and a second insulation layer 620 of 1000 to 2000 Å in thickness such as an oxide layer are successively applied to the first interlayer insulation layer 600 . The first nitride insulation layer 610 is used as an etch stop layer in the subsequent process.

According to Fig. 13B, a method of forming a first contact hole CH1 and a first conductor layer 56 is shown made of polysilicon. A resist pattern of a desired size is formed on the second insulation layer 620 by the subsequent process of applying the resist. The photoresist is then exposed or structured. Using the photoresist pattern, first and second insulation layers 610 and 620 and first interlayer insulation layer 600 are etched away to form the first contact opening CH1, which connects the storage electrode, which is used as the first electrode of the storage capacitor, to the source region 16 of the transfer transistor. After removal of the photoresist pattern, a doped polysilicon layer 56 with a thickness of 2000 to 6000 Å with hemispherical grains on its surface is applied to the entire surface of the substrate 10 . In Fig. 13B, the grains are connected to adjacent grains, that is, the distance S between the grains is zero as in Figs. 4A and 9A. However, the present invention can also be used for a storage electrode in which the grains are spaced from each other, as shown in the previous embodiments.

Referring to FIG. 13C, a method for forming a pattern of a polysilicon layer and a third insulating layer 630 is illustrated. First, a photoresist pattern of a desired size is formed on the first polysilicon wiring layer 56 by the following method of applying the photoresist. The photoresist is then exposed or structured. By using the photoresist pattern, the first polysilicon line layer 56 is etched away to form pattern 56 'of the first polysilicon layer with the hemispherical grains on its surface. The photoresist pattern is then removed and the third insulation layer 630 made of a 300 to 1000 Å thick HTO (high temperature oxide) layer is applied to the entire surface of the substrate 10 .

According to Fig. 13D illustrates a method for etching the third insulating layer 630. An etch back is performed on the substrate 10 to expose the uppermost regions of the grains of the polysilicon pattern 56 '. As a result, the third insulation layer 630 remains between the grains. Furthermore, the third insulation layer 630 'remains on the side walls of the polysilicon pattern 56 '.

Referring to FIG. 13E, a method is shown for forming the storage electrode. By using the remaining third insulation layer 630 'as a mask, the polysilicon pattern 56 ' is etched away to form a storage electrode 202 . As a result, the storage electrode 202 is formed, which has micro-trenches or micro-cylinders in the surfaces of the polysilicon pattern 56 'on which the remaining third insulation layer 630 ' is not applied. Furthermore, during the process of etching the storage electrode, the side wall regions of the polysilicon pattern 56 'are etched obliquely. In this case, the pattern etching of the polysilicon pattern 56 'is carried out by a mixed gas of HBR or Cl ₂ , which has a high etching selectivity with regard to polysilicon / oxide.

Referring to FIG. 13F, a method is shown for forming the storage capacitor. According to the method of FIG. 13E, remaining third insulating layer used as a mask 630 'is removed by wet etching using BOE or a buffered HF solution. Subsequently, a dielectric layer 40 with ONO (oxide nitride oxide) or NO structure is applied to the entire surface of the exposed storage electrode 202 . Next, a second conductive layer of doped polysilicon is deposited on the dielectric layer 40 and patterned to form the plate electrode 400 . As a result, the process of forming a storage capacitor with a storage electrode 202 , the dielectric layer 40 and the plate electrode 400 is completed. A bit line is then formed by exposing the upper region of the drain region 20 (not shown). The bit line can be formed before the first line layer for the storage electrode 202 is formed.

A further embodiment of the invention is illustrated below with reference to FIGS. 14A to 14H.

The method according to FIG. 14A is the same as the method according to FIG. 13A. In FIG. 14B, a first contact opening CH1, the polysilicon layer 56 and the third insulation layer 640 are formed in succession as described in FIG. 13B. Next, a resist pattern 700 is formed with a desired size on the third insulating layer 640 by a subsequent process of applying, exposing and photoetching the photoresist in FIG. 14C. Then, by using the photoresist pattern as a mask, the third insulation layer 46 and the polysilicon layer 56 are etched out to form a polysilicon pattern 56 a according to the drawing. The third insulation layer 640 is further etched along the polysilicon pattern 56 a by wet etching using BOE or a buffered HF solution to form a third insulation layer pattern 46 a. In this case, the etching depth for forming the third insulation layer pattern 640 a is approximately 500 to 1000 Å deep.

Referring to FIG. 15, the area A is in the following Fig. 14C explained in detail. The polysilicon layer pattern 56 a and the photoresist pattern 700 have the same size. The third insulation layer pattern 640 a is smaller by a predetermined width than the polysilicon layer pattern 56 a along its circumference. In FIG. 14D, the photoresist pattern 700 of FIG. 14C is removed and the polysilicon layer pattern 56 a is etched away using the third insulation layer pattern 640 a as a mask in order to form the regions B along the circumference of the polysilicon layer pattern 56 a. In FIG. 14E, the third insulation layer pattern 640 a is removed and a fourth insulation layer 650 made of a 500 to 1000 Å thick HTO film is applied to the entire surface of the substrate 10 .

A method of removing the third insulation layer pattern before applying the fourth insulation layer is negligible. Next, in FIG. 14F, etching back is performed on the substrate 10 on which the fourth insulation layer 650 is formed in order to obtain a fourth insulation layer pattern 650 a between the grains and on the side walls of the polysilicon layer pattern 56 a. It should be noted that a spacer 651 is formed on the area B from the remaining fourth insulation layer. Spacer 651 is used to form microcylinders along the side walls of the storage electrode in a later process step. In Fig. 14C, the polysilicon layer pattern 56 a is etched to a thickness of 4000 A by the fourth insulation layer pattern 650 a is used as a mask to the structure of the storage electrode to complete 204 having a plurality of micro grooves and / or micro cylinders. In FIG. 14H, the remaining fourth insulation layer pattern 650 a and the spacer 651 removed. Then, the storage electrode 204 is coated with the dielectric layer 40 and doped polysilicon is deposited on the dielectric layer 40 to form the plate electrode 400 . This completes the process of manufacturing the storage capacitor.

Even if different structures are one Storage capacitor shown according to the invention and described above are different Modifications within the scope of the present invention  possible. For example, the present Invention to form a depression in one Semiconductor substrate and then to form one Stack capacitor used in the recess will. Furthermore, in the cases where a Capacitor with a high storage capacity a limited area of an isolated substrate is required, this can form one Storage electrode with a variety of micro-trenches be met according to the invention, one dielectric layer is formed thereon a plate electrode is applied.

As can be seen from the above description, has a storage capacitor according to the invention a storage electrode with an enlarged Surface in a limited area on and consequently, the storage capacity is increased. There still micro-trenches and / or micro-cylinders relative formed evenly, will be high Reliability of the capacitor achieved. In the end the method according to the invention is comparative easy.

Claims (33)

A capacitor having a first electrode formed on a conductive layer formed on a limited area of a substrate and a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer, characterized in that the first Electrode has a plurality of micro-trenches and / or micro-cylinders, which are formed on a predetermined surface of the conductive layer. 2. The capacitor according to claim 1, characterized, that the conductive layer is a polysilicon layer is. 3. A semiconductor memory cell with one Transfer transistor, the source and drain regions of a second conductivity type based on a Semiconductor substrate of a first conductivity type are formed, a first conductive layer, which adjacent to the source and drain regions and from a channel region through a gate oxide layer isolated between the source and drain areas is formed, and a first insulation layer, which is used to insulate the first conductive layer this covers, has and with a Storage capacitor, the one on the substrate field oxide layer formed adjacent to the  Source region, a first electrode, which the Source area contacted and a predetermined Area of the first conductive layer overlaps and extends above the field oxide layer, one that first electrode covering dielectric layer and a second covering the dielectric layer Has electrode, characterized in that a Variety of micro trenches and / or micro cylinders the first electrode are formed. 4. The semiconductor memory cell according to claim 3, characterized in that the micro-trenches and / or Microcylinder hemispherical in floor areas are trained. 5. One on a limited area of a substrate formed capacitor with a first electrode formed on an insulating layer, conductive Layer, one formed on the first electrode dielectric layer and one on the dielectric layer formed second electrode, characterized, that the first electrode has a variety of micro-trenches and / or microcylinders of the conductive layer has, wherein the conductive layer in Bottom regions of the micro trenches and / or micro cylinders is in contact with the insulation layer and one thin, conductive layer the conductive layer in the Inside and outside of the micro trenches and / or Micro cylinder covered.   6. The capacitor according to claim 5, characterized, that the thin, conductive layer of polysilicon is. 7. The capacitor according to claim 5, characterized, that the micro trenches and / or micro cylinders a Have screw-hole-like structure that extends through the conductive layer. 8. A semiconductor memory cell with one Transfer transistor, which comprises: source and Drain areas of a second conductivity type, the on a semiconductor substrate of a first Conductivity type are formed; a first, conductive layer adjacent to the source and Drain areas and from one channel area through one Insulated gate oxide layer, which between the source and drain regions are formed; and a first Insulation layer used to insulate the first, conductive layer covered this, and with a Storage capacitor, comprising: a second, conductive layer that contacts the drain area and above the first insulation layer extends; a second layer of insulation that the second, conductive layer for their insulation covered; one formed on the substrate Field oxide layer adjacent to the source region; one first formed from a conductive layer Electrode which contacts the source region and a predetermined range of the first conductive Layer overlaps and over the field oxide layer  extends; a covering the first electrode dielectric layer; and one the dielectric Layer covering second electrode, characterized, that the first electrode has: a plurality of Micro trenches and / or micro cylinders of the conductive Layer, this in floor areas of the Micro trenches and / or micro cylinders in contact with the Insulation layer, and a thin, conductive Layer which is the conductive layer inside and Exterior of the micro trenches and / or micro cylinders covered. 9. The semiconductor memory cell according to claim 8, characterized, that the first and second conductive layers are one Word line or a bit line is. 10. The semiconductor memory device according to claim 8th, characterized, that the micro trenches and / or micro cylinders a Have screw hole-like structure, which by the conductive layer passes through. 11. The semiconductor memory cell according to claim 8, characterized, that the thin, conductive layer of polysilicon is. 12. The semiconductor memory cell according to claim 8, characterized,  that the second insulation layer is a leveled one Surface. 13. A semiconductor memory cell with one Transfer transistor, which comprises: source and Drain areas of a second conductivity type, which on a semiconductor substrate of a first Conductivity type are formed; a first, conductive layer adjacent to the source and Drain areas and from one channel area through one Insulated gate oxide layer, which between the source and drain region is formed; and a Insulation layer which is the first conductive Layer for their insulation, and covered with a Storage capacitor comprising: one on the Field oxide layer formed substrate, which is adjacent is arranged to the source region; one out of one conductive layer formed, the first electrode contacted the source region and a predetermined one Covered area of the first conductive layer and extends above the field oxide layer; one dielectric layer covering the first electrode; and a second one covering the dielectric layer Electrode, characterized, that the first electrode has a variety of micro-trenches and / or microcylinder of the conductive layer has, wherein the conductive layer in Bottom regions of the micro trenches and / or micro cylinders is in contact with the insulation layer, and a thin, conductive layer the conductive layer in the Inside and outside of the micro trenches and / or Micro cylinder covered.   14. The semiconductor memory cell according to claim 13, characterized, that the micro trenches and / or micro cylinders a Have screw hole-like structure that the conductive layer penetrates. 15. The semiconductor memory cell according to claim 13, characterized in that the thin, conductive Layer is made of polysilicon. 16. A method of forming a storage electrode having a plurality of micro trenches and / or micro cylinders with the following steps:
Forming grains on a surface of the storage electrode;
Forming an etch mask layer on side walls of the corresponding grains; and
Performing an anisotropic etching with the etching mask layer as a mask. 17. The method according to claim 16, characterized by the further step:
Removing sharp edges of the micro trenches and / or
Micro cylinder after the step of performing the anisotropic etching. 18. A method for producing a storage electrode with a plurality of micro-trenches and / or micro-cylinders, characterized by the method steps:
Flattening a surface of an insulation layer on which the storage electrode is formed;
Forming grains on a surface of the storage electrode;
Forming an etch mask layer on side walls of the corresponding grains;
Performing anisotropic etching using the etch mask layer as a mask to form screw hole-like openings that pass through the storage electrode to expose the insulation layer; and
Form a thin, conductive layer of polysilicon covering the inside and outside of the screw hole-like openings. 19. A method of manufacturing a storage capacitor for use in a semiconductor memory device using a polysilicon layer having a plurality of hemispherical grains, characterized by the following steps:
Forming an etch mask layer on the surface of the hemispherical grains;
Structuring the polysilicon layer;
Performing an anisotropic etching using the etching mask layer as a mask; and
Remove the etch mask layer to form a storage electrode. 20. The method according to claim 19, characterized by the further steps:
Oxidize the top surface of the hemispherical grains to form the etch mask layer on them. 21. The method according to claim 19, characterized by the further step:
Performing anisotropic etching of the polysilicon layer between the hemispherical grains. 22. The method according to claim 19, characterized by the further steps:
Forming a dielectric layer on the storage electrode; and
Form a plate electrode on the dielectric layer. 23. A method for forming a first electrode of a storage electrode in a semiconductor memory device comprising:
a transfer transistor, which has:
Source and drain regions of a second conductivity type, which are formed on a semiconductor substrate of a first conductivity type;
a first conductive layer adjacent to the source and drain region, which is insulated from a channel region formed between the source and drain region by a gate oxide layer, and
a first insulation layer, which covers the first, conductive layer for its insulation, and with a storage capacitor, which comprises:
a second conductive layer that contacts the drain region and extends above the first insulation layer; a second insulation layer covering the second conductive layer for insulation thereof; a field oxide layer formed on the substrate and disposed adjacent to the source region;
wherein the first electrode is formed from a conductive layer that is in contact with the source region, the first electrode overlapping a certain portion of the first conductive layer and extending above the field oxide layer;
a dielectric layer covering the first electrode; and
a second electrode covering the dielectric layer, characterized by the following method steps:
Forming a polysilicon layer contacting the source region with a plurality of hemispherical grains on the surface thereof, which covers the second insulation layer;
Forming an etch mask layer on the top surface of the hemispherical grains;
Structuring the polysilicon layer;
Performing an anisotropic etching using the etching mask layer as a mask; and
Remove the etch mask layer. 24. The method according to claim 23, characterized by a further step:
Oxidize the top surfaces of the hemispherical grains to form the etch mask layer thereon. 25. The method according to claim 23, characterized by a further step:
Performing anisotropic etching of the polysilicon layer between the hemispherical grains. 26. A method for producing a storage electrode of a storage capacitor over a leveled insulation layer on a semiconductor substrate with an active area, characterized by the following steps:
Forming a polysilicon layer on the insulation layer which contacts the active region and has a plurality of hemispherical grains arranged at a predetermined distance from each other;
Forming a SiN layer on the polysilicon layer;
Applying a leveled, spin-coated glass layer on the SiN layer;
Performing an etch back on the spun glass layer to expose the SiN layer on the top surfaces of the hemispherical grains;
Removing the exposed SiN layer to expose the top surfaces of the hemispherical grains;
Oxidizing the top surfaces of the hemispherical grains to form an etch mask layer thereon;
Performing anisotropic etching of the polysilicon layer using the etching mask layer as a mask; and
Remove the etch mask layer. 27. The method according to claim 26, characterized by the further step:
Performing anisotropic etching of the polysilicon layer between the hemispherical grains. 28. A method for producing a storage electrode of a storage capacitor over a leveled insulation layer formed on a semiconductor substrate with an active area, characterized by the following steps:
Forming a first intermediate layer of the insulation layer from the first and second insulation layers successively on the flattened insulation layer;
Forming a contact opening through the interlayer insulation layer and the first and second insulation layers to expose the active area;
Forming a polysilicon layer on the second insulation layer which contacts the active region and has a plurality of hemispherical grains;
Etching the polysilicon layer to form a pattern;
Forming an insulation layer on the semiconductor substrate covering the polysilicon layer and etching back the insulation layer to form an etch mask pattern with the remaining parts of the insulation layer;
Etch the polysilicon layer using the etch mask pattern as a mask. 29. The method according to claim 28, characterized, that the first insulation layer is a nitride layer is. 30. The method according to claim 28, characterized by the further step:
Forming the etch mask pattern between the hemispherical grains and the sidewalls of the polysilicon layer pattern. 31. A method for producing a storage electrode of a storage capacitor on a leveled insulation layer on a semiconductor substrate with an active area, characterized by the steps:
Forming a first interlayer insulation layer, a first and a second insulation layer sequentially on the leveled insulation layer;
Forming a contact opening through the interlayer insulation layer and the first and second insulation layers to expose the active area;
Forming a polysilicon layer on the second insulation layer that contacts the active region and has a plurality of hemispherical grains;
Forming a third insulation layer on the polysilicon layer;
Etching the polysilicon layer and the third insulation layer to form a pattern;
Etching predetermined portions of the patterned third insulation layer to form a first etch mask pattern from the third insulation layer;
Etching the polysilicon layer to a predetermined thickness using the first mask layer as a mask;
Applying a fourth insulation layer on the entire surface of the semiconductor substrate;
Etching back the fourth insulation layer to form a second etching mask pattern with remaining parts of the fourth insulation layer;
Etch the polysilicon layer using the second etch mask pattern as a mask. 32. The method according to claim 31, characterized, that the first etch mask pattern has a smaller width than the patterned polysilicon layer along has the scope. 33. The method according to claim 31, characterized, that the second etching mask pattern between the hemispherical grains and the side walls of the structured polysilicon layer is formed.