DE4039849A1 - Circuitry generating data clock signals for magnetic disc store - uses PLL with ring oscillator based upon delay stages - Google Patents

Abstract

A combined PLL is used for the generation of both write (WCK) and read (RCK) control pulses. The unit has a v.c.o. circuit (3) with a ring of delay stages (41-4n), each of which has an adjustable valve (deltat). The output of the last stage is fed back to form the ring oscillator. The delay stages connect to a selector circuit (9) to generate the read clock signal which is also fed to a phase detector (10). A further phase detector (7) provides the input to the oscillator. ADVANTAGE - Common circuit for read and write pulses.

Description

The invention relates to a circuit arrangement for Er testify to data clock signals in a magnetic disk memory according to the preamble of claim 1.

It is generally known, e.g. B. also from C.D. Mee + E.D. Daniel "Magnetic Recording", Vol. II, McGraw-Hill, New York, 1988, Pages 85 ff. That to perform the two operating functions "Read" and "write" in a magnetic disk memory, respectively Clock signals for the timing of these processes be done. So z. B. in the reading process of one Magnetic head emitted analog read signals in a read data channel prepared and digitized. The individual impulses of these digitized read data are temporally on the Peak values of the analog signals emitted by the magnetic head directed, but often do not come to the correct bit times. This time shift of the up the pulse edges can occur due to peak value shifts in the Read signal, but also other influences, such as tolerances Disk speed, etc. For further ver Working such a series of pulses, for example in the Central unit of a connected computer, but must Individual pulses should be standardized so that they are predetermined Times occur. For this synchronization with a pre benen clock grid must a read clock signal from the read data be directed. The same applies to the writing process. Also here the received from the magnetic disk storage and data pulses to be recorded synchro with write clock pulses nized to make it clear and error-free again re magnetic recording.

Write and read channels in magnetic disk storage  which are generally designed separately and therefore also have each have their own circuit arrangements for generating the respective gene data clock signals, d. H. of the read or write clock. Phase locked loops are used to obtain the data clock signals se, often referred to as PLL (Phase Lock Loop) circuits, used. For the present application, both Analog as well as digital phase locked loops are known. Analogue Phase locked loops require frequent readjustments therefore expensive in terms of downtime and maintenance wall. In addition, they are occasional in terms of their Control function not sufficiently stable.

Especially in the present application for magnetic layers digital phase locked loops or hy are therefore also saved bride circuit arrangements become known. Is common common to all these circuits that the phase locked loop in essentially of a phase detector and a controlled, preferably there is a voltage-controlled oscillator. It is this oscillator to a setpoint, mostly based on egg internal clock. With the help of the phase detector becomes an actual value of the current frequency and phase of the Data clock of the relevant data signals determined. From the A comparison of the actual and target values is made in the event of a deviation A new setpoint is also set and the oscillator is open this set.

Phase locked loops are relatively complex and complex because they are in this application must meet various requirements sen. You have to have a certain pulling behavior with it in the event of long-term changes, e.g. B. the scanning speed speed during a reading process, such a fluctuation in one can follow a certain area. On the other hand, they should have defined persistence, so little swan of the data impulses in relation to their target time at the Er Generation of the corresponding clock pulses is not taken into account ben. In addition, phase locked loops for this application have a favorable single-phase behavior, so that  changes in the operating functions or after operational interruptions of the process if possible quickly set back to the frequency of the data stream.

The present invention is therefore based on the object to create a circuit arrangement of the type mentioned fen, with which both the write and the read pulse for egg NEN magnetic disk storage in a common circuit circle with great long-term stability, d. H. so on digital Ways is generated.

In a circuit arrangement of the type mentioned this task according to the invention in the characteristics of Main claim described features solved.

This solution has the advantage that it has little circuitry is more complex than conventional solutions with individual len phase-locked loops for the read and write channels of the Ma disk storage. In addition, it shows a cheap Single phase behavior, since it can be assumed that Write and read operations with essentially the same target frequency are executed, even if they are tolerant is. Only the phase positions normally differ se, the compensation of a phase offset is possible without any problems Lich, so that the circuit arrangement according to the invention a gun shows constant single-phase behavior.

According to a development of the invention, the voltage is controlled oscillator circuit from a plurality of to one Ring-connected delay elements with controlled setting barely delay time built up. Such training of voltage-controlled oscillator with a ring structure results a phase adjustment range that is not limited to 2π.

According to another development, the inventor is preferred a servo clock signal as a reference signal for the setting the target frequency of the voltage controlled oscillator  det. Changes in the frequency range run in normal loading drive state only very slowly. Control movements to stop the low-frequency loading is therefore equal to a frequency offset assign richly. In contrast, in the part of the circuit Order that serves to generate the reading pulse, phase repositioning be balanced as quickly as possible. With this part of the Circuit arrangement, the bandwidth is therefore much higher than the bandwidth of the part of the circuit arrangement that is single frequency offsets. Therefore, low-frequency Disruptions resulting from the low-frequency control movements to compensate for frequency deposits, from the circuit part to Generating the reading bar can be easily captured without the Control stability of the overall arrangement to affect.

Further advantages and properties of the solution according to the invention result from the following description of an embodiment Example, which is based on the drawing. It shows the only figure is a block diagram for an inventive trained circuit arrangement for the common generation of Read clock and write clock signals in a magnetic disk game cher.

As a possibility in this embodiment assumed that - as is often the case - in magnetic disk storage a surface of the storage disks for permanently registered Servo information is reserved, in which then also a measure formation is included, which is the instantaneous speed of the magnet disk storage is proportional. The servo information is in in this case read with an individual servo magnetic head and then processed in a servo channel. It will also the corresponding clock information is recovered.

Such a preparation of the servo information read is quite common in conventional magnetic disk storage, moreover, it is also not essential as such in the present case. In the drawing, the Servoka channel 1 is therefore only shown in broken lines as a block. From the servo channel 1 , the control circuit is supplied with a servo clock signal SCK as one of the reference values for the generation of data clock signals, ie a write clock signal WCK or a read clock signal RCK.

In a similar form, a reading channel 2 is indicated schematically in the drawing. The reading channel 2 comprises, as far as is of interest here, at least one data head for reading information stored on a data surface of the magnetic disk memory and an amplifier arrangement in which an analog signal emitted by the magnetic head is preamplified. This preamplified signal is supplied to the circuit arrangement shown in the drawing in the form of an analog read signal RS as a further reference signal.

The heart of the circuit arrangement shown in the drawing is a clock generator 3 for generating the write clock signal WCK and the read clock signal RCK. This clock generator 3 comprises a voltage controlled oscillator. This oscillator is made up of a plurality of delay elements 41 .. 4 i .. 4 n, n being preferably an odd number. These delay elements are connected together in series to form a ring via crosspoints 5 . The delay time Δt of the delay elements 41 .. 4 n is variable and can be set by an analog control voltage Uc. From digital technology there are a number of solutions available to those skilled in the art as execution forms for such voltage-controlled delay elements, without limitation, for example, a Univi brator with built-in voltage-controlled current source would be named.

This ring structure of the delay elements 41 .. 4n forms an oscillator with an adjustable oscillator frequency fo, which according to relationship ( 1 ) is inversely proportional to the selected delay time Δt:

(1) fo = 1 / 2nΔt,

n is the number of delay elements and the individual delay time Δt of each of the delay elements 41 .. 4 n, as stated, a function of the analog control voltage Uc supplied in parallel to the delay elements 41 .. 4 n, in other words Δt = f (Uc).

The write clock signal WCK is coupled out at one of the coupling points 5 and is fed to a frequency reducer 6 in the present circuit arrangement. This frequency converter 6 divides the write clock signal WCK down in frequency and thus adapts it to the systematically predetermined, lower frequency of the servo clock signal SCK. The output signal of the frequency reducer 6 corresponding to the down-divided write clock signal WCK, like the servo clock signal SCK, is supplied to a first phase detector 7 . A number of solutions are also available to the person skilled in the art for the design of such a phase detector; for example, it can be designed as an edge detector. The phase detector 7 outputs an analog output signal which is dependent on the phase offset of its two input signals and is fed to an analog loop filter 8 which is designed as a low-pass filter. The loop filter 8 converts the offered input signal into a bandwidth-limited analog voltage, which is supplied as the control voltage Uc in parallel to the delay elements 41 .. 4 n of the ring oscillator.

The circuit section described above with the delay elements connected to a ring 41 .. 4 n, the frequency reducer 6 , the first phase detector 7 and the analog loop filter 8 forms a first phase locked loop, which generates the write clock signal WCK to the servo clock signal to be fed from the servo channel 1 SCK synchronized as a reference. The ring oscillator formed from the delay elements 41 .. 4n forms a voltage-controlled oscillator in digital technology. Due to its characteristics, the described first phase locked loop has a defined holding capacity in order to regulate low-frequency deposits of the frequency of the write clock signal WCK from the frequency of the servo clock signal SCK, but is too sluggish to respond to phase fluctuations, possibly also a lack of a single pulse of the servo clock signal supplied as a reference variable SCK to respond.

The circuit arrangement shown in the drawing has a further phase locked loop, with which the read clock signal RCK synchronized thereon is derived from the analog read signal RS supplied as a further reference variable. For this purpose, the clock generator 3 has a selection circuit 9 with selection inputs 91 , each of which is connected to one of the crosspoints 5 of the delay elements 41 .. 4 n. As will become apparent from the further description, the selection circuit 9 has the function of a phase actuator which, depending on the phase position of a digital signal supplied to it at an input 92, selects one of the pulse signals offered via its selection inputs 91 and to an output 93 switches through. The signal offered at this output 93 of the selection circuit 9 is the read clock signal RCK.

This read clock signal RCK is also offered to a second phase detector 10 . This digital phase detector 10 also receives the via an analog / digital converter 11 converted into a digital signal analog read signal RS, which is output from the read channel 2 . The second phase detector 10 evaluates the phase offset between the signals fed to its two inputs, the digitized read signal or the read clock signal RCK. It outputs a digital output signal which is dependent on this determined phase offset and which is fed via a digital filter 12 to the input 92 of the selection circuit 9 as a digital selection signal SEL.

Functionally, this means that the oscillator frequency fo of the ring oscillator constructed from the delay elements 41 ... 4 n is used to generate the read clock signal RCK. In this case, however, the phase position of the generated read clock signal RCK is referred to the phase position of the analog read signal RS with the aid of the selection circuit 9 used as a phase actuator. In other words, the read clock signal RCK leads the analog read signal RS in its phase position.

From this it becomes clear that the control movements of the first Phase locked loop with which the write clock signal WCK is generated is, in the second phase locked loop for generating the read clock i impact RCK as disturbances. But this is the case Case not a significant disadvantage and does not lead to one reduced control stability of the circuit arrangement described voltage because the bandwidth of the first phase locked loop to the Er testify to the write clock signal WCK far below the pulp te of the second phase locked loop for generating the read clock i general RCK lies. Because of this bandwidth ratio it is easy to correct the low-frequency disturbances Lich.

Claims (4)

1.Circuit arrangement for generating data clock signals (WCK, RCK) in a magnetic disk memory with a voltage-controlled oscillator circuit ( 3 ) as a clock signal generator, whose output clock signal (WCK or RCK) in a phase detector ( 7 or 10 ) with a reference signal (SCK or . RS) compared and a control signal (Uc or SEL) is derived, which is supplied to the oscillator circuit as a manipulated variable, characterized by an oscillator circuit ( 3 ) for generating a write clock signal (WCK), which is designed as a window generator, and a plurality (n) of clock signal outputs ( 5 ) for delivering clock signals shifted from one another in their phase position by a defined amount (Δt) and which is assigned a first phase detector ( 7 ) to which a servo clock signal (SCK) is supplied as a reference signal and act as a phase actuator by means of selection inputs ( 91 ) connected to the outputs of the oscillator circuit End selection circuit ( 9 ) for generating a reading clock signal (RCK), which is assigned a further phase detector ( 10 ) for evaluating an analog reading signal (RS) as a reference signal. 2. Circuit arrangement according to claim 1, characterized in that the voltage-controlled oscillator circuit ( 3 ) has a plurality of delay elements connected to a ring ( 41 .. 4n) with a controllably adjustable delay time (Δt), the control inputs of which are common to that of the first phase detector ( 7 ) generated control signal (Uc) is led and the coupling points ( 5 ) form the individual clock signal outputs, one of which is selected as an output for the write clock signal (WCK). 3. Circuit arrangement according to claim 1 or 2, characterized in that the first phase detector ( 7 ), whose one input the servo clock signal (SCK) is supplied as a reference signal, is connected via a further input to the output of a frequency reducer ( 6 ), which in turn is connected to the clock signal output of the voltage-controlled oscillator circuit ( 3 ) leading to the write clock signal (WCK) and that an analog loop filter ( 8 ) is provided between the first phase detector and the control input of the voltage-controlled oscillator circuit. 4. Circuit arrangement according to one of claims 1 to 3, characterized in that an analog / Digi tal converter ( 11 ) is provided for converting the analog read signal (RS) into a digital signal, to which a digital phase detector ( 10 ) is connected, the output of which is connected via a digital filter ( 12 ) to the control input ( 92 ) of the selection circuit ( 9 ).