DE4016173A1 - Bit error rate measurement system - has PLL synthesiser coupled in loop to provide signals for data rate - Google Patents

Abstract

The system has a PLL synthesiser (2) that has an output frequency that can be set within a range and is then frequency divided (3) to generate a required bit rate for transmission. A pattern generator (4) coupled to the computer provides a test signal with data works of a particular length. An encoder (5) converts the signals into a standard code format for output (6). Inputs (8) are received by a pulse processing stage (9) that allows the loop around the PLL synthesiser to be closed. A decoder (11) coupled to a comparator (12) allows the bit rate error to be determined. ADVANTAGE - Operation with various codes. Large frequency bandwidth.

Description

The invention relates to a bit error measuring device for determination the bit error rate of digital signal transmission links the preamble of claim 1.

Compared to an analog signal, one is digital over carried information against signal distortion and interference influences much less sensitive. However also digital signal transmission lines usually band limited and subject to fluctuating track damping. There ago it is necessary to transmit the digital signal by a line code so that, for example no equivalent share arises or the number of the maximum successive bits of equal value are limited.

A simple line code is the so-called NRZ code, the the property has that bits with value "1" also in the code the value "1" and bits with the value "0" also in Code have the value "0". Hence the after partly that the frequencies of the NRZ line code up to Fre go zero and on the other hand it can be difficult under certain circumstances is to regenerate the clock from the received NRZ signal, since with longer signal sequences of the same value, the tact formation in the received pulse train is missing.

By recoding an NRZ code, a so-called AMI Code are generated in which consecutive "1" values alternately sent as "+1" and "-1". About one longer period of time, the DC component of the Sig nals to zero. Due to the polarity change from original The continuous "1" values of the bit clock are regenerated  the. The AMI code also has the advantage that the recipient signal can be checked more easily for code violation. With longer "0" sequences, however, the AMI Coding the clock information.

A line code resulting from the AMI code, which as HDB-3 code does not have these disadvantages, since only three "0" elements appear in succession here can. With this code, longer "0" sequences are divided into blocks divided by four bits and sent, the fourth Bit is reversed in each case contrary to the AMI coding regulation.

Such an HDB-3 code is used in particular in the PCM multiplex systems used for voice signal transmission.

To determine the bit error rate of digital signal over transmission lines, e.g. B. microwave links or data lines, it is known to preselected data patterns over the transmission route to send and at the end of the transmission route the number of the disturbed data words with the total number of transmitters Compare data words. The measured value found represents the Bit error rate represents. This measured variable allows a statement about the Quality of the transmission link.

A universal bit error measuring device that is suitable for different Line codes can be used and a clear clock return win with any data word is allowed in the Re gel very expensive. Known bit error measuring devices are sufficient therefore, the bit error rate at fixed clock frequencies to determine zen.

The invention has for its object a bit error measurement device for determining the bit error rate of digital signals  Specify transmission lines that can be produced inexpensively is usable with a large clock frequency bandwidth and used for different line codes and data words is cash.

This object is achieved by the inven in claim 1 solved. Advantageous developments of the invention are specified in subclaims.

The invention enables the use of a bit error measurement advises for clock frequencies up to 50 MHz, whereby without white teres NRZ, AMI or HDB-3 codes can be used nen. The data word length can be chosen freely. Further no specification of the data word used is required Lich.

According to the invention, a random happens in the transmitting part of the device or specifically generated data word of certain length and ge speed over a subsequent encoder and suitable driver against the transmission link to be evaluated ben and repeated constantly. The signal is in the receiving section after going through an input stage and a clock return winnung a decoder, which a comparison stage is downstream. Here are the one after the other incoming data words compared with each other. Dev The data words are checked by a counter registered and on the number of data words transmitted based. The bit error rate of the testing transmission path can be determined.

The invention is illustrated below by means of an embodiment explained in more detail. Show it:  

Fig. 1 is a block diagram of the device A according to the invention,

Fig. 2 is an illustration for generating a clock signal on the transmission side and

Fig. 3 is an illustration for the regeneration of the clock signal on the receiving side.

The device according to the invention shown in FIG. 1 has a computer 1 which serves to control the device, to specify the line code to be selected, the type and length of the data words used and the evaluation of the error signals.

A PLL frequency synthesizer 2 is provided, the frequency of which can be adjusted over a wide range. The frequency synthesizer 2 is a switchable divider 3 downstream, in which the frequency generated by the PLL frequency synthesizer can be divided down to the desired value. By using the PLL frequency synthesizer 2 and the downstream divider 3 , a frequency range of, for example, 100 Hz - 50 MHz can be covered without the need for different oscillator circuits. The bit rate used is determined by the selected frequency.

A measurement word is generated in a pattern generator 4 by the computer using a randomly generated data word or a test data word deliberately chosen by the user. The length of the data word can be freely selected. For better comparison with existing bit error measuring devices, data word lengths of 8, 10, 15 or 23 bits are preferred. The preferred word length depends on the desired clock frequency. The selected data word is clocked at the frequency derived from the divider 3 . The data word is repeated continuously, for example over several minutes up to 24 hours.

In the subsequent line encoder 5 , the pulse sequence generated is converted into the desired line code, e.g. B. an NRZ, AMI or HDB-3 code. This line code can be freely selected depending on the transmission path.

The line encoder 5 is followed by an output stage 6 , which may also consist of several parallel output stages, for example, and which contains adaptation devices, drivers and filters for the transmission link to be tested.

The signal given on the transmission path is switched back before preferably in a remote receiving station, so that it can be returned to the bit error measuring device via a parallel transmission channel. The receiving part consists of an input stage 8 , in which the signal is additionally inverted. In the downstream pulse preparation stage 9 , a pulse of defined length is generated for each change of state of the data stream from "0" to "1". This pulse leads to a clock acquisition circuit 10 . The clock obtained from the received signal can be used directly for clock control of the downstream devices. However, since the number of the maximum permitted, depending on the following identical conditions depends on the line coding used, it is not guaranteed in every case that a clock signal can be derived from the received signal. The invention therefore provides that the PLL frequency synthesizer used on the transmit side is additionally followed by a programmable divider 7 , which is triggered on the one hand by the clock signal output from the clock acquisition circuit 10 or the pulse processing stage 9 , but on the other hand, in the absence of this clock signal itself is retriggerable. In this case, the output signal of the programmable divider 7 is used to determine the subsequent reception stages. This means that a clock pulse is also available if there is no change of state in the data stream.

In the decoder 11 , the line coding made in the transmitting part is canceled. Furthermore, the signal is monitored for exceeding the maximum number of consecutive identical states. Every exceeding (AIS) is registered by the computer and displayed. If it is exceeded, the transmission channel is considered to be inoperative and the bit error rate measurement is interrupted for the time the AIS signal is present. Since it is generally not possible in this case for a clock signal to be obtained from the received signal, the device according to the invention nevertheless allows a clock signal to be made available and the possibility to generate a clear AIS signal. The decoder 11 is followed by a comparator 12 , which is designed in particular as a feedback shift register. Herein the two or more successive words are compared and checked for errors. The errors that occur are summed up in the subsequent counter 13 and transmitted to the computer 1 . The evaluation of the measurement result is preferably carried out in the computer 1 with a connected display unit. A power supply unit 14 is also shown, which is used to power the device.

The circuit arrangement shown in FIG. 2 shows the PLL frequency synthesizer 2 with a switchable divider 3 connected downstream. The PLL frequency synthesizer has a PLL control IC 18 which is quartz controlled. The control IC is followed by a variable frequency oscillator 19 , the output signal of which is given via a coupling stage 20 to the switchable divider 3 , which is designed as an 8-bit binary meter. After reaching the maximum count value, a pulse is given to the pattern generator 4 . The division rate of the divider 3 and the frequency of the PLL frequency synthesizer can be specified or set by the computer 1 used .

Fig. 3 shows the circuit arrangement for the regeneration of the clock signal on the receiving side. In the input stage 8 an invented signal is additionally formed from the received signal, the edges of which are slightly apart in time. If both signals are routed to the NOR gate 15 a, a pulse sequence arises at the output of this NOR which is determined by the time difference between the directly received and the inverted received signal. The clock frequency does not change. The pulse length depends on the gates used and the clock frequency. To compensate for this pulse length shift, the pulse sequence present at the output of the N0Rs 15 b is additionally delayed by two NOR gates 16 a and 16 b. Delayed and undelayed pulse trains are given to the NAND 16 c, at the output of which the pulse train that appears has approximately the same pulse length even at different clock frequencies.

At the PLL frequency synthesizer 2 , not only the switchable divider 3 of the transmission stage, but also a programmable divider 7 for the reception stage is connected. This BE is in particular of a 2-stage counter with a Tei division ratio of each of 1: 2 to 1: 16. There is provided a NOR 15 c, via the respective counters 17 a and 17 b in case of overflow of the second counter 17b are reset will. The division ratio of the divider can be set by the computer 1 and depends essentially on the frequency of the PLL synthesizer used, which is, for example, 90-180 MHz.

The output of the first counter 17 a also leads to the input of the second counter 17 b. The output of the second counter 17 b leads to the NOR 15 c, on the other input of which the pulse sequence derived from the NAND 16 c of the input signal is applied. At the output of the NORs 15 c thus a pulse train arises, which can be determined both by the overflow pulses of the counter 17 b and by the pulses of the input signal. For example, if a pulse of the input signal at the output of the NORs 15 c generates a pulse, the counters are reset so that the pulse train running out of the counter 17 b is then synchronized with the pulse train of the output of the NAND 16 c, provided that the clock frequencies of the Divider 17 b originating pulse train and the clock frequency of the input signal essentially agree.

If no clock pulses are present in the received input signal due to the type of code or data word used, the pulse train at the output of NOR 15 c is determined solely by the clocks of counter 17 b until clock pulses are again present from the input signal.

The pulse sequence present at the output of NOR 15 c is fed to the subsequent receiver stages of the input part after inverting, for example to effect the decoding of the line code there or to determine the occurrence of inadmissible code length exceedances (AIS).

Instead of a 2-stage divider 7 , a multi-stage divider can also be used. The division rate determines the possible work area.

Since the frequency derived from the PLL synthesizer 2 is supplied to both the transmitting stage and the receiving stage, there are no clock frequency shifts between the clock frequency of the divider 7 and the clock frequency of the received pulse sequence, provided the division ratios of the divider 3 and the divider 7 are identical. In the event that the transmission frequency cannot be used, for example if a bit error rate is to be determined on a transmission link which is directed only on one side, the synthesizer frequency to be used is to be adapted to the clock frequency of the input pulses. It can be provided that the input pulse train controls the frequency of the PLL synthesizer. Since the frequency of the synthesizer remains fixed at a certain value until the clock frequency can be taken from the input signal again.

The entire circuit arrangement according to the invention can in EPLD technology can be manufactured, so that the circuitry build to a large extent in a manufacturer-related chip can be integrated. In addition to the economic advantage miniaturization can also be achieved in this way.

Reference symbol list

1 microcomputer
2 PLL frequency synthesizers
3 switchable dividers
4 pattern generator
5 line encoders
6 output stage
7 programmable dividers
8 input stage
9 pulse processing stage
10 clock recovery level
11 decoders
12 comparators
13 error counters
14 power supply
15 fast NOR
16 fast NAND
17 2-step programmable counter
18 PLL control IC
19 variable frequency oscillator
20 coupling stage
21 8-bit binary counter
22 8-bit digital multiplexers

Claims (5)

1. Bit error measuring device for determining the bit error rate of digital signal transmission links, with a PLL frequency synthesizer ( 2 ), with its output frequency after frequency division ( 3 ), the clock frequency of a measurement signal is determined, the measurement signal having a selectable data word, which repeats given on the transmission link is, and the signal received at the end of the transmission link is checked for agreement with the emitted signal or correctness, characterized in that the clock of the received signal is regenerated by evaluating the signal transitions of the received signal and that in time areas with missing signal transitions in the received signal the clock is obtained from the divided frequency of the PLL frequency synthesizer ( 2 ). 2. Bit error measuring device according to claim 1, characterized in that a PLL frequency synthesizer ( 2 ) is provided, the output signal of which is guided to a first switchable divider ( 3 ), the output signal of which determines the clock frequency of the measurement signal, and that the output signal of the PLL Fre quenzsynthesizers is also fed to a second programmable divider ( 7 ), the phase position of which is determined by the phase of the clock frequency derived from the received signal at the end of the transmission path. 3. Bit error measuring device according to claim 1 or 2, characterized indicates that the selectable data word is optionally in the NRZ, AMI or HDB-3 line code on the transmission link is given. 4. Bit error measuring device according to one or more of the preceding claims, characterized in that the data signal received at the end of the transmission path after the clock regeneration is fed to a feedback shift register ( 12 ), and that successive data words are compared with one another to match. 5. Bit error measuring device according to one or more of the preceding claims, characterized in that a device ( 11 ) for detecting a signal sequence with a larger number of logical states in the received data signal than is permitted for a selected line code is provided, and that when such occurs Signal sequence the measurement of the bit error rate is interrupted.